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# Scalable energy-efficient magnetoelectric spin–orbit logic

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ARTICLE https://doi.org/10.1038/s41586-018-0770-2
Scalable energy-efficient
magnetoelectric spin–orbit logic
Sasikanth Manipatruni1*, Dmitri E. Nikonov1, Chia-Ching Lin1, Tanay A. Gosavi1, Huichu Liu2, Bhagwati Prasad3,
Yen-Lin Huang3,4, Everton Bonturim3, Ramamoorthy Ramesh3,4,5 & Ian A. Young1
Since the early 1980s, most electronics have relied on the use of complementary metal–oxide–semiconductor
(CMOS) transistors. However, the principles of CMOS operation, involving a switchable semiconductor conductance
controlled by an insulating gate, have remained largely unchanged, even as transistors are miniaturized to sizes of 10
nanometres. We investigated what dimensionally scalable logic technology beyond CMOS could provide improvements
in efficiency and performance for von Neumann architectures and enable growth in emerging computing such as artifical
intelligence. Such a computing technology needs to allow progressive miniaturization, reduce switching energy, improve
device interconnection and provide a complete logic and memory family. Here we propose a scalable spintronic logic
device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear
momentum) combined with magnetoelectric switching. The device uses advanced quantum materials, especially
correlated oxides and topological states of matter, for collective switching and detection. We describe progress in
magnetoelectric switching and spin–orbit detection of state, and show that in comparison with CMOS technology our
device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced
logic density (by a factor of 5). In addition, its non-volatility enables ultralow standby power, which is critical to modern
computing. The properties of our device indicate that the proposed technology could enable the development of multi-
generational computing.
Transistor technology scaling
1–3
has been enabled by controlling the
conductivity of a semiconductor using an electric field applied across
a high-quality insulating gate dielectric. This fundamental principle
has remained largely unchanged since the seminal observations of
Moore and Dennard et al.
4,5
. Yet in the past decade, transistor scaling
has been enabled by direct improvements to the carrier transport1,6,7,
combined with superior electrostatic control
1–3,8
. In contrast to pure
dimensional scaling
5
, new transistor technologies have necessitated the
use of strain6, three-dimensional electrostatic gate control2,8, manipu-
lation of the effective carrier mass and band structure, and the gradual
introduction of new materials for interface and work function con-
trol
9
. Despite the successful scaling in the size of transistors, voltage
and frequency scaling have slowed
10
. Further decrease of voltage has
been hampered by the Boltzmann limit of current control (60mV for
every change in current by a factor of 10 at room temperature). In
response, a considerable effort to invent, demonstrate and benchmark
beyond-CMOS devices got underway
1113
. This effort includes alter-
native computing devices based on electron spin, electron tunnelling,
ferroelectrics, strain and phase change12,13 (seeMethods for beyond-
CMOS logicdevice options). However, a technologically suitable com-
putational logic device that has superior energy efficiency, high logic
density (that is, computed functions per unit area), non-volatility (to
counteract leakage power) and efficient interconnects has remained
elusive. The importance of these considerations has become evident
during extensive modelling, benchmarking and evaluation of more
than 25 beyond-CMOS deviceproposals12,13. With these considera-
tions in view, we propose and demonstrate the building blocks for a
new logic device that enables (1) voltage scaling, (2) scalable intercon-
nects, (3) energy scaling and (4) the potential for multi-generational
dimensional scaling.
Beyond-CMOS devices for replacing or enhancing the
electronic transistor
Collective state switching devices are potential candidates for replac-
ing or enhancing transistors. A collective state switch operates by the
reversal of the material’s order parameter (such as ferromagnetism,
ferroelectricity and ferrotorodicity)13 from ϴ to ϴ. It addresses sub-
10-nm miniaturization by using collective order parameter dynamics,
overcoming the ‘Boltzmann tyranny’, which is inherent to conductiv-
ity modulation, and providing a non-volatile nature to the computer.
It is well documented that the ‘Boltzmann tyranny’ and leakage are
the central challenges in traditional CMOS devices
1,2
. Logic based on
collective state switching devices is a leading option for computational
advances beyond the modern CMOS era owing to its (1) potential for
superior energy per operation, (2) higher computational logical density
and efficiency (that is, fewer devices required per combinatorial logic
function) owing to the use of majority gates14, (3) non-volatile memory-
in-logic and logic-in-memory capability15 and (4) amenability to
traditional and emerging architectures (for example, neuromorphic
16
and stochastic computing17).
Among these possible collective state order parameters, ferroelectric-
ity and multiferroicityare the preferred collective states for computing
13
owing to (1) the presence of a controllable, localized and phenome-
nologically strong carrier, the spontaneous dipole; (2) the switching
efficiency of a ferroelectric with respect to the stability of the switch is
given by the energy barrier per unit volume, λ=E
sw
/ΔE(Θ), where
ΔE(Θ) is the energy barrier relative to the stable state and Esw is the
total energy dissipated in switching; lower values of λ enable computing
switches to operate at lower energies for a given energy barrier.
A vital consideration for a new technology is the need for highly
compact nanoscale interconnects. While ferroelectric switching and the
1Components Research, Intel Corporation, Hillsboro, OR, USA. 2Intel Labs, Intel Corp., Santa Clara, CA, USA. 3Department of Materials Science and Engineering, University of California, Berkeley,
Berkeley, CA, USA. 4Lawrence Berkeley National Laboratory, Berkeley, CA, USA. 5Department of Physics, University of California, Berkeley, Berkeley, CA, USA. *e-mail: sasikanth.manipatruni@intel.com
3 JANUARY 2019 | VOL 565 | NATURE | 35
... Although room temperature magnetism and proximity effects have been reported using vdW magnets [20][21][22] , the lack of active spintronic device operation at room temperature significantly limits its practical application potential 21,23,24 . Furthermore, a lateral room temperature spin-valve device with vdW metallic magnets, an essential building block for proposed spin-based memory, logic, and neuromorphic computing architectures [25][26][27][28] has not been realized yet. ...
... This will bring a strong synergy between 2D materials and spintronics with the possibility of further controlling the figures of merit by twist angle between the vdW layers, magnetic proximity effects, and gate tunability for energy-efficient and ultra-fast spintronic devices 15,52 . These room-temperature developments in vdW magnet-based heterostructures will open future opportunities for fundamental studies and spintronic devices for magnetic sensor, memory, logic, communication, and novel computing architecture applications 25,26 . ...
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