Ultralow Phase Noise 10-MHz Crystal Oscillators

Abstract

This paper describes the design and implementation of low phase noise 10MHz Crystal Oscillators (using SC cut crystal resonators) which are being used as part of the chain of a local oscillator for use in compact atomic clocks. The design considerations and phase noise measurements are presented. The design includes a low noise transformer coupled differential amplifier, spurious resonance rejection filter and electronically tuned phase shifter. Phase noise measurements demonstrate a performance of -122dBc to -123dBc/Hz at 1Hz and -148dBc/Hz at 10Hz offsets. The phase noise at 1Hz offset is very similar to the phase noise produced by the low noise version of a doubled 5MHz BVA resonator based oscillators (Model number 8607) previously produced by Oscilloquartz. The noise floor of the oscillators presented in this paper is around - 161dBc/Hz. These designs can be used as the reference oscillator to control the timing of many modern electronics systems.

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Ultra Low Phase Noise 10MHz Crystal Oscillators
1Jeremy Everard, 2Tsvetan Burtichelov and 3Keng Ng
1Department of Electronic Engineering, University of York (UoY), Heslington, York, YO10 5DD
2Formerly UoY, now at CGC Technology Ltd, 3Formerly UoY, now at Mars
Abstract— This paper describes the design and implementation
of low phase noise 10MHz Crystal Oscillators (using SC cut
crystal resonators) which are being used as part of the chain of
a local oscillator for use in compact atomic clocks.
The design considerations and phase noise measurements are
presented. The design includes a low noise transformer coupled
differential amplifier, spurious resonance rejection filter and
electronically tuned phase shifter. Phase noise measurements
demonstrate a performance of -122dBc to -123dBc/Hz at 1Hz
and -148dBc/Hz at 10Hz offsets. The phase noise at 1Hz offset is
very similar to the phase noise produced by the low noise version
of a doubled 5MHz BVA resonator based oscillators (Model
number 8607) previously produced by Oscilloquartz. The noise
floor of the oscillators presented in this paper is around -
161dBc/Hz.
These designs can be used as the reference oscillator to control
the timing of many modern electronics systems.
I. INTRODUCTION
The phase noise and jitter in oscillators sets the ultimate
performance limits in communications, navigation, radar and
precision measurement and control systems. It is, therefore,
important to develop simple, accurate linear theories which
highlight the underlying operating principles and to present
circuit implementations based on these theories.
Crystal oscillators offer a solution for precision oscillators
due to the precise resonant frequency, very high Q and
controllable temperature coefficients.
Many papers have been written on High Frequency (HF),
Very High Frequency (VHF) and Ultra-high Frequency
(UHF) bulk crystal and surface acoustic wave (SAW)
oscillators [1-10] including a significant tutorial review of
crystal oscillators [11].
Key aspects to be considered to achieve low phase noise
in crystal oscillators are the 1/f flicker noise of the amplifier,
the flicker-of-frequency noise in the resonator [1] and the
AM-to-PM conversion at higher crystal drive power levels
due to non-linear effects in the crystal [2,3,5]. There is
transposition of this flicker noise onto the carrier which
typically produces a ~1/f3 phase noise contribution in the
oscillator.
Methods to reduce the drive level dependence include, for
example, cancellation of two opposing effects by operating a
quartz crystal oscillator at a point slightly above the crystal
series resonance where a change in oscillator phase would
result in a change in crystal drive level, producing a shift in
crystal frequency exactly equal to but opposite the frequency
shift resulting from the resonator phase versus frequency
characteristic [2], and the use of multiple resonators to share
the power [4].
The far from carrier noise floor is reduced by increasing
the crystal power so this should be considered at the same time
as the drive level dependence of the crystal [3].
The effect of resonator out-of-band impedance on the
sustaining stage white noise should be considered [6].
Multiple amplifiers with inter-amplifier attenuation can also
be used to improve performance [7].
A variety of self-limiting amplifier/oscillator types are
discussed in detail in [3], which highlight the requirement for
high Q and adequate suppression of l/f flicker-of-phase type
noise, and improvement in oscillator noise floor signal-to-
noise. A number of oscillator topologies are also discussed
including, the Pierce, Miller, Butler, Bridged-T
configurations. Measurements of the AM to PM conversion
are also important [9].
However there are very few papers (if any) showing
complete designs with phase noise near or below -120dBc at
1Hz offset in 10MHz Crystal Oscillators. Ultra-low phase
noise oscillators using BVA [12] SC cut resonators have been
described [13-14] but the detailed oscillator circuit
descriptions were not included.
The quoted phase noise for the low noise version of the
BVA OCXO 8607 oscillators in previous data sheets at 1Hz
offset is -130dBc at 5MHz and -122dBc/Hz at 10MHz. The
phase noise of the oscillators described in this paper, which
use standard SC cut resonators, are very similar to the doubled
5MHz output (+6dB) and directly to the 10MHz output.
A number of low phase noise commercial designs are
available, along with their phase noise specifications,
however circuit diagrams are not provided. For example, the
preliminary data sheet for the Morion MV3336M specifies -
119 to -120dBc at 1Hz offset so the oscillator presented in
this paper is 2.5 to 3.5dB better than the specification. The
“extraordinary range” of low phase noise 10 MHz oven

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controlled crystal oscillators manufactured by NEL states -
120dBc at 1Hz offset.
The short and medium-term phase noise and Allan
deviation of the local oscillator is one of the limiting factors
of the performance of most systems including for example
vapour cell atomic clocks. Extremely low phase noise can be
achieved by combining the close to carrier performance of
crystal oscillators with the medium offset and the low noise
floor of a Dielectric Resonator Oscillator (DRO) [15] and also
including narrow band digitally controlled Direct Digital
Synthesisers [16-18].
It is interesting to note that the DRO described in [15-16]
had similar or better phase noise performance than multiplied
100MHz crystal oscillators, but the 10 MHz oscillator was
able to improve the performance and stability below 10Hz
offsets. The resulting system [16] is highly versatile in terms
of tuning and locking the flywheel frequency to the atomic
resonance and is capable of providing multiple highly stable
output signals at both RF and Microwave frequencies.
In this paper, which is a significant extension of a paper
submitted to the joint EFTF-IFCS 2007 conference [19], and
the 2017 IFCS conference [16], we present the detailed design
information for all the elements required for an ultra-low
phase noise 10MHz crystal oscillator.
This paper is ordered as follows: section II describes the
underlying phase noise theories and resultant optimum
conditions; section 3 describes the oscillator design with 3A
covering the amplifier design, 3B resonator modelling, 3C the
spurious rejection filter and 3D the electronic phase shifter
tuning and section 3E describes the complete oscillator circuit.
Section IV covers phase noise measurements and section V
describes the implementation of a double oven OCXO
version. Section VI describes further work and potential
improvements and section VII includes conclusions.
II. PHASE NOISE THEORY
It is important to develop a simple model to calculate and
predict the noise performance of an oscillator. Leeson [10]
demonstrated an equation which gives useful information
about the phase noise but the optimum conditions for
minimum noise are not clear. Parker [21] demonstrated an
optimum condition for a modified version of Leeson’s
equation. It is useful, however, to develop a simple model,
from first principles, which enables an accurate and clearly
understood equation to be derived from first principles.
A suitable model is shown in figure 1 [22-25]. This
consists of an amplifier with two inputs which are added
together. These represent the same input but are separated to
enable one to be used to model the noise input and the other
for feedback. The resonator is represented as an LCR circuit
where any impedance transformation is achieved by varying
the component values. This circuit, through positive feedback,
operates as a Q multiplication filter but also contains the
additional constraint that the AM noise is suppressed in the
limiting process. This means that the phase noise component
of the input noise drops to kT/2 which has been confirmed by
NIST [26] and this research group. This limiting also causes
the upper and lower sidebands to become coherent and has
been defined as conformability by Robins [27]. The model is
put in this form to highlight all the effects, which are often not
clear in a block diagram model.
Figure 1 Oscillator Model
A general equation for the phase noise can be derived as
shown in [24][25] which incorporates a number of operating
conditions including multiple definitions of output power
from the amplifier, the input and output impedances, the ratio
of loaded to unloaded Q factor (QL/Q0) and operating noise
figure F.
The phase noise equation applicable to the crystal oscillator
in this paper, where ROUT = RIN and the Power is defined as
the power available at the output of the amplifier (PAVO)
simplifies to equation 1:
()
2
0
2
0
2
0
2
018








Δ







−








=f
f
P
Q
Q
Q
Q
Q
FkT
fL
avo
LL
(1)
This equation will be used in the analysis for the noise
performance and gain requirements in the thermal noise
regime and is minimum when QL/Q0 = ½ and hence when the
insertion loss of the resonator is 0.25 (–6dB) [24].
This minimum occurs when maximum power is dissipated
in the resonator. This is described in detail in [25] where it is
shown that the equation for power available to the resonator is
very similar to the denominator of the phase noise equation.
Paper [25] also shows how a similar phase noise derivation
can be applied to negative resistance oscillators and compares
the noise performance of the two types.
As S21 = (1-QL/Q0), a plot of phase noise vs insertion loss
for the resonator (which is the same as the closed loop gain of
the amplifier) is shown in Figure 2. It can be seen that less
than one dB of phase noise degradation occurs when the
insertion loss is within the bounds of 3.5 to 9.5dB.
L
C
(noise)
V
IN1
V
IN2
1
2
R
LOSS
R
IN
R
IN
(Feedback)
R
OUT

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Figure 2, Phase noise degradation with resonator insertion loss/open loop
gain
It should be noted that the optima, just discussed, apply if
the noise is thermal (additive) noise and also only apply to the
skirts of the phase noise. For far out noise to be minimum the
gain should be kept low (Q
L
/Q
0
low) and for reduced
transposed flicker noise the loaded Q should be higher.
However, it is a good starting point.
The more complete equation used to calculate the phase
noise, used in the simulations and measurements shown in
section IV, is shown below in equation 2 [19]. The right-hand
term (D) is based on equation 1 where F
1
is the noise figure of
the oscillation sustaining amplifier. The middle term (C)
shows the noise floor outside the resonator bandwidth (far
from carrier noise) caused by the closed loop amplifier gain.
Both these terms are multiplied by a flicker noise component
(B) (1 + F
C
/f) where F
C
is the flicker noise corner. The left-
hand term (A) includes the buffer amplifier after the output
coupler and is still assumed to be limited to the phase noise
component (therefore 2P). F
2
is the noise figure of the buffer
amplifier. C
0
is the coupling coefficient which relates the
power available to the resonator to the power available to the
buffer amplifier which is 1 in this case. The ‘1’ just after the
‘log’ refers to the phase noise of a single oscillator. This is
changed to 2 when the combined noise of two identical
oscillators is being displayed.
A B C D
()
()





























































−








+





















−







++=
2
0
2
0
2
0
2
0
1
0
1
0
2
18
1
1
2
1
2
1Log10 f
f
P
Q
Q
Q
Q
Q
kTF
Q
Q
P
kTF
f
Fc
PC
kTF
fL
LL
L
(2)
III. O
SCILLATOR
D
ESIGN
The block diagram of the feedback low phase noise 10
MHz crystal oscillator is shown in Figure 3. It comprises of a
differential amplifier, spurious resonance rejection filter, a
voltage tuned phase shifter and the crystal resonator. Details
on the design of each of these elements and their circuit
diagrams are described in this section.
Figure 3, 10 MHz crystal oscillator block diagram.
A. Differential Amplifier
The circuit diagram of the differential amplifier is shown in
Figure 4. The amplifier uses a low noise super matched NPN
transistor pair (SSM2210 or SSM2212) to ensure good
symmetry and low noise performance. This particular device
also has a very low flicker noise corner (<10 Hz), which is
important for achieving low close to carrier phase noise. The
flicker noise of both npn and pnp supermatch pairs are
discussed by Rubiola and Lardet Vieudrin for DC/LF
amplifier design [28].
Figure 4, Differential amplifier circuit diagram.
An advantage of using a differential amplifier is that two
outputs can be obtained simultaneously with a phase
difference of 180°. One of these outputs can be used to close
the loop (preferably the one with phase shift closer to
N*360°), while the other can be used directly as the output of
the oscillator. This eliminates the need for an output coupler.
The differential design also offers non-saturated limiting
and accurate control of the limiting output power and near
zero second order (and even order) non linearities.
The amplifier is differentially driven using a 1:16
impedance transformer. This provides biasing for the bases
0
1
2
3
4
5
6
7
8
9
10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Phase Noise Degration, dB
Resonator Insertion Loss, dB
Phase Noise Degradation with Resonator Insertion
Loss/Closed Loop Gain

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of both transistors (connecting them directly together at DC
and LF), while the impedance ratio ensures optimal noise
matching. For collector currents around 6.5 to 7.5mA, used
in these oscillators, the equivalent noise voltage is around
0.8nV/√Hz and the equivalent noise current is about
2pA/√Hz, therefore the optimum source impedance is about
400Ω for a single device and thereby 800 Ω in the differential
mode. This is 16 times the source resistance of 50Ω.
The minimum noise figure available for these noise sources
is given in equation (3) [24]:
𝑁𝐹

10log1𝑒

𝑖

2𝑘𝑇𝐵 0.8dB 󰇛3󰇜
The noise figure was measured to be 1.8dB and the
difference is most likely due to the losses in the transformer.
Resistors R1 and R2 ensure that the output impedance is
about 50 Ohm for both outputs. Resistor R3 and R4 sets the
current through the transistors at about 6.5 to 7.5 mA.
Capacitors C1 and C2 are used for coupling the RF signal to
the outputs.
The bias current is set by resistor R3 and potentiometer R4
which also sets the gain and the P
AVO
at the output of the
amplifier. The gain should be larger than the losses around
the loop to ensure oscillation under all conditions including
the high turnover temperature and the power should be
correct for best operation of the crystal. The power should be
low enough not to cause damage, AM-PM conversion, or
excessive aging but large enough to maintain low phase noise
and low phase noise floor.
A simple calculation for the limiting output power can be
obtained by assuming that the DC voltage across the output
resistors (R1 and R2) under quiescent collector current
conditions for a single transistor (I
CQ
) is:
𝑉

𝐼

𝑅

󰇛4󰇜
The peak to peak voltage swing in R1 and R2 in terms of
the collector currents is twice this:
𝑉

2𝐼

𝑅

󰇛5󰇜
The peak voltage is half this value. As these limiters only
saturate very lightly they produce an output which is very
nearly sinusoidal (not a square wave) so the rms value is
therefore: 𝑉

𝐼

𝑅

√2 󰇛6󰇜
This is the equivalent open circuit voltage so the power
available into a 50Ω load is:
𝑃

𝑉


4𝑅

𝐼

𝑅

8 󰇛7󰇜
The quiescent current in terms of the power available at the
output is therefore:
𝐼

8𝑃

𝑅

󰇛8󰇜
For an available output power of 250μW (-6dBm), which
appeared to be optimum, this predicts a collector current of
6.32mA. The quiescent collector current measured in the
original prototype (which used high Q components) was
6.6mA. Phase noise measurements vs power for the original
prototypes are discussed in [19].
The typical gain and phase shift were measured using a
network analyzer. Figure 5 shows the frequency response of
a later amplifier operating at 7.5mA. The measured gain at
10MHz was 8.3dB, while the phase shift at one of the outputs
was 84.7°.
Figure 5, Differential amplifier frequency response.
B. The Crystal Resonator
SC cut 10MHz crystal resonators manufactured by Nofech
Ltd were used. The characteristics specified by the
manufacturers were approximately: RR ~ 53Ω, Q
0
~ 1.3M
and turnover temperature, TO, ~ 82ºC.
A simple model of the crystal resonator is shown in Figure
6 and includes series and parallel resonant components. The
crystal was placed on a test board with 50Ω microstrip
transmission lines and its frequency response was measured
using a vector network analyzer. Figure 7 shows the

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measurement of the series resonance. The measured loaded
Q was 491,580 (which corresponds to a bandwidth of about
20Hz) and the insertion loss was 3.79dB. Note care should be
taken to ensure that the sweep rate is sufficiently low to
obtain accurate results. It is also quite easy to see ringing on
the network analyzer if the sweep is too fast.
It is also worth noting that a low cost compact USB
controlled VNA (VNWA v2) made by SDR kits was used as
this offers sub Hz resolution, easy measurement, calibration,
internal crystal modelling and the use of 50,000 points in a
single sweep allowing full simultaneous measurements of all
the wanted and spurious modes over 100MHz. The stability
of this network analyser was also found to be sufficient to
obtain highly accurate readings.
Figure 6, Model for crystal resonator
Figure 7, Crystal Resonator series resonance (Span = 100Hz).
Simplifying the model to just the series resonant elements,
it is possible to use the equation S
21
= (1 – Q
L
/Q
0
) to estimate
the unloaded Q. From this equation Q
0
= 1.39M (which is a
about 7% higher than the manufacturers parameters). Note
that more accurate modelling can be achieved by including
further components in this model. By using the ratio of the
series and parallel resonances, the other components can be
calculated using:
PS
S
S
P
CC
C
f
f
+
+= 1
(9)
C. Spurious rejection filter
Aside from the useful 10MHz resonance, the crystals
exhibit an unwanted spurious resonance at about 10.9MHz.
This can cause the oscillator to begin oscillating at the wrong
frequency. In order to suppress this resonance, a filter was
designed and incorporated into the loop. It is essential that
this filter does not interfere with the main resonance, while
filtering out the unwanted one. The design that was used in
this case is inspired by the model of the crystal resonator.
Figure 8 shows the circuit diagram of the filter. The series LC
resonance is tuned to 10MHz, while the parallel resonance to
10.9MHz. This enables an increased insertion loss in the
unwanted resonance, while the loss in the useful resonance is
kept to a minimum while using only three components. It also
provides the correct open loop phase shift for the oscillator.
The frequency response of the filter is shown in Figure 9.
Figure 8, Spurious resonance filter circuit diagram.
Figure 9, Spurious resonance filter frequency response.
D. Tuning Elements

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Frequency tuning is typically achieved by incorporating the
varactor diodes either into the resonator or by using phase
shift tuning separate from the resonator as illustrated in
Figure 3. Phase shift tuning has the advantage that it does not
degrade the resonator unloaded Q and the phase noise
degradation can be accurately calculated. This group has
shown (theoretically and experimentally) that the noise
performance degrades with a cos
4
θ relationship [24] [29].
Therefore an open loop phase error of 45º causes 6dB
degradation + the insertion loss of the phase shifter. The
phase noise degradation for + 20° of phase shift is < 1dB.
The phase shifter should have low insertion loss and a near
linear phase vs frequency response. A voltage controlled
phase shifter was therefore designed.
1) Electronic Phase Shifter
The electronic phase shifter consists of a tunable high pass
filter as shown in Figure 10.
Figure 10 Tunable phase shifter based on 5
th
order
Butterworth Filter
The design process uses a tuneable high pass filter based on
a 5
th
order Butterworth filter prototype used by the author for
a commercial CRO design [30] and ultra low phase noise
dielectric resonator oscillators [15]. Low insertion loss is
ensured by always operating in the pass band. As the cut-off
frequency is changed the passband phase shift (near cut-off)
varies. A high pass design was used as low pass designs often
suffer from parasitic series resonances causing increased loss
[31]. The design also incorporated back to back diodes to
enhance the power handling capability. The network can be
tuned directly from a voltage (low impedance) source
ensuring no resistor thermal noise.
The initial 5
th
order normalised high pass Butterworth
prototype circuit is shown in Figure 11.
Figure 11 Normalised high pass Butterworth filter
prototype
The high pass parameters were then calculated for a cut-off
frequency of 0.6 x fc as this was found to give good phase
shift tuning with negligible change in insertion loss. The final
6MHz circuit is shown in Figure 12. The terminating
impedances were chosen to be 50Ω.
Figure 12, 6MHz High Pass Butterworth filter
C1 and C2 are now replaced by a combination of varactors
and fixed capacitors where 0.6fc occurs when:
C1= C2 = 328 pF.
The varactors were chosen by considering the total
capacitance and capacitance variation required in the phase
shifter. The BB201 was chosen from the CV characteristic
shown in Figure 13 (taken from the data sheet). The early
prototype oscillator used BB147 varactors but these were
replaced here as they are no longer available.
2) Final Circuit and measurements
The final circuit is shown in Figure 14 where the centre
inductor is now used to bias the varactors. This point should
be decoupled correctly. Note that the modulation sidebands
roll-off at 6dB per octave only inside the 3dB bandwidth of
the resonator.
Figure 13, CV characteristics for BB201

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Two varactor diode pairs (BB201) were used in series-
parallel in order to have increased tuning capability. Fixed
value capacitors C5 and C6 were also added to bring the
capacitance up to the filter design specifications. Capacitor
C7 is for decoupling the inductor L3. This point should be
driven by a low impedance source. The inductors chosen
were the closest standard values to the calculated ones.
Figure 14, Voltage tuned phase shifter circuit diagram.
Figure 15, Insertion loss and phase shift vs voltage
The insertion loss vs phase shift, of the phase shifter shown
in figure 14, is shown in Figure 15. It should be noted that the
cutoff frequency of this filter starts to become close to
10MHz (causing increased insertion loss) when the bias
voltage is above 6 volts, so this circuit should not be used
above this point. If higher/different voltage operation is
required the ratio of fixed to variable capacitance can be
varied and the varactors can be changed.
Using this phase shifter, the oscillation frequency can be
electronically tuned within a range of a few Hz. A theoretical
curve showing phase noise degradation (dB), resonator
insertion loss (dB) and tuning range (linear) plotted against
phase shift (degrees) is shown in Figure 16. The normalized
factor for the absolute tuning range is shown in the lowest
curve in figure 16. For a Q
L
of 491,580 and + 20° of tuning,
this predicts a tuning range of 0.36𝐹0/󰇛2𝑄𝐿󰇜 = + 3.7Hz with
<1dB of phase noise degradation.
Figure 16, Phase noise degradation, resonator insertion loss and tuning range
plotted against phase shift (degrees)
E. Complete Oscillator Circuit Diagram
The complete diagram of the 10MHz crystal oscillator is
shown in Figure 17. The circuit was tested in open loop
configuration and the transmission between the input of the
transformer and the output of the resonator was measured to
ensure that the correct conditions for oscillation were met.
Note that the circuit was broken at the junction between R2
and C2 as this has a 50Ω source impedance enabling correct
use of the total S parameters. With a varactor diode bias of
1.5V the phase shift through the complete circuit was about
3° and there was an excess gain of at least 1.4dB at 10MHz.
These conditions were enough to sustain oscillation at the
desired frequency. Oscillator switch-on time is of course very
slow.
Figure 17, 10MHz crystal oscillator complete circuit diagram.
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
100
110
120
130
140
150
160
170
012345678910
Insertion loss dB
Bias Voltage
Phase Shift
Phase
Ins Loss

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Page 8 of 11
IV. P
HASE
N
OISE
M
EASUREMENTS
A prototype crystal oscillator was built and powered by 4 x
1.5V AA batteries, for both the positive and negative supply.
A 1.5V AA battery was used for biasing the phase shifter.
The oscillator was then placed inside a metal screened box.
A second, smaller oscillator was also built and placed in a
specially machined aluminum jig, which provides screening
and heating capabilities for both the circuit board and the
crystal resonator. The jig was then covered with a brass lid
and feed-through pins were used to interface for the bias
input, output and power supply to the oscillator (Figure 18).
This oscillator was also powered by batteries.
Figure 18, Crystal oscillator in aluminum jig (Oscillator 2).
The phase noise was measured using the Symmetricom
5120A (opt 01) phase noise measurement system. A total of
3 sets of measurements were taken: one for each individual
oscillator using the internal reference of the Symmetricom
instrument and one in which the two oscillators were
measured against each other.
It is important to use high quality passive components
(inductors, capacitors and resistors) for construction. Poor
choice of components could degrade the phase noise by as
much as 10dB. The best phase noise results were achieved
with high-Q Coilcraft surface mount inductors and high
quality polystyrene capacitors. This is possibly due to the
piezoelectric properties of the dielectrics, non-linearity
and/or added flicker noise.
A. Oscillator 1
The phase noise of the first oscillator was measured using
the internal reference of the measurement system. In order to
bring the signal level to the value required by the instrument,
a ZFL-1000VH Mini Circuits 20dB low residual phase noise
amplifier was used. A 10dB attenuator was added to make
sure the instrument’s input was not overloaded. A block
diagram of the measurement configuration is shown in Figure
19.
Figure 19, Block diagram of the measurement configuration with internal
reference.
The measured phase noise performance is shown in Figure
20. The measured values are shown in Table 1.
Figure 20, Oscillator 1 phase noise performance.
Table 1: Oscillator 1 phase noise results.
Offset frequency (Hz) Phase noise (dBc/Hz)
1 -123.0
10 -148.6
100 -157.8
1,000 -161.0
10,000 -161.1
It can be seen that the oscillator shows excellent phase noise
performance down to 1Hz offset frequency. There are
multiple spurs visible between 1Hz and 10Hz offsets. These
could be attributed to insufficient screening, pickup from the
interconnecting cables or spurs generated by the instrument.
A theoretical phase noise plot is shown in Figure 21 based on
equation (2). The parameters used in this equation are shown
in Table 2:
Table 2: Parameters used in phase noise simulation
Q
0
1.39M
Q
L
491,580
P
AVO
-6dB
m
F
1
, Noise fi
g
ure of oscillatin
g
amplifie
r
1.8dB
F
2
, Noise fi
g
ure of Buffer Amplifie
r
4.7dB
F
c
, Flicker noise corner of circuit 150Hz

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Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
Page 9 of 11
The 150Hz transposed flicker noise corner takes into account
the flicker noise in the amplifier, the flicker-of-frequency
noise in the resonator and the drive level dependent AM to
PM conversion in the resonator.
Figure 21, Phase noise simulation using equation (8) and parameters from
table 2
B. Oscillator 2
The second oscillator was measured using the same
measurement configuration as Oscillator 1 (Figure 19). The
measured phase noise performance is shown in Figure 22.
The values are shown in Table 3.
Figure 22, Oscillator 2 phase noise performance.
Table 3: Oscillator 2 phase noise results.
Offset frequency (Hz) Phase noise (dBc/Hz)
1 -122.4
10 -146.8
100 -155.3
1,000 -158.2
10,000 -159.0
It can be seen that there is a small increase in the phase noise
at all offsets. This may be attributed to the differences in the
resonators, the tolerance of the components or the smaller
volume of Oscillator 2. When the inductors are placed too
close to each other there may be magnetic coupling between
them, which could alter the response of the filter and phase
shifter. The spurs below 10Hz offset are reduced in this case.
C. Oscillator 1 vs. Oscillator 2
Both oscillators exhibit good phase noise performance when
measured using the internal reference of the Symmetricom
system. However, when using the internal reference, the
system’s noise floor is specified as “-120dBc/Hz at 1Hz” by
the manufacturer. Therefore, it is unclear whether these
results are accurate. Also the 5120A uses cross correlation
which can be prone to cross spectrum collapse [32][33].
In order to confirm the performance, the two oscillators were
measured against each other, one used as reference and the
other as the input signal, as shown in Figure 23. This brings
the noise floor of the measurement down significantly (down
to -145dBc/Hz according to the datasheet).
Figure 23, Block diagram of the measurement configuration with external
reference.
The results of the phase noise measurements are shown in
Figure 24 and the values are tabulated in Table 4.
The resulting graph shows the added noise of the two
oscillators. Therefore it is safe to estimate that the phase noise
of any of the two oscillators is at least 3dB lower than the
displayed graph. This ties in with the measurements taken on
each individual oscillator.
Figure 24, Phase noise performance with Oscillator 1 as reference and
Oscillator 2 as input.

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Table 4: Oscillator 1 vs. Oscillator 2 phase noise results.
Offset
frequency (Hz)
Phase noise
(dBc/Hz)
Phase noise
(dBc/Hz), -3dB
1 -118.9 -121.9
10 -144.7 -147.7
100 -153.2 -156.2
1,000 -156.2 -159.2
10,000 -156.5 -159.5
V. D
OUBLE
O
VEN
10MH
Z
C
RYSTAL
O
SCILLATOR
The latest version of the crystal oscillator was built in a more
compact package and was temperature stabilized around the
inversion temperature of the resonator (82°C) in a double
oven configuration. In this version the polystyrene capacitors
were replaced with high-quality ceramic surface mount
capacitors from ATC. This was done for two main reasons:
the polystyrene capacitors are larger, which increases the
volume of the construction and their maximum operating
temperature (85°C) is too close to the desired oven
temperature. A photograph of the construction of the
oscillator is shown in Figure 25.
Figure 25, The three stages of the construction of the double oven
controlled crystal oscillator.
The oscillator circuit and resonator are contained in the
aluminium jig, which is a smaller version of Figure 18 and
serves as the first oven. Power transistors and resistors were
used as heating elements. They are placed around the
resonator enclosure in such a way as to enable a more
symmetrical and uniform distribution of heat. A layer of
insulation is placed over them, followed by a brass box,
which serves as the second oven. A second layer of insulation
and an outer brass box complete the construction. The
temperature controllers were built on FR4 boards and
attached under the box using offset screws. The complete
oscillator is shown in Figure 26.
The inner oven of the oscillator was stabilized at 82°C and
the outer oven around 20° lower. The phase noise was
measured in this configuration and was found to be close to
the previously measured results at room temperature, with
only a small degradation of about 0.6dB.
VI. F
URTHER WORK AND POTENTIAL IMPROVEMENTS
The emitter resistor, shown in Figure 4, could be replaced
with a current source. This could offer reduced sensitivity to
supply ripple but could affect the flicker noise performance.
It is interesting to note that the collector voltage can be
reduced and the oscillator will even run with the collector
shorted to ground (0V) but the phase noise has not been
checked under these conditions.
Parallel configurations of transistors could be used to reduce
the noise figure, flicker noise and the impedance
transformation ratio.
Figure 26, The complete double oven crystal oscillator.
VII. C
ONCLUSIONS AND
F
UTURE
W
ORK
It is shown that oscillators with excellent phase noise
performance can be built using relatively simple, but highly
accurate linear theories and these can be implemented using
a modular approach to oscillator designs, utilising
transformer coupled differential amplifiers, a 3 element filter
and high pass phase shifter designs.
Further improvements in the longer-term phase noise
performance are expected through improved and optimized
temperature stabilization of the resonator at the turnover
temperature (82°C). Certain types of components have been
found to be more effective in keeping the phase noise low.
VIII. R
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TUFFC.2018.2881456, IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
Page 11 of 11
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