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An Ultra-Low Power Temperature Sensor Based on Relaxation Oscillator in Standard CMOS
... Several STS devices using an FDC topology have been proposed [1][2][3][4][5]. Although [1][2][3][4] present great performance, their minimum supply voltages, of around 1.1 V, make them impossible to be used in applications that require very low VDD. ...
... Several STS devices using an FDC topology have been proposed [1][2][3][4][5]. Although [1][2][3][4] present great performance, their minimum supply voltages, of around 1.1 V, make them impossible to be used in applications that require very low VDD. Work [5] operates with a minimum supply voltage of 0.5 V with a very low silicon area, but consumes 8.8 µW, which is too much for systems that need to operate with energy harvesting [6]. ...
... This modification in the external clock duty cycle can be understood as a possible calibration parameter. Note that it is not an issue, because two-point calibration is normally required to guarantee proper and optimum operation in temperature sensors [1][2][3][4]8]. Figure 17 shows the digital output code generated by the digital counter and the simulated nonlinearity is given in Table 2. As can be seen, the worst non-linearity occurs in the FF corner case. ...
The smart temperature sensor measures the room temperature and converts it to the digital domain, thus making it easier to process and store data. This work presents a fully integrated smart temperature sensor implemented in a 180 nm CMOS technology suitable for low voltage and ultra-low power electronic applications. The designed circuit uses a frequency to digital conversion topology, in which the frequency of an internal signal is linearly dependent on the room temperature. The minimum supply voltage for the designed circuit is only 0.5 V, while the occupied silicon area is 0.04 mm². By employing a simple frequency doubler circuit and proper circuit topologies, a very low power consumption of 19 nW for a sampling frequency of 100 Hz at 27 °C is achieved. Moreover, the sensor consumes nominally 190 pJ per conversion. The simulated inaccuracy using nominal (TT) transistor models is lower than 0.5 °C over a wide temperature range of − 30 °C to 100 °C. Preliminary silicon data shows the functionality of the design circuit. Additionally, the effects of the external clock signal temperature coefficient on the performance of the designed circuit were discussed, and a correction method was proposed.
... Several STS devices using an FDC topology have been proposed [1][2][3][4][5]. Although [1][2][3][4] present great performance, their minimum supply voltages, of around 1.1 V, make them impossible to be used in applications that require very low VDD. ...
... Several STS devices using an FDC topology have been proposed [1][2][3][4][5]. Although [1][2][3][4] present great performance, their minimum supply voltages, of around 1.1 V, make them impossible to be used in applications that require very low VDD. Work [5] operates with a minimum supply voltage of 0.5 V with a very low silicon area, but consumes 8.8 µW, which is too much for systems that need to operate with energy harvesting [6]. ...
... This modification in the external clock duty cycle can be understood as a possible calibration parameter. Note that it is not an issue, because two-point calibration is normally required to guarantee proper and optimum operation in temperature sensors [1][2][3][4]7]. Fig. 9. Simulated PTAT clock frequency as a function of temperature using process corner Fig. 10. Simulated output counted value as a function of temperature for corner cases TT, SS, and FF. Figure 10 shows the digital output code generated by the digital counter and the simulated nonlinearity is given in Table I. ...
... The evolution of low-power consumption sensor technology has led to the creation of CMOS sensors that function effectively on mere nano-watts of power, as shown through representative works in TableⅠ [6][7][8][9][10]. Solar light, a pervasive and high-density energy source, with an energy density reaching up to 0.16μW/lux·cm2, could provide sufficient energy for microsensors through small size on-chip solar cells. ...
... As dl approaches 0, n approaches infinity. After simplification, the N+ region's equivalent resistance rRE approximates to be (9). When accounting for near-electrode square equipotential surfaces, rRE is rewritten as (10), where k represents the percentage of the circular equipotential surface. ...
Enhancing the photoelectric conversion efficiency of on-chip solar cells is important for the realization of self-powered smart microsensors. The surface electrode models for the on-chip solar cell based on CMOS process is constructed. It is verified by simulations and measurements that square ring electrode (RE) and center electrode (CE) don’t cause significant differences in the internal resistance of solar cells. Adopting the CEs instead of the REs can significantly reduce the shadowing effect of surface electrodes. To solve the problem of light blockage caused by the metal interconnections in the segmented solar cells, highly doped regions are used to replace some of the metal interconnections. A 0.01mm2 segmented triple-well on-chip solar cells with the CEs and highly doped region as interconnection is fabricated using a standard 0.18μm CMOS process. Measurement results show a 25.79% photoelectric conversion efficiency under solar simulator illuminations and has a 17.49% improvement compared to the conventional design. Utilizing the proposed solar cells, an on-chip energy harvesting power source has been realized, achieving a maximum conversion efficiency of 10.20% from incident solar power to voltage output power. Despite variations in illumination and load, this power source is able to maintain a relatively stable output voltage of 1V.
... However, their accuracy is generally high. On the other hand, time-domain temperature sensors-as they select digital circuits such as time-to-digital converter (TDC) or frequency-to-digital converter (FDC) [9,10]-can often build most circuits using standard cell libraries, and have strong adaptability, simple structure, small area, and low power consumption. Therefore, it is necessary to determine CMOS temperature sensors with different architectures in advance according to different needs. ...
This paper proposes a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology. The temperature sensor consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), a relaxation oscillator with oscillation frequency independent of temperature (OSC-CON), and a divider circuit cascaded with D flip-flops. Using BJT as the temperature sensing module, the sensor has the advantages of high accuracy and high resolution. An oscillator that uses PTAT current to charge and discharge capacitors to achieve oscillation, and utilizes voltage average feedback (VAF) to enhance the frequency stability of the oscillator is tested. Through the dual temperature sensing process with the same structure, the influence of variables such as power supply voltage, device, and process deviation can be reduced to a certain extent. The temperature sensor in this paper was implemented and tested with a temperature measurement range of 0–100 °C, an inaccuracy of +0.65 °C/−0.49 °C after two-point calibration, a resolution of 0.003 °C, a resolution Figure of Merit (FOM) of 6.7 pJ/K2, an area of 0.059 mm2, and a power consumption of 32.9 μW.
... Compared to voltage domain thermal sensors, TDCs provide better stability and reliability with improved accuracy and low-power requirement. 5,14,15 However, CMOS ring-/relaxation-VCO based TDCs deploy either a bulky op-amp or a series of back-to-back connected inverters, thus consuming a large silicon die-area. 13,[16][17][18] Various metal and semiconductor based thermal sensors are also commercially available in the market. ...
In this paper, we propose a hybrid CMOS and phase-change memory (PCM)-relaxation-oscillator based circuit for temperature-sensing applications. Unlike conventional CMOS temperature sensors based on ring- or relaxation-oscillators, the proposed sensor does not require any curvature calibration technique for linearity improvement of the thermal response. The presented system explores the temperature dependence of Ovonic-threshold-switching voltage (Vth) and DC OFF state resistance (ROFF) of a PCM device. The proposed temperature sensor exhibits a resolution of ∼0.04 °C (for the 0 °C to 80 °C temperature range) with 0.51 nJ energy consumption per conversion in simulations.
... Compared to voltage domain thermal sensors, TDCs provide better stability and reliability with improved accuracy and low-power requirement. 5,14,15 However, CMOS ring-/relaxation-VCO based TDCs deploy either a bulky op-amp or a series of back-to-back connected inverters, thus consuming a large silicon die-area. 13,[16][17][18] Various metal and semiconductor based thermal sensors are also commercially available in the market. ...
In this paper, we propose a hybrid CMOS and phase-change memory (PCM)-relaxation-oscillator based circuit for temperature-sensing applications. Unlike conventional CMOS temperature sensors based on ring- or relaxation-oscillators, the proposed sensor does not require any curvature calibration technique for linearity improvement of the thermal response. The presented system explores the temperature dependence of Ovonic-threshold-switching voltage (Vth) and DC OFF state resistance (ROFF) of a PCM device. The proposed temperature sensor exhibits a resolution of ∼0.04 °C (for the 0 °C to 80 °C temperature range) with 0.51 nJ energy consumption per conversion in simulations.
This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of
, and a VCO tuning linearity of 26%. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz.
A VCO-based temperature sensor with low supply sensitivity is presented. Fabricated in a 65nm CMOS process, the 0.004mm 2 prototype operates with 1V supply and achieves a supply sensitivity of 0.034°C/mV and an inaccuracy of +0.9°C/−0.9°C and +2.3°C/−2.3°C from 0–100°C after 2-point calibration, with and without static non-linearity correction, respectively. For (programmable) resolutions of 1°C-to-0.3°C, the sensor draws 1nJ-to-3.4nJ per conversion, respectively.
Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is using a time-domain delta-sigma (Δ) modulator. This type of TDC with Δ modulator can achieve higher resolution by increasing oversampling ratio, with the advantages of low area and low power consumption. To increase the accuracy by producing true temperature independent time delay, an external reference clock is utilized instead of temperature independent inverter cells for robust operations. The measured temperature sensors demonstrated a minimum power consumption of 480nW and a resolution under 0.1°C. The 3 error of the sensor is 0.99 °C over -20 °C 80 °C temperature range from 10 sample measurement results. The chip area is 0.089 mm² using a Dongbu 0.18-μm CMOS process. The conversion rate is 1.25 samples/s.
This paper presents the first voltage-calibrated CMOS time-domain smart temperature sensor to reduce the cost of mass production. A digitally adjustable relaxation oscillator designed as the temperature sensor vibrates between CMOS-based CTAT, PTAT voltage references with mutual curvature compensation to generate linear temperature-dependent output pulses. Voltage instead of temperature calibration is adopted to alleviate the impact of process variation and TDC is used for output coding. Fabricated in a TSMC 0.18-μm standard CMOS process, the proposed sensor is able to operate at a high speed of 486k samples/sec for SoC thermal monitoring. The active area is merely 0.122 mm2 and the inaccuracy is measured to be less than ±1°C for 15 test chips in a wide temperature range of -40°C to 120°C. The performance is even superior to some chips with one- or two-point temperature calibrations [1-4]. A milestone is established for time-domain smart temperature sensor to get rid of the heavy burden of fixed-temperature calibration with reason error budget.
A miniaturized thermal sensor for use in Intel's microprocessors has been demonstrated in a cutting-edge purely digital process. The circuit shows nearly linear frequency dependence with temperature of 45kHz/°C. The circuit occupies 3.75 × 10-3 mm2 and consumes a current of ~700uA, which makes it suitable to be placed in array on a microprocessor to measure thermal gradients across the die.