IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001 545
A New Simplified Space–Vector PWM Method for
Jae Hyeong Seo, Member, IEEE, Chang Ho Choi, Member, IEEE, and Dong Seok Hyun, Senior Member, IEEE
Abstract—In this paper, a new simplified space–vector pulse
width modulation (SVPWM) method for three-level inverter
is proposed. This method is based on the simplification of the
space–vector diagram of a three-level inverter into that of a
two-level inverter. If simplified by the proposed method, all the
remaining procedures necessary for the three-level SVPWM are
done like conventional two-level inverter and the execution time
is greatly reduced. The dc-link neutral-point potential control al-
gorithms are implemented more easily. And the proposed method
can be applied to the multi-level inverters above three-level. The
validity of the new SVPWM method isverified by experiment with
a 1000 KVA three-level insulated gate bipolar transistor (IGBT)
Index Terms—Multilevel inverter, space-vector PWM, three-
ECENTLY, with the dramatic improvements in high
voltage technologies, high voltage insulated gate bipolar
transistor (HVIGBT) and gate commutated thyristor (GCT) are
expanding the area of their application. For the high perfor-
mance ac drive systems at increased power level, high quality
inverter output with low harmonic loss and torque pulsation
is necessary. In case of the conventional two-level inverter
configuration, the harmonic contents reduction of an inverter
output current is achieved mainly by raising the switching
However in the fieldof high voltage, high powerapplications,
the switching frequency of the power device has to be restricted
below 1 KHz, even with the HVIGBT and GCT, due to the
increased switching loss. So the harmonic reduction by raised
switching frequency of a two-level inverter becomes more diffi-
of a two-level inverter is limited by voltage ratings of switching
devices, the problematic series connection of switching devices
is required to raise the dc link voltage. By series connection,
the maximum allowable switching frequency has to be more
From the aspect of harmonic reduction and high dc-link
voltage level, three-level approach seems to be the most
promising alternative. The harmonic contents of a three-level
inverter are less than that of a two-level inverter at the same
Manuscript received February 25, 2000; revised March 31, 2001. Recom-
mended by Associate Editor S. Y. R. Hui.
J. H. Seo is with the R&D Center, POSCON Corporation, Seoul 136-701,
Korea (e-mail: email@example.com).
C. H. Choiand D.S. Hyun arewith the Department ofElectrical Engineering,
Hanyang University, Seoul 133-791, Korea.
Publisher Item Identifier S 0885-8993(01)05956-7.
Fig. 1. Circuit diagram of a three-level inverter.
switching frequency and the blocking voltage of the switching
device is half of the dc-link voltage. So the three-level inverter
topology is generally used in realizing the high performance,
high voltage ac drive systems .
However, the inherent neutral-point potential variation of a
three-level inverter has to be effectively suppressed to fully uti-
lize the above-mentioned advantages of a three-level inverter.
So many PWM strategies have been proposed to solve the neu-
tral-point potential unbalance problem , , . But many of
them are focused mainly on the neutral-point potential control
method, while still using the complicated dwelling time calcu-
lation and the switching sequence selection method.
In this paper, a simple SVPWM method for three-level in-
verter is proposed. By using the new PWM strategy, dwelling
time calculation and switching sequence selection are easily
done like conventional two-level inverter. And the neutral-point
voltage control algorithm can be easily implemented. In this
paper, the proposed three-level SVPWM method is explained
in detail and verified using 2500 V, 1000 KVA three-level IGBT
IMPLIFIED SPACE–VECTOR PWM METHOD
A. Basic Principles of the Proposed SVPWM Method
Fig. 1 is a circuit diagram of a three-level inverter and the
There are three kinds of switching states P, O, and N in each
phase, so there exist 27 switching states in three phase three-
By using the space–vector diagram of a three-level inverter,
the basic principle of the proposed SVPWM method can be
0885–8993/01$10.00 ©2001 IEEE
546 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001
WITCHING STATES AND TERMINAL VOLTAGES OF A THREE-LEVEL
easily explained. The space–vector diagram of a three-level in-
verter, shown in Fig. 2, can be thought that it is composed of
six small hexagons that are the space–vector diagrams of con-
ventional two-level inverters. Each of these six hexagons, con-
stituting the space–vector diagram of a three-level inverter, cen-
ters on the six apexes of the inner small hexagon as is shown
in Fig. 3. So, if these six small hexagons are shifted toward the
center of the inner hexagon by
, the space–vector diagram
of a three-level inverter is simplified to that of a two-level in-
verter. To simplify into the space–vector diagram of a two-level
inverter as explained above, the following two steps have to be
taken. First, from the location of a given reference voltage, one
hexagon has to be selected among the six hexagons. Secondly
the original reference voltage vector has to be subtracted by the
amount of the center voltage vector of the selected hexagon.
By these two steps, the three-level space–vector plane is trans-
formed to the two-level space–vector plane.
Then the determination of switching sequence and the calcu-
lation of the voltage vector duration time are done as conven-
tional two-level SVPWM method. As the proposed SVPWM
method is same in principle as conventional two-level SVPWM,
various techniques used in two-level SVPWM can be applied to
this proposed method too.
B. Correction of Reference Voltage Vector
In this section, the first procedure for the simplified
three-level space–vector PWM method is described in detail.
By the location of a given reference voltage vector, one hexagon
is selected among the six small hexagons that comprise the
three-level space–vector diagram. The reference voltage vector
should stay at the inner of the selected hexagon. This procedure
divides the three-level space–vector diagram into six regions
that are covered by each small hexagon as shown in Fig. 3. The
in Fig. 3 represents the selected hexagon. There exist
the regions that are overlapped by adjacent small hexagons
in the three-level space–vector diagram. So if the reference
voltage vector stays at those regions,
can have any values that
are possible. Fig. 3(a) and (b) illustrate two possible ways of
selecting the value of
. If those methods shown in Fig. 3(a)
and (b) are used, the value of
at the shaded region of Fig. 2
can have the value of 1 or 2.
Once the value of
is determined, the origin of a reference
voltage vector is changed to the center voltage vector of the
selected hexagon. This is done by subtracting the center vector
of the selected hexagon from the original reference vector, as
shown in Fig. 4. This is summarized in Table II.
Fig. 2. Space–vector diagram of a three-level inverter.
Fig. 3. Simplification of a three-level space–vector diagram.
In Fig. 4, is the original reference voltage vector and
is the corrected reference voltage vector seen from the location
of the (POO), (ONN) vector.
Following is the sample program of this procedure explained
in this section.
Sample Program for the Simplifying of the Three-Level
SEO et al.: NEW SIMPLIFIED SPACE–VECTOR PWM METHOD FOR THREE-LEVEL INVERTERS 547
Fig. 4. Changing the base vector of an original reference voltage vector.
C. Calculation of the Dwelling Times
If the reference voltage vector is redefined as explained in
the previous section, the dwelling times are calculated at the
same manner as conventional two-level SVPWM method. The
calculation of dwelling times can be done more efficiently by
the method presented in  as shown in the following example.
In calculating the dwelling times, the only difference between
the two-levelSVPWM and the three-level SVPWM is the factor
2 appearing at the first two lines of the following example.
Sample Program for the Dwelling Time Calculation
If the dwelling times are calculated, the switching sequence
has to be determined. However the switching sequence is deter-
minedautomaticallyby the valueof
.Thatis, onthebasis of the
center voltage vector of the selected hexagon, the switching se-
quence is determined as conventional two-level inverter. For ex-
ample, in case of Fig. 4, the switching sequence will be (POO)-
(PON)-(OON)-(ONN). If the (ONN) vector is selected as a base
and the notations used in two-level space–vector diagram are
adopted, the switching sequence can be expressed as (111)-
(110)-(010)-(000). This switching sequence is exactly the same
as that of conventional two-level SVPWM. Therefore in deter-
mining the switching sequence, the only thing to do is selecting
EFERENCE VOLTAGE VECTOR CORRECTION OF THE PROPOSED
Fig. 5. Neutral-point potential control of a three-level inverter.
Fig. 6. Application of theproposed SVPWM methodto the four-levelinverter.
theswitchesthat haveto be enabled to changetheir statesamong
the four switches in each phase. This is realized by simple logic
gates using the value of
D. Neutral-Point Potential Control
It is well known that there are two methods controlling the
neutral-point potential of a three-level inverters. The first is
changing the switching sequence and the second is rearranging
the time distribution of the redundant voltage vectors. These
two methods can be easily implemented with the proposed
SVPWM method. The switching sequence is easy to change
using the index
1) Method 1: Changing the Switching Sequence
548 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001
Fig. 7. Test results of the proposed SVPWM method with 100 kW induction motor. (a) Line-to-line voltage and phase current at
Hz . (b) Line-to-line
voltage and phase current at
Hz . (c) Line-to-line voltage and dc-link voltage error at Hz . (d) Line-to-line voltage and dc-link
at Hz .
If the reference voltagevectorstays at theregion,thatis
overlapped by adjacent small hexagon, the neutral-point
potential can be controlled by changing the switching se-
quence. When the reference is given as in Fig. 5(a), the
can have the value 1 or 2 as explained in the pre-
ceding section. In this case, the switching sequence can
be given in the order of (POO)-(PON)-(OON)-(ONN) or
(PPO)-(POO)-(PON)-(OON). The former sequence is the
case that the index
has the value of 1, and the latter is
the case that the index
has the value of 2. In Fig. 5(a),
is the original reference voltage vector and is
the corrected reference voltage vector when the index
has the value of 1. is the corrected reference voltage
vector when the index
has the value of 2. If the former
switching sequence is selected and the load current flows
out from dc-link capacitors, the load current will dis-
charge the lower capacitor, while charging the upper ca-
pacitor of the dc-link. But on the contrary, if the latter
switching sequence is selected, the upper capacitor is dis-
chargedandthe lowercapacitor is charged. So if the value
is changed depending on the voltage error
and the direction of the power, the neutral-point potential
is controlled. This is realized by simple procedure, sub-
tracting or adding 1 from the value of
2) Method 2: Rearranging the Time Distribution of the Re-
dundant Voltage Vectors
If the reference voltage vector stays at the region C in
Fig. 5(b), the switching sequence is given as follows:
, , , and are dwelling times of the corre-
sponding voltage vectors.
In this case, the neutral-point voltage is controlled by
adjusting the value of Tip and Tin in response to the
voltageerrorandtothe load conditions .As the voltage
vector (POO) and (OON) are same in magnitude and in
phase, changing the dwelling times of the two vectors has
SEO et al.: NEW SIMPLIFIED SPACE–VECTOR PWM METHOD FOR THREE-LEVEL INVERTERS 549
Fig. 8. Test results of the proposed SVPWM method with RL load. (a)
line-to-line voltage and phase current at
Hz ; (b) line-to-line voltage
and phase current at
noeffectonthe outputvoltagevectoronly if the following
equations are satisfied
The underlined part of the sample program in Sec-
tion II-C shows this process.
E. Application to the Multilevel SVPWM
The proposed SVPWM method is also applicable to the
multi-level SVPWM above three-level. For example, the
four or five-level space–vector diagram can be simplified to
the three-level space–vector diagram on the same principles
explained in this paper. Fig. 6 shows the case of four-level
SVPWM. From Fig. 6, we can know that the space–vector
diagram of a four-level inverter is composed of six three-level
space–vector diagrams whose center vectors are shown as cir-
cles. If it is simplified to the three-level space–vector diagram,
the remaining procedures for the SVPWM can be done like that
of the proposed three-level SVPWM method.
The proposed SVPWM method was programmed with the
TMS320C31 DSP board and the 3300 V, 1200 A, EUPEC
IGBT’s are used to develop the three-level inverter. The inverter
was designed for driving the 630 kW, 2500 V induction motor,
but the 3300 V, 100 kW induction motor and RL load was used
for the test.
The test results of the developed system are shown in Figs. 7
and 8. The waveforms shown in Fig. 7 are the test results of
driving the 3300 V, 100 KW induction motor at 3600 V dc-link
voltage. Fig. 8 shows test results when the RL is used as a load
of inverter at 3250 V dc-link voltage. From the test results, we
can know that the proposed SVPWM is good at pulse-width
modulation of a three-level inverter and the voltage balance of
the dc-link is controlled fairly well in the whole speed range
of the motor, even though the proposed method is simple in its
In the field of high power, high performance applications, the
three-level inverter seems to be the most promising alternative.
In this paper, a new simplified space–vector PWM method for
the three-level inverter is proposed and described in detail. The
proposed SVPWM method has the following features.
1) The switching sequence is determined without a look-up
table, so the memory of the controller can be saved.
2) The dwelling times of voltage vectors are calculated at
the same manner as two-level SVPWM. Thus the pro-
posed method reduces the execution time of the three-
3) It is easy to implement the neutral-point potential control
4) It can be applied to the multi-level SVPWM method
The validity of the presented SVPWM method is verified by
experimental results. The developed three-level IGBT inverter
system was applied to the #2 steel making factory of Pohang
Steel Corporation (POSCO).
 J. H. Suh, “A design of a new snubber circuitfor three-levelgate turn-off
thyristor inverters,” in Proc. EPE Conf., 1995, pp. 573–578.
 D. S. Hyun, “A Novel PWM Scheme for a Three-Level Voltage Source
InverterwithGTOThyristors,”inProc. IAS Conf.,1994,pp.1151–1157.
 R. Jotten, “A fast space–vector control for a three-level voltage source
inverter,” in Proc. EPE Conf., 1991, pp. 70–75.
 J. S. Kim, “A novel voltage modulation technique of the space vector
PWM,” Trans. Inst. Elect. Eng. Jpn., vol. 116-D, no. 8, pp. 820–825,
 S. Tamai, “3-level GTO converter-inverterpair system for large capacity
induction motor drive,” in Proc. EPE Conf., 1993, pp. 45–50.
550 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001
Jae Hyeong Seo (M’96) was born in Kyeong-San,
Korea, on May 21, 1971. He received the B.S. and
M.S. degrees in electrical engineering from Hanyang
University, Seoul, Korea, in 1994 and 1996, respec-
Since 1996, he has been with the Department of
Power Electronics, R&D Center, POSCON Corpo-
ration, Seoul, as an Associate Research Engineer,
where he has been engaged in the development
and design of high voltage, high power converter
systems, and their control strategies. His current
research interests are high performance, high voltage motor drive systems,
power quality systems, and control problems in power electronics.
Chang Ho Choi (M’84) received the B.S. degree
from Ajou University, Suwon, Korea, in 1979
the M.S. degree from Seoul National University,
Seoul, Korea, in 1984, and the Ph.D. degree from
Hanyang University, Seoul, in 2000, all in electrical
From 1983 to 1986, he had been withthe Research
Institute of LG IndustrialSystems Co., Ltd., Anyang,
Korea, where he was a Senior Researcher in the
Department of Power Electronics. From 1987 to
1990, he had been with Korea Servo Corporation,
Suwon, as a Principal Researcher in the Department of Servo Motor Drives.
Since 1990, he has been with the Department of Power Electronics, R&D
Center of POSCON Corporation, Seoul, as a Chief Researcher. His current
research interests are high-power motor drive system for continuous processing
lines, power quality systems, high-voltage pulse power applications, and
energy saving systems.
Dong Seok Hyun (S’79–M’83–SM’91) received the
B.E. and M.E. degrees from Hanyang University,
Seoul, Korea, in 1973 and 1978, respectively, and
the Ph.D. degree from Seoul National University,
Seoul, in 1986, all in electrical engineering.
From 1976 to 1979, he was with theAgency of De-
fense Development, Korea, as a researcher. He was
a Research Associate in the Department of Electrical
Engineering, University of Toledo, Toledo, OH,from
1984 to 1985, and a Visiting Professor of electrical
from 1988 to 1989. Since 1979, he has been at Hanyang University, where he is
currently a Professor in the Department of Electrical Engineering and Director
of the Advanced Institute of Electrical Engineering and Electronics (AIEE).
He is the author of more than 80 publications concerning electric machines,
high-power engineering, power electronics, and motor drives. His research in-
terests include power electronics, motor drives, digital signal processing, trac-
tions, and their control systems.
Dr. Hyun is a member of the Korean Institute of Electrical Engineers, the In-
stitution of ElectricalEngineers, U.K,and the IEEEPower Electronics, Industry
Applications, Circuits and Systems, and Electron Devices Societies.