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Universal Waveforms Processor

Martin Danneberg∗, Ahmad Nimr∗, Nicola Michailow†, Shahab Ehsanfar∗, Maximilian Matth´

e∗,

Ana-Belen Martinez∗, Dan Zhang∗and Gerhard Fettweis∗

∗Vodafone Chair Mobile Communication Systems, Technische Universit¨

at Dresden, Germany

†National Instruments Corp., Austin, TX, USA

{first name.last name}@ifn.et.tu-dresden.de, nicola.michailow@ni.com

Abstract—This paper presents a ﬂexible physical layer (PHY)

implementation based on the National Instruments (NI) USRP-

RIO software-deﬁned radio (SDR) platform. The implementation

allows to reconﬁgure important parameters of the physical layer

during run-time to create a multitude of modern waveforms.

In addition, a ﬁrst performance evaluation of the transceiver is

given. The source code of the ﬁeld programmable gate array

(FPGA) design is freely available as open source.

Index Terms—PHY, OFDM, GFDM, FPGA, SDR.

I. INTRODUCTION

The demand to achieve higher data rates for the enhanced

Mobile BroadBand (eMBB) scenario and novel ﬁfth genera-

tion (5G) use cases like ultra-reliable low latency communi-

cation (URLLC) and Massive Machine-type Communications

(mMTC) drive researchers and engineers to consider new

concepts and technologies for future wireless communication

systems. The goal is to identify promising candidate technolo-

gies among a vast number of new ideas and to decide, which

are suitable for implementation in future products. Fig. 1 gives

a simpliﬁed overview of the evaluation process.

New ideas and concepts typically ﬁrst undergo extensive

software simulations, which allow to make ﬁrst predictions

on the expected performance. After downselection of the

candidates, selected aspects of the envisioned system can be

implemented on a hardware-accellerated platform, e.g., SDR,

in order to learn about real-time behavior and over-the-air per-

formance with real RF components. Technologies that prove

promising in this stage can be further evaluated in testbeds,

where the focus shifts towards the interworking of different

technology building blocks and the realization of complete

end-to-end applications. New concepts and technologies that

have been proven to work in practice will ultimately ﬁnd their

way into new standards and lastly, industry will adopt them

in future products.

In this paper we present an FPGA-based, real-time imple-

mentation of a modulator/demodulator prototype for multicar-

rier waveforms [1], which provides a large number of degrees

of freedom to the experimenter and offers the ﬂexibility

required for the practical evaluation of 5G concepts. Speciﬁc

example applications include experiments with ﬂexible nu-

merology, which is a key differentiator of 5G New Radio (NR)

as compared to fourth generation (4G) long term evolution

(LTE). In addition, characteristics of diverse waveforms can

Products

Standards

Testbeds

Prototypes

Simulations

New ideas

and concepts

Predict expected performance

based on suitable models and

reasonable assumptions.

Find reasonable simplifactions, al-

gorithm partitioning and estimate

implementation complexity.

Demonstrate the interworking of dif-

ferent components under real-world

conditions and in real-time.

Decide which technologies should be in-

cluded in future products.

Fig. 1: Simpliﬁed process of downselection

be analyzed. The presented platform is a building block for

testbeds that will in the future assist the design of 5G radio

interfaces and network architectures. The following sections

give a detailed description of the available features and how

they are implemented. First, in Section II, we represent a

uniﬁed modem model. In Section III, we detail the transceiver

design. The evaluation of the design is given in Section IV.

Finally, we conclude the paper and highlight the future work

in Section V.

II. MULTICARRIER WAVEFORMS OVERVIEW

In general multicarrier modulation, a stream of data symbols

is split into time-frequency sub streams dk,m,i, where kis the

index in the frequency domain known as subcarrier, mthe

index in time domain known as subsymbol and irepresents

the block index. Each stream is modulated with transmitter

pulse shapes gt

k,m[n]. The discrete transmitted signal can be

written as

xt[n]=

∞

i=−∞

k∈Kon

m∈Mon

dk,m,igt

k,m[n−iNs]

=

∞

i=−∞

xt

i[n−iNs].

(1)

where Nsis the symbol spacing, Kon and Mon are the sets

of active subcarriers and subsymbols, respectively, and xt

i[n]

978-1-5386-1478-5/18/$31.00 c

2018 IEEE

is the i-th multicarrier symbol, which is given by

xt

i[n]=

k∈Kon

m∈Mon

dk,m,igt

k,m[n].(2)

In common modulation techniques, e.g. [2], [3], gt

k,m[n]has a

ﬁnite length Ntand can be generated using a prototype pulse

shape g[n]through circular shift in time and frequency such

that

gt

k,m[n]=g[n−mK −n0N]ej2πk

Kn,

n=0,··· ,N

t−1,(3)

where •Ndenotes the modulo Noperation. There, Kis

the number of subcarriers, Mthe number of subsymbols

N=MK ≤Nt. Let Nobe the overhead that represents a

cyclic preﬁx (CP) and/or cyclic sufﬁx (CS), where Nt=

N+No. The type of overhead is deﬁned by the time shift

n0. For instance, when n0=Nowe get pure CP. Based on

that, we can deﬁne a core block xi[n]of length Nsamples

such that

xi[n]=

k∈Kon

m∈Mon

dk,m,ig[n−mKN]ej2πk

Kn.(4)

The relation between the core block and the actual transmitted

block is given by

xt

i[n]=xi[n−n0N].(5)

Two speciﬁc cases evolve depending on Nsand Nt

•Ns≥Nt: the transmitted blocks xt

i[n]do not overlap

and the total transmitted signal xt[n]can be generated by

transmitting xt

i[n]independently. Here, NP=Ns−Nt

represents a guard interval between sequential blocks.

Orthogonal frequency division multiplexing (OFDM) and

Generalized frequency division multiplexing (GFDM)

belong to this case.

•Ns<N

t:xt[n]can be still produced based on xt

i[n],

however, additional overlapping of length No=Nt−Ns

must be considered. In this, the last Nosamples of the

current xt[n]are added to the ﬁrst Nosamples of the

next xt

i[n]. An example of this case is Filtered Multitone

(FMT) [4] with overlapping factor M. In which, Mon

contains one subsymbols and the remaining M−1are

non-active. The overlapping by No=K(M−1) com-

pensates this overhead. Another example is the weighted-

overlap-and-add (WOLA) processing in [5], where the

ramp-down of the i−1-th windowed block overlaps with

ramp-up of the i-th block.

As a result, by the conﬁguration of the prototype pulse shape

gin addition to the parameters, Ns,Nt,n0,K,M,Kon and

Mon we can produce most of the state of the art waveforms.

As illustrated in Fig 3, the process of waveform generation

can be divided into two main stages; the ﬁrst is computing

the core block xi[n]according to (4). Let us collect the data

symbols dk,m,i for the ith transmit block in a sequence di

using the relation di[mK +k]=dk,m,i. Then, as shown in

[6], the core block generation at the transmitter side can be

written as

xi[mK +k]=

M−1

m=0

g[(m−m)K+kN]D[mK+k]

(6)

with D[mK+k]=K·IDFT{di[mK+•]}[k].

(7)

Similarly, at the receiver side, a linear receiver using the

receive ﬁlter γ[n]is applied to the core block xi[n]by

ˆ

dk,m,i =

N−1

n=0

xi[n]γ[n−mKN]e−j2πnk

K.(8)

In analogy to the transmitter, we can reformulate this to

Xi[mK +k]=

M−1

m=0

γ[(m−m)K+kN]xi[mK+k]

(9)

ˆ

di[mK +k]=

K−1

k=0

e−j2πkk

KXi[mK +k](10)

=DFT{Xi[mK +•]}[k].(11)

Apparently, the modulator and demodulator have the opera-

tions (6), (9) in common, which we denote as the core ﬁltering

operation. In addition, at the transmitter an inverse fast Fourier

transform (IFFT) is employed before the core ﬁltering whereas

at the receiver side, the according fast Fourier transform (FFT)

is applied after the core ﬁltering. Hence, the same ﬁltering and

FFT1implementation can be reused at both transmitter and

receiver side.

The subsequent stage at the transmitter corresponds to block

multiplexing where the CP/CS overhead is added to generate

xt

i[n]as done in (5). At this stage, further signal processing

items, such as windowing or ﬁltering, can be performed

afterwards to support waveforms like F-OFDM [7] or WOLA-

OFDM [5]. Then, the transmitted signal is generated according

to (1) considering overlapping or zero padding. Finally, the

discrete block is converted to an analogue signal using an

digital-to-analogue converter (DAC) with sampling rate Fs.

The subcarrier spacing can be derived as Δf=Fs

Kand the

bandwidth can be controlled via Kon. At the receiver side, a

similar block is employed to perform receiver-side windowing

to suppress collection of spectral leakage from adjacent signals

and CP/CS removal.

III. TRANSCEIVER DESIGN

The block diagram in Figure 2 depicts the components

which have been integrated in the overall demonstrator. Except

for the blue marked blocks supplied by NI, all other blocks

are implemented highly ﬂexible to support the various require-

ments of 5G wireless networks. The focus of this paper lies

on the PHY aspects of a 5G transceiver, since these signal

processing algorithms have to be implemented in FPGA to

1Switching between FFT and IFFT does usually incur only a neglible

overhead.

support the throughput and latency requirements. In particular,

we focus on describing the core modem implementation.

medium access control (MAC) and higher layers will be

implemented using software components running on standard

PC hardware as those are not as time critical to require

specialized hardware accelerator support. The design follows

a handeshaking protocol, where each unit is indicating the

previous unit if it can accept data. This way samples cannot

get lost during the processing and a slower radio-frequency

(RF) sampling rate slows down the signal processing.

Control PC

Host controller

UDP

data

source

To GFDM block

UDP

data

sink

To UDP packet

QAM

Mapper

Preamble

Multiplexer

SDR

D/A + RF

Modulator

Resource

Mapper

CP/CS

Windowing

FPGA

Channel

Estimation

Synchronization

Decoder

SDR

RF + A/D

QAM

Demapper

Channel

Equalization

Demodulator

Resource

Demapper

UDP

Configu

ration

Encoder

Listen before Talk, Sensing

FPGA

Controller

Fig. 2: Block diagram of the transceiver.

A. Baseband modem

The baseband signal processing is conducted by the resource

mapper, modulator, demodulator and resource demapper as

depicted in Figure 3. A ﬁrst implementation of the modulator

has been presented in [8]. Before the modulator, the incoming

data don

ihas to be mapped to the two-dimensional time-

frequency resource grid. Further, control channel or additional

training sequences should be multiplexed into the data stream

dias well. To accomplish this, the resource mapper as depicted

in Figure 3 has several input sources. Whenever a new data

block is going to be created the multiplexing pattern is read-out

of the memory to control the switch at the output of this block.

This mechanism allows to support any user-deﬁned resource

grid which can be adapted during run-time to the respective

standard as also pre-deﬁned training-sequences can be read

out of a memory.

As mentioned, the modulation and demodulation operation

can be separated into two main functional blocks. The ﬁrst

block is the IFFT to convert the data into time domain and

the second block applies the actual modulation process. In this

context it is called core-modem. The demodulation operation

consists of the same processing blocks in a reversed order.

First the demodulation has to be applied on the received data

via the core-modem block and afterwards it is transformed

back into frequency domain by a FFT. The modulation and

demodulation process inside the core-modem are performed

with the same architecture, the only difference are the used

ﬁlter coefﬁcients.

The ﬁrst task of the core-modem block is to split the

incoming inverse discrete Fourier transform (IDFT) output

stream δinto Msub-symbols with Ksamples each, e.g. δ0,

δ1. In the following, each individual sub-symbol has to be

repeated Mtimes, such that the ﬁlter gwith Nsamples can

be applied. Therefore, the Ksamples of each sub-symbol are

stored inside an independent subsymbol data memory bank.

These Mparallel banks are read out sample by sample in

parallel. The ﬁlter gis stored in Mparallel subsymbol ﬁlter

banks, too. Each of the ﬁlter memory bank contains Ksamples

of the ﬁlter which are representing a sub-symbol as similar to

the data. However, the ﬁlter has to be multiplied with the data

in a circular shifted way. This is implemented by connecting

a different ﬁlter bank to the multiplier for each data memory

bank. For instance, ﬁrst the Ksamples of the ﬁrst sub-symbol

δ0are multiplied with g0. Afterwards the same Ksamples

are multiplied with g1until they have been multiplied with

all ﬁlter coefﬁcients. In the case of the second sub-symbol,

the Ksamples stored inside the memory are multiplied ﬁrst

with g1and then with g2. The last step of the process is to

accumulate the contributions from all Mparallel branches to

get the transmit signal.

B. Post modem processing

After the modulator the CP and CS, a additional time-

window and a preamble have to be added. The general frame

format of the implemented transceiver is based on a preamble

which is used for synchronization and channel estimation and

one or several data blocks concatenated to each other. Figure 4

depictes the general frame format. CP and CS can be applied

on both preamble and data block. NP,CP deﬁnes the length

of the CP for the preamble, NCP for the data block, NP,CS

deﬁnes the length of the CS for the preamble and NCS for

the data block. It is assumed that the window is symmetric,

thus the length of one half is given by NP,W and NW.NP

denotes the length of the preamble. A detailed overview which

frame structure and PHY parameters are suitable for different

scenarios is given in [9].

CP GFDM block CS

NN

CS

N

CP

NWNW

PreambleCP CS

N

P

N

P,CP

NP,W

N

P,CS

NP,W

Fig. 4: Considered frame structure with one preamble and one

data block.

Different to the data, the complete preamble is precalculated

on the host computer. Therefore, it will be written to a memory

during the conﬁguration phase of the transceiver. The CP, CS

for the data is added via three ﬁrst in, ﬁrst out buffers (FIFOs)

in Figure 3. A control logic handles which data is stored inside

which FIFO and in which order the content is read-out. In the

end, all FIFOs can be seen as variable delays to shift the data

samples into the right output order.

The windowing unit follows, where only the rising half is

stored inside a memory. An integrated counter in the control

logic counts up until NWis reached to trigger the memory for

the appropriate samples. During the main data block the unit

FIFO

Payload

FIFO

Control chann el

BRAM

Reference

signals

BRAM

Resource map

MUX iƑKDEMUX

BRAM 0

Subsymbol

memory

BRAM ...

Subsymbol

memory

BRAM 15

Subsymbol

memory

BRAM 0

Filter

memory

BRAM ...

Filter

memory

BRAM 15

Filter

memory

MUX

•

•

•

∑

FIFO

CP

FIFO

Payload

FIFO

CS

DEMUX MUX

BRAM

Preamble

BRAM

Window

•

CP/CS + WindowingPulse Shaping Unit

Resource Mapper Block multiplexing

on

i

d

Transform

>@

on

on

ii

on

dd

on

on

i

d

ii

Axd

i

x

0i

N

xnn

ªº

¬¼

>@

t

is

i

xn N

¦

>

i

>

¦

MUX

>@

t

xn

t

i

x

on

on

KMgNtn0Ns

G

...

GG

0

GG

m

GG

g0

g...

gm

Fig. 3: Block diagram of the transmitter excluding encoder, symbol mapper and the RF logic.

is disabled. Finally, the same counter is decreased to create

the falling part.

Whenever the controller has ﬁnished reading the ﬁrst data

block of a frame into the data-FIFO, the preamble insertion

unit is triggered to push the preamble samples to the DAC.

C. Inner Receiver: Synchronization and Channel Estimation

Despite focusing on the core modem in this paper, a

complete transceiver chain requires adequate synchronization

and channel estimation blocks. For the present evaluation,

we employ a preamble-based synchronization and channel

estimation. The synchronization algorithm is derived from the

Schmidl-Cox algorithm [10] and in detail described in [11].

For the channel estimation, a frequency domain least-squares

estimator with subsequent linear interpolation is implemented

on the real-time platform. In particular, the channel estimation

unit already provides the inverse channel coefﬁcients for the

subsequent frequency domain channel equalizer. Hence, the

equalizer will only employ multiplications instead of divisions

in the signal’s frequency domain, which can reduce overall

latency when multiple payload blocks share a common pream-

ble.

D. Additional Units

Currently, a convolutional code with code-rate 1

2and a

QPSK mapper is included as these were available processing

units in LabVIEW. Additionally, a channel sensing function

is implemented facilitating the second RF chain of the SDR

platform. It consists of a power spectral density (PSD) calcula-

tion unit followed by a ﬁlter. This allows to scan the spectrum

in real-time and support listen-before-talk access schemes via

ﬁltering the received energy in a given frequency band.

E. Flexible Conﬁguration

Using the described blocks, a multitude of waveforms for

wireless communications systems can be emulated. A subset

of existing possibilities is shown in Table I. There, for different

waveforms, the signal processing blocks are parametrized

differently or even bypassed, such that in total the desired

waveform is generated. For example, multicarrier waveforms

such as OFDM or ﬁlter bank multicarrier (FBMC) employ

the FFT operation at the modem to obtain a frequency-division

multiplexing structure. On the other hand, the deﬁnition of the

resource map strongly depends on the actual frame structure

and no general statement can be made. Here, the ﬂexibil-

ity of the resource mapper to support different waveforms

shall be emphasized. Finally, the pulse shaping unit cannot

only be used for classical ﬁltering, but it can also serve as

the spreading operator for direct-sequence spread spectrum

(DSSS) signalling. Further, if the signal processing of one

frame is ﬁnished the conﬁguration can be switched within 20

clock cycles. This can be achieved using the presented memory

structures as chaches for several conﬁgurations. In this case

the other conﬁgurations are stored using a address offset inside

the memory, such that by adding a constant offset a different

part with a different conﬁguration is accessed during the signal

processing.

IV. TRANSCEIVER EVALUATION

The full-duplex capable FPGA implementation of the

transceiver ﬁts into one NI USRP-RIO 2953R SDR platform.

In this section the latency and the performance on an additive

white Gaussian noise (AWGN) channel is evaluated.

The transmit latency of the processing in FPGA clock cycles

can be expressed as

LTX =(N+8)

Encoder +(7+N)Resource Mapper

+LFFT(K)+(N+ 23)Modulator

+(N+NCP +NCS )CP&CS + (10)Windowing +N.

(12)

The latency is shown based on the input of the ﬁrst data sample

at the encoder towards the last sample given to the RF control

logic. The index of each bracket is indicating the latencies

introduced by speciﬁc subblocks. It is assumed, that the RF

bandwidth is high enough to not stall the transmitter. Further,

all subcarriers are allocated with payload. The latency of the

XILINX FFT core is stated as LFFT(K)[16] and for the DFT

Waveform Resource Mapper FFT Pulse shaping CP/CS Windowing Overlapping Preamble

OFDM Frame-dependent ON OFF ON OFF OFF Frame-

dependent

LTE Pilot/Control ON OFF ON OFF OFF OFF

WiFi Header/Payload ON OFF ON OFF OFF ON

Single-Carrier Frame-dependent OFF OFF ON OFF OFF Frame-

dependent

5G NR [7] Pilot/Control ON OFF ON ON ON OFF

GFDM [12] Frame-dependent ON GFDM pulse ON ON OFF Frame-

dependent

FBMC [13] Pilot/Control ON FBMC pulse OFF ON ON OFF

Spread-spectrum

[14] Frame-dependent OFF Spreading function OFF OFF OFF Frame-

dependent

Chirp-Based

[15] Frame-dependent ON Chirp function ON OFF OFF Frame-

dependent

TABLE I: Conﬁguration for waveform generation

core as LDFT(N)[17]. The receiver latency behaves as

LRX =(5×396)Synchronization +(11+2×LDFT (N))Equalizer

+LFFT(K)+(N+ 23)Demodulator

+(9)

Demapper +2×((49)Decoder +N).

(13)

Here it is assumed that the input samples are arriving with

40MHz. Further, the syncronization unit operates with a

40MHz clock rate, which is a ﬁve times longer processing

time than other FPGA modules. The decoder runs with a

100MHz clock and therefore needs twice the time. Any other

signal processing block reaches the 200MHz clock rate. In

addition, it is assumed that the channel has been estimated

already and the channel coefﬁcients are stored inside the

equalizer unit, e.g. calculated based on the preamble of a

previous data frame. Fig. 5 and Fig. 6 show the achieved

latencies depending on the number of samples for one data

frame. In both ﬁgures the minimum latency is depicted in

case a single-carrier waveform is created and the maximum

latency for the GFDM case where all processing units are

needed. The processing time of the FFTs impacts the overall

processing latency. In the graphs this is visible as a step

where the total amount of samples Nis the same, however

the number of subcarriers Kand thus the FFT latency is

increasing. Both transmit and receive latency are in all cases

below 100μs such that the transceiver leaves enough time for

higher network layers to fulﬁl the targeted latencies deﬁned

by 5G communications. The performance of the implemented

transceiver is ﬁrstly evaluated in the laboratory using a cable

setup between USRP transmit port and recieve port to emulate

a AWGN channel. The noise can be varied to simulate different

signal to noise ratio (SNR) levels using a second NI USRP-

RIO 2953R. All components are connected via cables such that

the channel is deﬁned mainly by the generated noise. A two-

way RF combiner realizes the summation between noise and

Fig. 5: The transmit latency depicted over Nat 200MHz clock

rate. The results for the ﬁrst 200 samples are shown in the

upper corner for better readability.

the transmitted data. The conﬁguration used by the transceiver

are represented in Table II. Fig. 7 shows the achieved result

Filter Raised-cosine with roll-off factor 0

(M,K, CP, CS ) (9,64,32,16)

Mon {1,··· ,8}

Kon {2,··· ,28}∪{37,··· ,62}

Fs20MHz

Frame length 80 Bytes

TABLE II: Evaluation parameters

for different SNRs, where the SNR is estimated based on

the transmitted and received preamble in AWGN channel.

The simulation is using a complex ﬂoating point reference,

while the FPGA implementation uses complex ﬁxed-point

with 32 bits precision. The performance is consistent with

Fig. 6: The receive latency depicted over Nat 200MHz clock

rate. The results for the ﬁrst 200 samples are shown in the

upper corner for better readability.

Fig. 7: Measurement results using the presented setup.

the simulations with a difference of up to 1 dB due to the

reduced precision of the FPGA signal processing. Moreover,

the presented architecture achieves up to 9.6Mbit/s throughput

under the given conﬁguration and conditions.

V. C ONCLUSION

In this paper a ﬂexible FPGA transceiver design for modern

waveforms is presented. It allows ﬂexible reconﬁgurations

such as changing the number of subcarriers and subsymbols,

the length of the CP and CS. In addition, arbitrary pulse

shaping ﬁlters or recieve ﬁlters, windowing functions and

preambles are supported as well. With the proposed transceiver

architecture, a multitude of waveforms can be generated by

simply reconﬁguring the device without the need to provide a

specialized implementation for each waveform. Hence, PHY-

level real-time evaluations using different waveforms becomes

feasible and aids academia and industry understanding the

beneﬁts and limitations of diverse waveforms. Further, the pre-

sented transceiver design allows to change its waveform con-

ﬁguration quickly and therefore supports research on mixed

numerology applications. [18]

ACKNOWLEDGMENT

This work has been supported by National Instruments with

hardware, software and technical support. This project has

received funding from the European Union’s Horizon 2020

research and innovation programme under grant agreement No

732174 (ORCA) and grant agreement No 688116 ”eWINE”.

This work has received support from Prof. Dr. Mendes and

his team at INATEL, Brazil.

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