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Three-Phase Three-Level T-type Grid-Connected

Inverter with Reduced Number of Switches

Necmi Altin

1

, Ibrahim Sefa

1

, Hasan Komurcugil

2

and Saban Ozdemir

3

1

Department of Electrical and Electronic Engineering, Faculty of Technology, Gazi University, Ankara, Turkey.

2

Department of Computer Engineering, Eastern Mediterranean University, Gazimağusa, Via Mersin 10, Turkey.

3

Department of Energy Systems Engineering, Faculty of Technology, Gazi University, Ankara, Turkey.

naltin@gazi.edu.tr, isefa@gazi.edu.tr, hasan.komurcugil@emu.edu.tr, sabanozdemir@gazi.edu.tr

Abstract— In this study, a three-phase three-level T-type neutral

point clamped grid connected inverter with reduced number of

switch is proposed for distributed generation systems. The

proposed inverter topology has only two legs and totally eight

semiconductor switches. Thus, advantageous multi-level inverter

technology has been achieved with less number of

semiconductor switches resulting in reduced circuit complexity.

The proportional-resonant controller in stationary reference

frame is designed to control the proposed inverter, thus fast

dynamic response and good reference tracking ability is

obtained with zero steady-state error. The feasibility and correct

operation of the proposed system is validated through

MATLAB/Simulink simulation studies. The obtained results

show that proposed three-phase three-level T-type inverter

exhibits comparable performance with the conventional T-type

inverters. Furthermore, total harmonic distortion level of the

output current is computed as 2.07%, which is in accordance

with the limits specified by the international standards such as

IEC61727 and IEEE1547.

Index Terms— T-type, three-level inverter, two-leg inverter,

reduced number of switches, PR controller, grid interactive.

I. INTRODUCTION

The voltage source inverters (VSI) are commonly used in

grid connected inverter operations. Multi-level inverter

topologies have been widely used in grid-connected systems

to provide good waveform quality with reduced total harmonic

distortion (THD) at the expense of increased controller

complexity [1]. However, multi-level inverters offer some

advantages such as less filter requirement, electromagnetic

interference (EMI) level reduction, and improved efficiency as

well. Some of these multi-level inverter topologies also allow

the use of ordinary semiconductor switches at high power

level which make their usage more common and cheaper.

Although different multi-level inverter topologies have been

proposed in the literature, the neutral point clamped (NPC)

inverters, the cascaded H-bridge (CHB) inverters and flying

capacitor (FC) (or capacitor clamped) inverters are more

common.

In spite of the fact that multi-level inverters provide

significant increase in the power levels and offer some

advantages, they have some limitations and drawbacks. The

CHB multi-level inverter topology requires isolated DC

voltage sources. The FC multi-level inverter requires large

capacitor which increases the size as well as the cost. The

NPC inverter suffers from the voltage and power loss

unbalance problems. Fortunately, this problem can be solved

by modifying circuit topology and/or control method [2,3].

Although, this has made the use of the NPC inverter more

attractive, it requires an extra effort. Since the modified NPC

structure increases the complexity slightly, T-type inverters

have been proposed as an alternative solution [4]. Besides the

advantages of the conventional NPC topology such as

eliminating isolated power source and large capacitor

requirements of CHB and FC inverters, T-type inverters have

also fewer components than NPC inverters.

However, the cost, size and complexity of all multi-level

inverter topologies are higher than that of two-level inverters

which can be considered as the major problem multi-level

inverters. The main reason behind this problem is the

necessity of a high number of PWM output capability

processors, a large number of semiconductor switches and

driver requirement. Neither the customers nor the

manufacturers appreciate any increase in the number of

components, size, cost and complexity. Power electronic

researchers focus on converter topologies with reduced switch

count and complexity, and present more compact and cost-

effective inverter topologies [5-8]. The two-leg inverter has

been proposed in place of commonly used conventional three-

phase two-level inverter [9-11]. This structure generates three-

phase output voltages by conventional H-bridge inverter

structure also known as B4 inverter. Furthermore, these

structures are combined with impedance networks to provide

step-up ability [12]. However, there is limited number of

studies for multi-level inverters with the reduced number of

switches. In the past literature, the nine-level inverter [13], the

n-level inverter such as 53-level [14] and the multiple-poles

multi-level diode-clamped inverter [15] with reduced number

978-1-5386-4478-2/18/$31.00 ©2018 IEEE

2018 6th International Istanbul Smart Grids and Cities Congress and Fair (ICSG)

58

of switches have been proposed. Although these studies are

good and new horizons, they have some drawbacks such as

employing coupled inductors [13] and bi-directional switch

requirements [14, 15]. There is no proposed structure and

control method for T-type inverter with reduced number of

switches.

In this study, three-phase three-level T-type grid-

connected inverter with two-leg structure is proposed. Since

only two legs are required for a three-phase three-level

inverter, the number of semiconductor switches is reduced by

a factor of one third. On the other hand, the grid current is

controlled by using proportional-resonant (PR) controller.

Although, PI and PID controllers provide satisfactory transient

and steady-state performance for DC applications, their

performances for AC signals are poor [16-18]. The PR

controller adds a resonant pole at specific frequency, thus a

high gain value is obtained at this specific frequency (resonant

frequency). Therefore, the PR controller provides high

performance in AC signal tracking applications such as grid

interactive inverter applications. The proposed inverter

topology and control scheme are validated through the

simulation studies carried out in MATLAB/Simulink. The

simulation results show that the inverter with the reduced

switch count generates balanced and sinusoidal output

currents. Besides, the proposed system exhibits fast dynamic

response and eliminates the steady-state error in the grid

current. In addition, the grid current THD level is computed to

be 2.07% which is within the limits specified in IEEE1547

and IEC61727.

II. T-TYPE INVERTER WITH REDUCED NUMBER OF SWITCHES

A. T-type Inverter

The multi-level inverters become the first choice of the

designers for medium and high-power levels due to their

advantages over the two-level inverters such as low EMI level,

low filter requirement, higher power level with standard

switches etc. However, depending on the structure of the

multi-level inverter topology, they have some drawbacks such

as isolated power supply requirement in CHB inverters, huge

capacitor requirement in FC inverters, and voltage balancing

problem in NPC inverters. In addition to these topologies, T-

type inverter, which is a special type of NPC inverter, is

becoming more popular. Since the T-type inverters eliminate

the isolated source, huge capacitor and clamping diode

requirements, they become an alternative solution for the

complex three-level inverter topologies with their advantages

such as easy operation and less number of switches. This

topology is also more efficient than the two-level and three-

level NPC inverters at medium frequency range [18-20].

Although the number of active switches is same as NPC

inverter, the clamping diode necessity is eliminated [18].

Furthermore, it requires less isolated gate driver than the other

three-level topologies due to the common emitter switches

connected to the neutral point which are also operating at low

frequency [18, 21].

The three-level T-type inverter structure is illustrated in

Fig. 1. Each leg of the inverter consists of four active switches

and this module commercially available even if with wide-

Fig. 1. Three-phase three-level T-type inverter structure.

bandgap (WBG) semiconductor devices such as SiC or GaN

devices which are new trend. While the commercially

availability of T-type inverter leg modules make them more

compact and inexpensive, the use of WBG semiconductors

increases their efficiency.

B. T-type Inverter with Reduced Number of Switches

Multi-level inverters are commonly used in medium and

high-power applications. The main drawback of the multi-

level inverter topology is its higher number of switch count

when compared with the conventional two-level inverters.

This increases the cost, size and complexity of the inverter. In

this study, the two-leg inverter topology, which is proposed in

place of conventional three-phase two-level inverter, is

adopted to three-phase three-level T-type inverter.

Three-phase two-level two-leg inverter scheme is given

Fig. 2(a). It has only four switches, which is two-to-third ratio

to conventional ones. Although this topology has been

proposed for variable speed motor drives, the power factor

correction (PFC) rectifiers [22-24] in initial studies, nowadays,

it is suggested for many power electronics applications.

Different modulation strategies and control schemes have also

been proposed for this topology which allows more compact

designs that achieve the same purpose [5-9].

In Fig. 2(b), the three-phase three-level T-type inverter

structure with reduced switch count, which is inspired from a

three-phase two-level two-leg inverter, is depicted. Three-

phase two-leg inverter voltage equations are written as:

)(

4321 aaaadcAN

SSSSVV −−+=

(1)

)(

4321 bbbbdcBN

SSSSVV −−+=

(2)

where

nm

S

(n=1,2,3 and m=a, b) are position of switches

(1=ON and 0 = OFF). State equations can be expressed as:

(a) (b)

Fig. 2. Three-phase two-leg inverters a) two-level inverter b)three-level T-

type inverter.

Fig.3. Comparison of PI and PR controller a) PI b) PR controller.

2018 6th International Istanbul Smart Grids and Cities Congress and Fair (ICSG)

59

BNBAAN

b

b

a

a

vvvv

dt

di

L

dt

di

L++−=−

00

(3)

CBBN

c

c

b

b

vvv

dt

di

L

dt

di

L

00

+−=−

(4)

Equations (3) and (4) can be written in the state space form as

−

+

−

−

−

=

−

−

CN

BN

AN

cb

ba

C

B

A

cb

ba

b

a

v

v

v

LL

LL

v

v

v

LL

LL

dt

di

dt

di

010

011

0

0

110

011

0

0

1

0

0

0

1

(5)

As seen from Fig. 2(b), the proposed inverter can be operated

as three-phase three-level with only eight semiconductor

switches. Compared to conventional three-phase three-level T-

type inverters, the number of semiconductor switches and

drivers is reduced from twelve to eight, and six clamped

diodes in conventional NPC topology are removed.

C. Proportional-Resonant Controller

Proportional-resonant controller is a robust method which

is preferred especially in AC systems due to the large gain

factor at the resonance frequency. PR is a good solution to the

inability in tracking sinusoidal reference with traditional

control methods such as PI and PID. Because of this unique

feature, the PR controller is preferred in grid-connected

inverters, high power factor rectifiers and active filter

applications. The transfer function of the PR controller is

given as follows:

22

2

)(

)(

)(

ω

+

+== s

sK

K

sE

sY

sG

i

p

(6)

where K

p

and K

i

are the PR controls gains and ω is the

resonant frequency. The K

p

gain determines the dynamics of

the system such as bandwidth and phase margin. The

determination of the gains is similar to the PI control. The

dynamics and steady-state response can be determined by

changing the K

p

and K

i

gains. The ideal PR controller has

infinite gain in frequency ω. A higher value of gain may be a

good property, but it causes stability problems. To solve this

problem, it is suggested to add a damping to the ideal PR

controller as shown below

22222

2

2

2

)(2

)(2

)(

ωω

ω

ωωω

ωω

++

+≈

+++

+

+= ss

sK

K

ss

sK

KsG

c

ci

p

cc

cci

p (7)

here, ω

c

is the cut-off frequency which is very small compared

to ω. The approximate models of PI and PR controllers are

shown in Fig 3. As can be seen from Fig. 3, the PR is an

improved version of the PI controller that regulates AC gain.

Ideal and non-ideal PR controller amplitude and phase

responses are illustrated in Fig. 4 for K

p

=6, K

i

=220, ω

c

=0.5

rad/s and ω=2*pi*50 rad/s. It is seen that when the non-ideal

model is used, the sharp peak is significantly reduced and

instability problems can be removed.

0

50

100

150

200

10

1

10

2

10

3

10

4

-90

-45

0

45

90

Bode Diagram

Frequency (rad/s)

Phase (deg) MAgnitude (dB)

Ideal PR

Dumped PR

Fig.4. The frequency response of the ideal and damped PR controllers.

III.

P

ROPOSED

S

YSTEM

The proposed three-phase three-level T-type two-leg

inverter scheme with PR controller is shown in Fig. 5. The

proposed system consists of the DC voltage source, three-level

two-leg T-type inverter, the LCL output filter, the PR current

regulator and the phase locked loop (PLL) circuit. The DC

link voltage is divided with voltage divider capacitors and

midpoint is connected as the third phase.

The differential equations of inverter can be written as

NMCadcaaf

a

f

VVVSir

dt

di

L−−=+

11

1

1

(8)

NMCbdcbbf

b

f

VVVSir

dt

di

L−−=+

11

1

1

(9)

NMCccf

c

f

VVir

dt

di

L−−=+

11

1

1

(10)

gaCaaf

a

f

VVir

dt

di

L−=+

22

2

2

(11)

gbCbbf

b

f

VVir

dt

di

L−=+

22

2

2

(12)

gcCccf

c

f

VVir

dt

di

L−=+

22

2

2

(13)

aa

ca

f

ii

dt

dV

C

21

−=

(14)

bb

cb

f

ii

dt

dV

C

21

−=

(15)

cc

cc

f

ii

dt

dV

C

21

−=

. (16)

Equations (8)-(10) can be revised if the system is balanced

Cadcbdcaaf

a

f

VVSVSir

dt

di

L−−=+ 3

1

3

2

11

1

1

(17)

Cbdcadcbbf

b

f

VVSVSir

dt

di

L−−=+ 3

1

3

2

11

1

1

(18)

Ccdcbdcacf

c

f

VVSVSir

dt

di

L−−−=+ 3

1

3

1

11

1

1

. (19)

Then, the equations (17)-(19) can be written in the stationary

reference frame as given below:

2018 6th International Istanbul Smart Grids and Cities Congress and Fair (ICSG)

60

Fig. 5. The block diagram of the proposed grid tied inverter system.

αβαβαβ

αβ

Cnff

VVir

dt

di

L−=+

11

1

1

(20)

αβαβαβ

αβ

gCff

VVir

dt

di

L−=+

22

2

2

(21)

αβαβ

αβ

21

ii

dt

dV

C

c

f

−=

. (22)

The grid current of the three-phase three-level T-type two-leg

grid-connected inverter is controlled by PR controller. The

PR controller generates the necessary control signal by

processing the grid current error. The control signal U is

generated as in the following equation which is illustrated in

Fig. 5.

)

2

2

)(()(()(

22

*

ωω

ω

αβαβ

++

+−=

ss

sK

KsisisU

c

ci

p

(23)

The control signal U is applied to the PWM unit which

generates the gate signals for the two legs of the inverter. It is

worth noting that the PWM method used here is different

than conventional the PWM methods. In conventional PWM

generation techniques, the gate signals are generated for three

legs of the inverter, but in this study, there are two legs only.

In addition, the proposed control method has a voltage

balancing ability.

IV.

S

IMULATION

R

ESULTS

The PR controlled three-level T-type inverter with

reduced number of switches is simulated with

MATLAB/Simulink. Table I shows the used parameters in

the simulation studies. The performance of the proposed

inverter is tested in different conditions. The simulation

studies showed that the three-level T-type two-leg inverter

can perform the same function even though it has fewer

elements than the conventional inverters. The dynamic

performance of the inverter has been tested under step

changes in the reference grid current. The reference grid

current amplitude is increased from 15A to 30A at t=0.065s,

and it is reduced from 30A to 15A at t=0.125s. The inverter

currents, grid currents and grid voltages for these operation

tests are depicted in Figs. 6 and 7, respectively. It is seen

from the Fig. 6 and Fig. 7 that the proposed three-phase three

level T-type inverter generates and injects balanced and

TABLE I. P

ARAMETERS

O

F

T

HE

S

YSTEM

S

y

mbol Value

DC link voltage,

V

in

800V

Output L filter,

L

f1

,

L

f2

1.4 mH, 0.5 mH

Resistive effect of inductance,

r

f1

,

r

f2

0.09 Ω , 0.04 Ω

Output C filter,

C

f

40 µF

Switching frequenc

y

,

f

sw

10 kHz

Rated Powe

r

,

P

15 k

W

Proportional gain (

K

p

), Integral Gain

(

K

i

)

6, 220

Resonant freq. (

ω

), Cut-off freq. (

ω

c

)

ω

=314, 0.5 rad/s

0.02 0.03 0.04 0.05 0. 06 0.07 0.08 0.09 0.1

-30

-15

0

15

30

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-30

-15

0

15

30

0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-300

-150

0

150

300

I

1abc

(A)

I

2abc

(A)

V

g_abc

(V)

t (s)

t (s)

t (s)

Fig.6. The step increase in inverter current reference.

0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16

-30

-15

0

15

30

0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16

-300

-150

0

150

300

I

2abc

(A)

V

g_abc

(V)

t (s)

t (s)

t (s)

0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16

-30

-15

0

15

30

I

1abc

(A)

Fig.7. Sudden decrease in inverter load.

sinusoidal output currents to the grid. The proposed PR

controller provides fast transient response and eliminates the

steady-state error in the grid current. The grid currents are

also in phase with the grid voltages and unity power factor

operation is obtained. In order to evaluate the scientific and

standards compliance of the results, the THD value is

analyzed which is one of the most important criteria for the

grid-connected inverters. Fig. 8 shows the harmonic spectrum

of the grid current for this simulation study. According to the

simulation results, the current THD level is computed as

2.07%.

2018 6th International Istanbul Smart Grids and Cities Congress and Fair (ICSG)

61

0 0.02 0 .04 0.06 0.0 8 0.1 0. 12

Time (s)

-20

0

20

Sig nal ma g.

Selected signal: 6.688 cycles. FFT window (in red): 2 cycles

0 50 100 150 200

Harmonic order

0

0.05

0.1

0.15

0.2

0.25

0.3

Mag (% of Fundamental)

Fundamental (50Hz) = 14.93 , THD= 2.07%

Fig.8. Inverter output current waveform analysis.

V.

C

ONCLUSIONS

In this study, three-phase three-level T-type grid-

connected inverter topology is proposed. The proposed

topology, unlike conventional three-level inverters, has

reduced the number of semiconductor switches. Thus, the

cost and size of the inverter, which are related to the

component count, are reduced while maintaining the three-

level inverter’s superior advantages. Another advantage of

the proposed topology is the control technique. In this study,

a PR controller is proposed, which is an effective and robust

control system for tracking AC signals, and provides fast

response and eliminates the steady-state error in the grid

current. The proposed system is validated through the

MATLAB/Simulink simulation studies. It is seen from the

simulation results that the proposed inverter generates three-

phase balanced and sinusoidal grid currents. The THD of grid

current meets the limits specified in the international

standards such as IEC61727 and IEEE1547.

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