Impact of NBTI on the temporal performance degradation of digital circuits

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
IEEE Electron Device Letters (Impact Factor: 2.75). 09/2005; 26(8):560 - 562. DOI: 10.1109/LED.2005.852523
Source: IEEE Xplore


Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

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    • "Both models can support different input stress types depending on the solving method: only for DC, AC stress (duty factor dependent) or any kind of input stress including the non-periodic workload. Paul et al. in [24] pioneered the work by performing NBTI analysis through the R-D model in case of the DC voltage stress that resulted in the pessimistic outbound of the BTI degradation. Wang et al. [11] and Kumar et al. [30] applied the signal probability and the activity factor concept to the R-D model, where a non-periodic input stream is converted to its equivalent periodic stream. "
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    ABSTRACT: In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.
    Full-text · Article · Mar 2014 · IEEE Transactions on Device and Materials Reliability
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    • "While the longterm model abstracts circuit operation patterns into aging calculations, the aging-aware library serves as the key bridge between device-level reliability effects and large-scale digital circuit analysis. Previous works use complicated methodologies to predict delay shift due to NBTI [46]–[50]. To reduce the computation cost in such a process, a simple gate delay model is proposed in this section. "
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    Full-text · Article · Jan 2014 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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    • "Furthermore, recently reported 3D physical simulations indicate that even alternative device architectures with superior electrostatic integrity such as thin-body SOI and double-gate MOSFETs are not spared from the profound effects of BTI-related variability [18]. A number of previous works have proposed simulation approaches to predict circuit performance under BTI degradation1920212223. Even though these have addressed some of the main concerns of the impact of BTI degradation on circuits, they are generally based on the assumption of a nominal V T degradation when transistors of an identical design are subjected to a similar stress level; or they require a priori knowledge or assumption of the V T variation caused by sources of statistical variability. "
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    ABSTRACT: In the contemporary and future MOSFETs, NBTI/PBTI-related charge trapping in the presence of underlying statistical variability gives rise to statistical degradation of the coresponding electrical characteristics and figures of merit. We present a framework that integrates the statistical aspect of the NBTI/PBTI degradation, obtained from large-scale 3D ‘atomistic’ device simulations, into statistical compact models. Through a selection of physically relevant compact model parameters, the resulting library of compact models provides high accuracy in representing the statistical NBTI/PBTI degradation effects, across a wide range of degradation conditions. This approach enables circuit designers to verify to what extent particular design solutions will meet the design specifications subject to progressive BTI degradation in the presence of statistical variability.
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