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Wafer Backside Cleaning for Defect Reduction and Litho Hot Spots Mitigation DI: Defect Inspection and Reduction
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Ever since its inception in the late 1980s, chemical-mechanical planarization (CMP) has been the pivotal enabling process in the manufacturing of integrated circuits (IC). Whether it is for front-end-of-the-line (FEOL) applications such as shallow trench isolation (STI) and metal gate, or back-end-of-the-line (BEOL) such as Cu interconnects or through-silicon via (TSV), CMP is the terminal step that completes a process module. As a consequence, the defects observed after CMP have direct impacts on the yield and reliability of the devices and circuits.
Provided the nature of CMP process described above and its heavy usage of consumables, CMP-related defects are complicated in nature. Not only does CMP generate defects from its own process and consumables involved, but it also reveals the defects not detected and removed from all the up-stream process steps. In addition, the tolerance and specification for post CMP defect density will only become more stringent as the device dimension continues to decrease with shrinking design ground rule. For example, in the 7 nm technology node, the width of Cu interconnects in the thin wire levels is only around 24 nm, which is smaller than the diameter of abrasive nano particles in most CMP slurries. The presence of any post-CMP defects of equal or greater size on the Cu surface poses serious concern for yield loss. As a consequence, the characterization, mitigation, and reduction of CMP-related defects are among the most important yet challenging tasks in IC manufacturing.
In this chapter, CMP defects will be categorized by their formation mechanism. The roles of consumables and processes in the generation of CMP defects will be discussed. The characterization of defects and the strategies to mitigate and reduce these defects will be elaborated. The chapter will be organized according to the following index:
Wafer manufacturing processes are also employed to produce photovoltaic wafers from single or polycrystalline silicon. The generalized process flow of wafer manufacturing includes the following classification of four categories: crystal growth, wafer forming, wafer polishing, and wafer preparing. In this chapter, each of the four categories is discussed. With the trend of wafers with larger diameter, the Czochralski method is the most suitable technique for crystal growth. The wafer manufacturing process following crystal growth is the wafer forming process which includes cropping, trimming, orientation identification, slicing and edge rounding. Once an ingot is sliced into wafers of the same thickness, the next group of wafer manufacturing processes serves the purpose of polishing the surface of sliced wafers. The chapter presents industrial practice of wafer manufacturing with illustrations of wafer manufacturing equipment and processes.
The presence of a particle on the backside of a wafer is commonly acknowledged to produce a deflection of the wafer when it is held on a flat surface by means of a pressure difference. We simulated this wafer topography, taking into account both elastic and plastic deformations. The simulations are backed up by experimental evidence. The results show that height variations of 100 nm can extend over several mm. At the same time, indentation and plastic deformation reduce the surface height variations to values that are orders of magnitude below those predicted in the ITRS roadmap.
of preventive backside cleaning steps. These cleaning steps can be introduced after processes that generated high backside defect counts or right before a lithographic wafer exposure. In this study that was performed at imec’s 300mm cleanroom facility, the study objective was to evaluate the focus spot reduction performance of a stand-alone scrubber in a case study featuring known focus spot generating equipment sets. . In the first part of the study, monitoring of various production tools in terms of backside cross-contamination was done. A set of equipment’s that generated high backside defect counts was selected for generating adequate backside contaminated test material for the cleaning evaluation. This backside contaminated test material was used in our cleaning experiments and evaluation of focus spot reduction by performing leveling tests on an immersion scanner that was able to measure out of plane deviations.
Defects on the backside of a wafer during processing can come from many sources. Particles and scratches on the backsides of wafers can be caused by wafer handling equipment such as robots and chucks, as well as by CMP processes. In addition, cross-contamination of wafers and handling equipment can occur when wafers move from tool to tool, through the production line. When wafers are exposed, backside defects can cause localized areas of poor lithography pattern resolution on the frontsides of wafers, resulting in increased rework rates, decreased throughput, and yield loss. As minimum feature sizes continue to shrink with each new technology node, devices become denser and exposure tool depth of focus decreases - making the elimination of lithography hot spots an even more critical issue. At a major worldwide IDM, automated macro defect inspection tools for integrated front, edge, and backside inspection have been implemented to inspect wafers at several After Develop Inspection (ADI) and post-etch inspection steps. These tools have been used to detect foreign material and scratches on the backsides of several lots that were caused by another process tool, causing photolithography hot spots. This paper describes advanced macro inspection of wafer front and back surfaces and how the inspection data was used to correlate backside defects to photolithography hot spots, and take corrective action.
Correlation of wafer backside defects to photolithography hot spots using advanced macro Inspection
- A Carlson
- T Le
A. Carlson and T. Le, "Correlation of wafer backside
defects to photolithography hot spots using advanced macro
Inspection", SPIE 31 st International Symposium on Advanced
Lithography, pp. 61523 E-61523 E (2006).
Effects of Back Surface Polishing of Silicon Wafer on Lithography Process
- Takahashi
Takahashi, "Effects of Back Surface Polishing of Silicon
Wafer on Lithography Process", CAMP 21 st CMP symp.,Aug.
14~16, Lake Placid, NY (2017).
Effects of Back Surface Polishing of Silicon Wafer on Lithography Process
- Y Matsui
- T Kawasaki
- N Mizuno
- Y Fujiyama
- T Takahashi