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Fallstudien sicherheitsgerichteter programmierbarer elektronischer Systeme
Abstract
Drei speziell für sicherheitsgerichtete Anwendungen konzipierte programmierbare elektronische Systeme werden vorgestellt. Das erste wird höchsten Sicherheitsansprüchen gerecht, indem seine Software die Form leicht verifizierbarer Ursache-/Wir- kungstabellen hat, die unmittelbar von der Hardware ausgeführt werden. Das zweite ist auf inhärente Unterstützung der Verifikation von Funktionsplänen mittels diversitärer Rückwärtsanalyse hin ausgelegt. Eine asymmetrische Mehrprozessorarchitektur vermeidet durch Betriebssysteme erzeugte Nichtdeterminismen mittels Migration der Funktionen des Betriebssystemkerns auf einen Koprozessor und fördert die Vorhersehbarkeit des Ausführungsverhaltens. Weiterhin wird Prozeßperipherie für zeitgenau bestimmbaren Datenaustausch beschrieben.
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The rules of deduction which are usually used for many-sorted equational logic in computer science, for example in the study of abstract data types, are not sound. Correcting these rules by introducing explicit quantifiers yields a system which, although ...
Most accidents are caused by human error. Computer control systems in aircraft, chemical plant, nuclear reactors and so on could in principle prevent many accidents, but in practice they are not reliable enough to be put in charge of human lives. This Report describes some of the developments in computer hardware and software which are needed before this situation can change, and introduces the VIPER microprocessor which has been designed specifically for ultra-reliable systems. In conjunction with a number of other RSRE Publications (see references) it defines the VIPER architecture formally and describes some of its supporting software.
In summary, predictability in real-time systems has been defined in many ways. For static real-time systems we can predict the overall system performance over large time frames (even over the life of the system) as well as predict the performance of individual tasks. If the prediction is that 100% of all tasks over the entire life of the system will meet their deadlines, then the system is predictable without resorting to any stochastic evaluation. In dynamic real-time systems we must resort to a stochastic evaluation for part of the performance evaluation. Predictability for these systems should mean that we are able to satisfy the timing requirements of critical tasks with 100% guarantee over the life of the system, be able to assess overall system performance over various time frames (a stochastic evaluation), and be able to assess individual task and task group performance at different times and as a function of the current system state. If all these assessments meet the timing requirements, then the system is predictable with respect to its timing requirements.
Everyone knows what time is, or at least how the word “time” is used in everyday language. Time is so much a part of our everyday
experience that it has become a self-evident aspect of the world in which we live. One might expect that this familiarity
with time would enhance the ability to relate it to the behavior of computing systems. In particular, the timing of input-output
relations should pose no special problems. But a quick glance at the state of affairs in computer science tells us that, in
sharp contrast to the alleged exactness of the discipline, there is little concern for descriptions of systems or programs
that are exact with respect to time. Most of the attention devoted to time is directed toward speeding up the rate of data
processing or developing time-efficient algorithms.
There is evidence that, among all design domains of hard real time systems, architectural issues gained the lowest research interest. Universal architectures, which are generally applied as hardware bases for hard real time applications, are seldom behaving in a fully predictable way. In the paper, several commonly used techniques which prevent temporal determinism of instruction execution are enumerated. An asymmetrical multiprocessor architecture for hard real time applications is presented, whose temporal behaviour is fully predictable. Some adequate features are discussed which are incorporated into the processor's implementation.
A real-time language, called Real-Time Euclid, has been specifically designed with a set of schedulability analysis provisions built in. The authors introduce a set of schedulability analysis techniques that are applied to Real-Time Euclid programs and, utilizing knowledge of implementation-dependent information, provide good worst-case time bounds and other schedulability information. To demonstrate the effectiveness of these techniques, a prototype schedulability analyzer has been developed, to be used on a realistic real-time system. A description is given of the design of the prototype, and preliminary evaluation results.
Consider the problem of scheduling a set of preemptible tasks in one or more processor systems. The task system consists of
a set of independent tasks or a task set with precedence relations. Each task is characterized by execution time and deadline.
This article presents scheduling algorithms that guarantee all time constraints. These algorithms are so easy to implement
that they can be used in real-time operating systems. An overview is given for the different feasible scheduling algorithms
of some task and processor systems.
High-Integrity Pearl, (HI-Pearl) an extension to the Process and Experiment Automation Real-Time language (Pearl) which incorporates several principles from the real-time Euclid language, is described. The requirements of real-time software and components of a real-time language are reviewed. HI-Pearl's mechanisms for concurrency control, synchronization, allocation, time-bounded loops, surveillance of events, parallelism, timing constraints, overload detection and handling, storage management, run tracing, and error detection and handling are discussed. HI-Pearl's schedulability analyzer, an automated tool to predict whether real-time software will adhere to its critical timing constraints, is also discussed
The task of safeguarding systems is to bring processes from dangerous into safe states. A special class of safeguarding systems are emergency shutdown systems (ESD), which, until now, are only implemented in inherently fail safe hardwired forms. Despite their high reliability, there is an urgent industrial need to replace them by more flexible systems. Therefore, in an earlier work, a dedicated programmable logic controller (PLC) was designed, which directly supports functional logic diagrams (FLD), the traditional and user oriented graphical programming paradigm of ESDs, in its architecture. In this paper we give a formal correctness proof of the functional building blocks occurring in FLDs specifying ESDs. For this task Isabelle/HOL is used as a mechanical proof assistant. In a final step, safety licensing of ESD software can easily be carried through by back translation. 1 Introduction Many technical systems have the potential of disastrous effects on the environment, equipment, or...
Ein Verfahren zur Software-Verifikation
- H Krebs
- U Haspel
Constructing Predictable Real Time Systems
- W A Halang
- A D Stoyenko
- Wolfgang A. Halang
Predictability of temporal behaviour of hard real-time systems
- M Colnarič
Funktionelle Beschreibung von Prozeßrechner-Betriebssystemen. VDI-Richtlinie VDI/VDE 3554
- R Baumann