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A Double Stage Implementation for 1-K Pseudo RNG using LFSR and TRIVIUM
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Random number generator (RNG) is largely used to supply the initial computation stage for many digital systems, noise generation in DSP, and cryptographic applications. As for cryptographic applications, RNGs should be efficiently implemented to ensure maximum unpredictability with minimum Area-Time trade off. In this paper, we are implementing fast two stages pseudo random number generator (PRNG) to maintain enhanced randomization and performance. At the first stage, we have used the linear feedback shift register (LFSR) method feed the initialization vector for the Trivium generator (the second stage). For verification and benchmarking purposes, we have synthesized our implementation using Cyclone IV E FPGA chip family with target device EP4CE115 F29C7 in terms of cost factors area and delay. Thus, the proposed implementation has recorded a fixed maximum frequency of 214.9 MHz (i.e. clock cycle duration is 7.74ns) and fixed design area of 657 LEs with variable delay values ranges from 18.10 Micro sec to 25.78 Micro sec for different datapath ranges from 16-to 1024 bit respectively. Thus, the results conformed a linear relationship between area and bit length. Consequently, the obtained results are attractive for many embedded system applications such as cryptographic algorithm design. These results imply that the design area is scalable and can be easily increased or embedded with many other design applications.
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... In general, RNGs can be classified into two types, namely, pseudo-random number generators (PRNGs) and true random number generators (TRNGs) [6][7][8]. However, because of the merits of TRNGs in terms of unpredictability, they have been preferred over PRNG in many more cases including, but not restricted to, cryptographic key generation, nonce generation, one-time pads, random simulations, gaming, test pattern generators and device authentication [9,10]. ...
True random key generator (TRNG) architectures play a notable role in strengthening information security infrastructure. The development of new entropy sources based on reconfigurable hardware is always in demand, especially for the integrity of devices in IoT applications. TRNGs can be adopted for generating unique device IDs that form the data network in the IoT. A ring oscillator (RO) is an efficient entropy source which can be implemented on FPGAs or realised as ASIC hardware. This work proposes a non-identical RO array as an entropy source. The TRNG architecture, based on an increasing odd number of inverters per ring, was extensively studied. The various statistical and hardware analyses provided encouraging results for this reliable entropy unit. The suggested device-independent non-identical RO structure was implemented on five different types of FPGA hardware belonging to the Xilinx and Intel families, consuming 13 registers and nearly 15 combinational functions. This TRNG achieved a throughput of 3.5 Mbps. While the emergence of the Gaussian response evaluated true randomness, the NIST 800-90B and NIST 800-22 tests yielded good results in terms of the justification of randomness evolving from the proposed TRNG architecture.
... Nevertheless, the non-linear feedback shift register (NLFSR) is more resistant to several types of attacks. Trivium [20] is considered an NLFSR and is used in the proposed model to provide more resistance to such attacks. ...
Privacy-preserving of medical information (such as medical records and images) is an essential right for patients to ensure security against undesired access parties. This right is typically protected by law through firm regulations set by healthcare authorities. However, sensitive-private data usually requires the application of further security and privacy mechanisms such as encipherment (encryption) techniques. ’Medical images’ is one such example of highly demanding security and privacy standards. This is due to the quality and nature of the information carried among these images, which are usually sensitive-private information with few features and tonal variety. Hence, several state-of-the-art encryption mechanisms for medical images have been proposed and developed; however, only a few were efficient and promising. This paper presents a hybrid crypto-algorithm, MID-Crypt, to secure the medical image communicated between medical laboratories and doctors’ accounts. MID-Crypt is designed to efficiently hide medical image features and provide high-security standards. Specifically, MID-Crypt uses a mix of Elliptic-curve Diffie–Hellman (ECDH) for image masking and Advanced Encryption Standard (AES) with updatable keys for image encryption. Besides, a key management module is used to organize the public and private keys, the patient’s digital signature provides authenticity, and integrity is guaranteed by using the Merkle tree. Also, we evaluated our proposed algorithm in terms of several performance indicators including, peak signal-to-noise ratio (PSNR) analysis, correlation analysis, entropy analysis, histogram analysis, and timing analysis. Consequently, our empirical results revealed the superiority of MID-Crypt scoring the best performance values for PSNR, correlation, entropy, and encryption overhead. Finally, we compared the security measures for the MID-Crypt algorithm with other studies, the comparison revealed the distinguishable security against several common attacks such as side-channel attacks (SCA), differential attacks, man-in-the-middle attacks (MITM), and algebraic attacks.
... Some of the Primality testers are used to prove a number is prime where some are used to prove a compositeness. Thus, the prime number generation module consists of two stages of computations: generating the random number [14,15] and then test its primality. In order to generate a prime number, the random number generating stage should be followed by primality testing [8] phase to check whether the generated number is prime or not. ...
Due to the demand for large prime numbers to be used by many public key cryptographic systems such as RSA and SSC (Schmidt-Samoa cryptosystem), this led for the development of fast and reliable methods for primality testing to determine whether a given integer is prime or composite. Many algorithms were proposed by to address the efficient method of testing the primality of the integer number. In this paper, we propose a pipelined reconfigurable FPGA implementation for the primality testing coprocessor using Millar-Rabin method by employing the maximum possible parallelism of the internal operations. The proposed design targeted the ( along with simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed parallel architecture implementation has recorded: critical path delay of , maximum operational frequency of , hardware design area (number of logic elements) of , and total thermal power dissipation estimated as 151.30 mW. Consequently, the proposed PT architecture can be efficiently employed by many public key cryptographic mechanisms.
On-device intelligence and AI-powered edge devices require compressed deep learning algorithm and energy efficient hardware. Compute-in-memory (CIM) architecture is a more suitable candidate than traditional Complementary Metal-Oxide-Semiconductor (CMOS) technology for deep learning applications since computations are performed directly within the memory itself, reducing the need for data movement between memory and processing units. However, the current deep learning compression techniques are not designed to take advantage of CIM architecture. In this work, we proposed Twofold Sparsity, a joint bit- and network-level sparsity method to highly sparsify the deep leaning models by taking advantage of CIM architecture for energy-efficient computations. Twofold Sparsity method sparsify the network during training by adding two regularizations, one to sparsify the weights using Linear Feedback Shift Register (LFSR) mask, and the other one to sparsify the values in the bit-level by making bits zero. During inference, the same LFSRs is used to choose the correct sparsed weights for multiplication between input and weights and 2bit/cell RRAM based CIM is responsible to do the computation. Twofold Sparsity method achieved 1.3x to 4.35x energy efficiency in different sparsity rates compared to baselines and eventually enabling powerful deep learning models to be run on power constrained edge devices.
Random numbers are needed in many areas: cryptography, Monte Carlo computation and simulation, industrial testing and labeling, hazard games, gambling, etc. Our assumption has been that random numbers cannot be computed; because digital computers operate deterministically, they cannot produce random numbers. Instead, random numbers are best obtained using physical (true) random number generators (TRNG), which operate by measuring a well-controlled and specially prepared physical process. Randomness of a TRNG can be precisely, scientifically characterized and measured. Especially valuable are the information-theoretic provable random number generators (RNGs), which, at the state of the art, seem to be possible only by exploiting randomness inherent to certain quantum systems. On the other hand, current industry standards dictate the use of RNGs based on free-running oscillators (FRO) whose randomness is derived from electronic noise present in logic circuits and which cannot be strictly proven as uniformly random, but offer easier technological realization. The FRO approach is currently used in 3rd- and 4th-generation FPGA and ASIC hardware, unsuitable for realization of quantum RNGs. In this chapter we compare weak and strong aspects of the two approaches. Finally, we discuss several examples where use of a true RNG is critical and show how it can significantly improve security of cryptographic systems, and discuss industrial and research challenges that prevent widespread use of TRNGs.
In this paper, we are implementing fast pseudo random number generator (PRNG) based on linear feedback shift register (LFSR) method with variable datapath sizes (8 bit –to- 1024 bit). The design was synthesized using Xilinx Virtex 7 chip family with target device XC7VH290T-2-HCG1155 in terms of maximum frequency and area of the FPGA design. As a result, a fixed maximum frequency of 1436.678MHz for different datapaths has been achieved. Thus, the results conformed a linear relationship between area and bit length. Consequently, the obtained results are attractive for many embedded system applications such as cryptographic algorithm design.
This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.
This chapter introduces a group of combinational logic building blocks that are commonly used in digital design. As we move into systems that are larger than individual gates, there are naming conventions that are used to describe the size of the logic. Table 6.1 gives these naming conventions. In this chapter we look at medium-scale integrated circuit (MSI) logic. Each of these building blocks can be implemented using the combinational logic design steps covered in Chaps. 4 and 5. The goal of this chapter is to provide an understanding of the basic principles of MSI logic.
eSTREAM called for new stream ciphers designed for niche areas such as exceptional performance in software and hardware where resources are restricted. This project provides an open platform to discuss these ciphers. Trivium is one of the promis- ing new ciphers submitted to it. Until now, no attack has been successfully applied to it. This paper illustrates new design principles of stream ciphers based on the structure of Trivium and introduces the definition of k-order primitive polynomials. New designs of Trivium are also given according to the principles in this paper.
A new algorithm called Mersenne Twister (MT) is proposed for generating uniform pseudorandom numbers. For a particular choice of parameters, the algorithm provides a super astronomical period of 219937 - 1 and 623-dimensional equidistribution up to 32-bit accuracy, while using a working area of only 624 words. This is a new variant of the previously proposed generators, TGFSR, modified so as to admit a Mersenne-prime period. The characteristic polynomial has many terms. The distribution up to ν bits accuracy for 1 ≪ ν ≪ 32 is also shown to be good. An algorithm is also given that checks the primitivity of the characteristic polynomial of MT with computational complexity O(p2) where p is the degree of the polynomial. We implemented this generator in portable C-code. It passed several stringent statistical tests, including diehard. Its speed is comparable to other modern generators. Its merits are due to the efficient algorithms that are unique to polynomial calculations over the two-element field.
Efficient FPGA Implementation of RSA Coprocessor Using Scalable Modules
- Q Al-Haija
- M Smadi
- M Jaffri
- A Shua'ibi
Q. Abu Al-Haija, M. Smadi, M. Jaffri and A. Shua'ibi,
"Efficient FPGA Implementation of RSA Coprocessor
Using Scalable Modules", Procedia Computer Science,
Elsevier, Canada, 2014.
[4].
Cryptographically secure pseudo-random number generator
- G G Rose
- A Gantman
- L Xiao
G.G. Rose, A. Gantman, and L. Xiao,
"Cryptographically secure pseudo-random number
generator", US Patent 8019802, Google Patents, 2011.
Marouf is a senior student of Electrical Engineering Department at King Faisal University. He is a Syrian resident born on Aug -15-1995 and excellent in both languages Arabic and English. His research interests include (but not limited to): Public Key Cryptography, FPGA Design, Digital Arithmetic
- A Ibrahim
Ibrahim A. Marouf is a senior student of Electrical Engineering Department at King Faisal University. He is a Syrian resident
born on Aug -15-1995 and excellent in both languages Arabic and English. His research interests include (but not limited to):
Public Key Cryptography, FPGA Design, Digital Arithmetic, Microcontroller Design, Electronic Design.