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Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.
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PersPective
https://doi.org/10.1038/s41565-018-0082-6
1Dipartimento di Ingegneria dell’Informazione, Università di Pisa, Pisa, Italy. 2Istituto Italiano di tecnologia, Graphene Labs, Genova, Italy. 3Materials Science
and Engineering, University of Texas at Dallas, Richardson, TX, USA. *e-mail: g.iannaccone@unipi.it; francesco.bonaccorso@iit.it
Recently, the so-called materials-on-demand paradigm has been
proposed1 thanks to the possibility of forming a three-dimen-
sional (3D) material with tailored characteristics by combin-
ing layers of two-dimensional (2D) materials, such as graphene2,
and other single/few-atomic-layer semiconductors, insulators and
metals3,4. In many ways, this paradigm is a modern and challenging
evolution of what in the 1980s was called ‘bandgap engineering5
or ‘band-structure engineering’6, that is, the artificial modifica-
tion of band-edge profiles using heterostructures made possible
by epitaxial growth of III–V, II–VI and IV–IV (ref. 7) materials
systems. Pioneering the use of heterostructures of nearly lattice-
matched semiconductor layers of few nanometres, researchers at
US and Japanese research laboratories proposed and demonstrated
new device concepts, such as hot-electron transistors8 or resonant
tunnelling transistors9,10, as well as optimized devices, such as
graded-base bipolar transistors11. This capability transformed opto-
electronics and electronics, as testified by the realization of the fast-
est transistor commonly used in telecommunications, that is, the
heterojunction bipolar transistor.
The semiconductor industry has made intense use of new mate-
rials and device engineering techniques to sustain Moore’s law.
This has been especially true in the past 15 years, when strained
silicon (using SiGe in the source and drain) was introduced at the
so-called 90 nm node, high-k gate dielectrics and metal gates at the
45 nm node, and the tri-gate geometries at the 22 nm node12. As
devices are scaled down to nanometre feature sizes, the boundary
between materials and devices as separate physical abstractions
becomes blurred.
Lateral and vertical heterostructures of 2D materials can repre-
sent an enabling device engineering technology beyond what can
be accomplished by either Si and SiGe or III–V materials systems
(cubic systems). Indeed, the ability to fabricate lateral 2D hetero-
structures with graphene and hexagonal boron nitride (h-BN)1316,
or with different phases (metallic and semiconducting) of transi-
tion metal dichalcogenides (TMDs)17,18 provides additional degrees
of freedom for device engineering at the atomistic scale, with ver-
tical and/or planar heterostructures. These developments have
the potential to revolutionize electronics and optoelectronics via
quantum engineering of electron devices. Several recent reports19,20
suggested that twisted layers of 2D materials can modify the trans-
port properties of the stacked layers significantly1921.
There is a difference in scope between quantum engineering and
band-structure engineering: while the latter mainly enables a mod-
ulation of the band-edge profiles and of bandgaps by controlling
alloy composition during materials growth, quantum engineering
involves heterostructures with layers that often have no atomic spe-
cies in common (for example, MoS2–WSe2), or have incommensu-
rate lattice structures and completely different band structure. In
addition, combinations of lateral and vertical heterostructures can
be devised, largely expanding the range of possibilities in the direc-
tion of atom-by-atom transistor design.
Pioneering research has already demonstrated proof-of-prin-
ciple transistors with vertical graphene-based2226 or TMD het-
erostructures27,28, transistors with lateral heterostructures2932 and
non-volatile memory cells33,34, as well as optoelectronic devices such
as photodiodes based on 2D vertical heterostructures35,36, and high-
quantum-efficiency photovoltaic cells based on TMDs/graphene
stacks37. The number of 2D materials already used to form the so-
called van der Waals heterostructures is of the order of a few tens3.
This number will surely increase as the number of 2D materials and
more conventional heterostructures or metal/semiconductor con-
tacts are identified and fundamental properties studied.
In this Perspective, we discuss the challenges, the opportunities
and the potential of quantum engineered transistors by exploiting
the fundamental properties of 2D materials and their heterostruc-
tures. We focus on field-effect transistors (FETs), because they can
be used with current digital logic architectures and already exhibit
promising operation at room temperature. Devices based on other
operation mechanisms38,39 are beyond the scope of the present paper.
We consider the fundamental issues related to device/material
fabrication from an industrial point of view, and the attainable
device performance, using as a benchmark the expected evolution
of complementary metal-oxide–semiconductor (CMOS) technol-
ogy, outlined by semiconductor industry roadmaps40,41. We also
critically discuss transistor structures that—even under extremely
optimistic fabrication conditions—cannot be competitive with the
Quantum engineering of transistors based on 2D
materials heterostructures
Giuseppe Iannaccone1*, Francesco Bonaccorso2*, Luigi Colombo3 and Gianluca Fiori1
Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that uni-
fies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral
heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nano-
technology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors?
In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of
two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential per-
formance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a
performance point of view, even if heterostructure formation and control are in the initial technology development stage.
Corrected: Publisher Correction
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NATURE NANOTECHNOLOGY | VOL 13 | MARCH 2018 | 183–191 | www.nature.com/naturenanotechnology 183
PersPective NaTure NaNoTechNology
foreseeable evolution of CMOS technology, that is, the continued
scaling down of FinFETs below the present-day 14 nm technology
node and further scaled gate-all-around (GAA) FETs.
Vertical stacking or lateral growth of different 2D materials is a
new and complex challenge. While stacking of 2D materials for ver-
tical heterostructures presents the issue of registration or orienta-
tion control of one layer to the other, lateral growth requires ‘lateral
lattice matching, which is still at the embryonic stage of develop-
ment. These challenges also present opportunities that both mate-
rial scientists and device engineers must address to optimize device
design and performance.
Fabrication of vertical and lateral heterostructures
The direct growth of III–V, II–VI and IV–IV heterostructures
has been used in volume manufacturing45 for a few decades.
Heterostructures of these materials have been grown predomi-
nantly by molecular beam epitaxy (MBE)46, and by metal–organic
chemical vapour deposition (MOCVD) and, given that the indi-
vidual layers have a thickness of at least several nanometres, their
growth at reduced temperatures, to minimize inter-diffusion, is
now pervasive.
The fabrication of 2D materials-based heterostructures presents
a new set of opportunities and challenges. A key aspect of 2D mate-
rials is the fact that under ideal conditions they are expected to have
low interfacial defects unlike 3D materials, and, because of the weak
interlayer van der Waals bonding, they are also expected to have
lower inter-diffusion compared to their 3D counterparts. Moreover,
2D materials-based vertical heterostructures are less sensitive to
lattice mismatch, thus enabling high-quality abrupt interfaces
with low trap densities. Additionally, perhaps a minor point, less
material will be needed for device fabrication with respect to 3D
cubic materials.
Significant progress has been made in the growth of graphene
on metals and on SiC (ref. 47). Progress has also been reported on
the growth of h-BN (refs 48,49) and TMD5052 materials, but growth
of large-area monolayer or controlled few-layer single crystals is
still elusive and will require significant time and resources. As with
any new material, there are many challenges in the deposition of
2D materials to form heterostructures, depending on the specific
2D material. For example, in the case of graphene and h-BN, it is
important to use a catalyst to grow the film4850,54 and the challenge is
to transfer the film onto the desired substrate or to grow it in situ. In
the case of the TMD materials family, the challenge is in the nucle-
ation and growth of single crystals on dissimilar surfaces (dielectric
oxides, TMDs or h-BN).
Lateral growth of 2D materials also presents a number of oppor-
tunities. In this case, the structures must be fabricated by creating
materials sequentially by selective lateral growth processes. The
development of this technology may also enable bottom-up tech-
niques53. Two-dimensional growth has already been clearly demon-
strated for graphene on Cu (ref. 54). Deterministic nucleation and
growth of graphene on Cu has also been proven to yield hexagonal
graphene single crystals55. In principle, this process can be extended
to the growth of lateral structures that follow predetermined lay-
outs. The process of course will require careful edge functionaliza-
tion depending on the lateral heterostructure composition profile.
The growth anisotropy is a critical advantage of 2D materials in
comparison to 3D materials that has already been demonstrated in
both graphene54,56 and, more recently, in TMDs57.
The most important challenge, for devices based on both lateral
and vertical heterostructures, is the preparation of the basic mate-
rials followed by their integration in the desired device structure.
While vertical heterostructures, in principle, can be formed by
direct growth (Fig. 1a) or by a transfer process for planar geometries
(Fig. 1b), lateral heterostructures must be grown in place by some
chemical means. At present, three methods are used or are under
evaluation for the fabrication of 2D materials-based heterostruc-
tures58: (1) layer-by-layer stacking via mechanical transfer of CVD-
grown films and exfoliated natural or synthetic bulk-grown 2D
materials; (2) direct growth by CVD, MBE or atomic layer epitaxy
(ALE); and (3) layer-by-layer deposition of solution-processed 2D
crystals. However, at this time, all of the aforementioned approaches
have limitations.
Layer-by-layer stacking or deterministic placement of 2D mate-
rials via mechanical transfer is the only technique that has been
successfully used to create heterostructures and heterostructure
devices. The method has relied principally on the mechanical exfo-
liation of bulk layered materials into atomically thin sheets59, but
more recently the direct transfer of CVD-grown films (Fig. 1b) has
also been used. The method has been extensively used for graphene,
bilayer graphene, h-BN and TMDs to fabricate various stacked
devices60. While transfer techniques of synthetic films or exfoli-
ated layers from natural or synthetic bulk crystals have enabled the
demonstration of many proof-of-principle stacked devices, allow-
ing fundamental understanding of physical phenomena in these
structures, manufacturing processes of heterostructures on a large
scale have not been developed yet. It should be noted that mechani-
cal exfoliation from either natural or synthetic bulk crystals is not
believed to be a manufacturable process at present, given the small
size of the available crystals. So far, CVD or MBE techniques have
been favoured for the growth of thin films of the various 2D materi-
als47; these growth techniques will certainly be optimized for sin-
gle-layer films of graphene, h-BN and TMDs, as has been done for
traditional materials used by the semiconductor industry.
The selection of the growth technique will depend mainly on
device design and integration scheme and, secondarily, on tech-
niques that yield the highest quality material. The availability of
high-quality synthetic 2D films will enable the development of
equipment for transfer with and without rotational alignment of 2D
materials for the fabrication of any type of planar on-demand verti-
cal heterostructure. As new equipment is developed for transfer and
placement of the 2D films, many opportunities will emerge for the
integration of these material structures in semiconductor manufac-
turing flows. The ideal or preferred case would be to use MBE, CVD
and ALE processes to create/grow in situ new heterostructures.
However, it is envisioned that the growth of on-demand aligned
heterostructures (Fig. 1a) using these techniques could be extremely
difficult, particularly in the case of twisted layers (Fig. 1c).
In the case of aligned heterostructures, nucleation and growth
processes will have to be developed. The growth of these hetero-
structures on a large scale could be facilitated by the development
of selective ALE growth, thus mitigating the need for large-area
single crystals. However, the case of twisted heterostructures, not
discussed here given the immaturity of this technology, will require
transfer of individual films with precise rotational alignment on
planar surfaces. If in situ growth of layered structures becomes
elusive, dry transfer protocols must be developed to create vertical
heterostructures.
The manufacturing techniques will have to ensure that the trans-
ferred films have clean surfaces to enable the ultimately necessary
low-defect-density 2D–2D interfaces. It is important to note that
these transfer techniques will be limited to planar vertically aligned
and twisted structures3.
In recent reports56,61,62, dry transfer of graphene using pick and
place techniques exploiting h-BN as the dielectric has proved to be
successful through the demonstration of very high carrier mobil-
ity (ranging from 30,000–80,000 cm2 V–1 s–1) in graphene on h-BN.
These results suggest that high-quality films can be achieved; the
question is how these processes can be transferred to a manufac-
turing environment. In the case of h-BN, small high-quality films
can be exfoliated from small bulk synthetic crystals but, while
progress is being made in growing large-area thin films by CVD
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184
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processes, the quality is still not as high as the exfoliated films and
the thin-film crystals are still at the micron level. Therefore, more
work has to be done to achieve high-quality synthetic h-BN thin
films. Additionally, if rotational alignment of 2D material hetero-
structures begins to yield devices with performance that exceeds
non-controlled stacking or registered films, the industry will have
to develop tools to achieve controlled alignment of 2D materials.
The growth of TMDs faces similar challenges to h-BN in that
wafer-scale single crystals are still not available, and stacked-crys-
tals and layer-by-layer wafer-scale single-crystal growth are yet
to be demonstrated. Significant efforts are being dedicated to the
understanding of single-crystal growth by CVD through simula-
tions63 and experiments51,64. The growth of lateral heterostructures
(Fig. 1d,e), as described above, will require a different approach.
Seeding experiments performed up until now64,65 will form the
basis for future lateral heterostructures. Seeding of both graphene
and TMD films has already been demonstrated and it is not dif-
ficult to imagine a process in which sequential films can be grown
in a similar way to graphene on Cu, where isotopic C was used to
demonstrate lateral growth54.
For lower-performance devices, layer-by-layer deposition from
2D crystal-based inks is another strategy for the scalable produc-
tion of 2D heterostructures66,67. However, although progress has
been made in this field6669, even under the best conditions these
materials will not meet high-performance device requirements and
thus will not be discussed further in this article.
Vertical and lateral heterostructure field effect transistors
In the pioneering years of a new field in science and technology, cre-
ativity flourishes and many original concepts are proposed, some-
times at the expense of good design. After this initial creative phase,
a screening phase is needed, since the measure of an electron device
is the improvement in performance and in functionality over the
incumbent technology.
Indeed, the possibilities opened up by vertical and lateral het-
erostructures have unleashed the creativity of researchers in recent
years, leading to the proposals of new transistor concepts and to
the experimental demonstration of different heterostructures of
2D materials. Figure 2 shows seven examples of potential transistor
structures. At the most basic level, the devices shown in Fig. 2 share
Fig. 1 | a, Direct growth of 2D-materials-based vertical heterostructures by CVD with (i) h-BN by exploiting ammonia borane as precursor and
(ii) graphene onto the as-grown h-BN layers. b, Growth by either CVD or MBE of individual 2D materials and subsequent dry transfer using pick and
place techniques enabling, in principle, any combination of different 2D materials. c, The relative orientation of the different layers of 2D materials is key
and mandatory to be controlled to design (i) vertically aligned and (ii) controlled twist heterostructures. d, Lateral heterostructures can be realized by (i)
seeding an already grown 2D material template, (ii) growing a second 2D material by using the appropriate precursors and (iii) by a proper placement
of seeds through either a pattern and etch process or a mask, which can allow the realization of different lateral heterostructures such as linear, zigzag
and donut-like shape. e, (i) Direct growth of h-BN on graphene edges; (ii) scanning electron microscopy image showing a concentric h-BN/graphene
heterostructure; (iii) optical image of a graphene/h-BN array of circles, with graphene circles embedded in an h-BN matrix. Panel (i) in c courtesy of
M. Kim and E. Tutuc; panel (ii) and (iii) in e adapted from ref. 15, Macmillan Publishers Ltd.
© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
NATURE NANOTECHNOLOGY | VOL 13 | MARCH 2018 | 183–191 | www.nature.com/naturenanotechnology 185
PersPective NaTure NaNoTechNology
a common operating principle: the current between one contact
(source) and the other contact (drain), separated by an energy bar-
rier—sometimes called the channel—is controlled by modulating
the height or the shape of such barrier via the voltage applied to the
gate electrode. For most transistor structures, we can have a ‘lateral’
implementation, in which current flows in the plane through a lat-
eral heterostructure, and a ‘vertical’ implementation, in which cur-
rent flows in the direction perpendicular to the layers.
In vertical22,24,27 and lateral28,3032,70 heterostructure FETs, the
channel consists of a material with a larger gap than that used in
the source and drain regions. In both cases, the voltage applied to
the top gate modulates the energy barrier height and therefore the
current. An interesting aspect is that heterostructures enable real
device optimization: on the one hand, the large gap region enables
the suppression of the current in the OFF state, thus yielding large
current modulation; on the other hand, mobility is inversely corre-
lated with the energy gap, that is, small or zero-gap materials in the
source and drain regions provide us with high-mobility regions and
low-resistance contacts4.
In vertical23 and lateral70 barristors, the Schottky barrier height
between a semimetal source with a low density of states (for exam-
ple, graphene) and a semiconductor drain is modulated by the top
gate voltage, thus tuning the thermionic current.
In the case of the graphene base transistor25,26, the barrier
between source and drain is represented by a graphene sheet sand-
wiched between two insulator or semiconducting layers. The voltage
Device structure ON state band profileOFF state band profile
Vertical
heterostructure
FET
(VH-FET)22
Lateral
heterostructure
FET
(LH-FET)29–31
Vertical barristor23
Lateral barristor70
Graphene base
transistor
(GBT)25,26
Lateral
heterostructure
TFET
(LH-TFET)71
Vertical
heterostructure
TFET
(VH-TFET)71
Semimetal
Dielectric
A
A’
B’
B
Graphene
A
B
A’
Dielectric
Semiconductor
Dielectric
AA’
B
Graphene
(base)
A
Dielectric
B’
B
AA’B
Electron flow
B’ AA
’B
B’
Dielectric
AA’
B
Dielectric
AA’ B’ B
2DM
Gate
DielectricDielectric
AA’
B
AA’B
Electron flow
AA
’B
AA’B
’B
2DM
AA’B’B
VDS
Electron flow
2DM
AA’B
Electron flow
AA’B
Silicon
A’
Semiconductor 2
Source Drain
Gate
2DM
Semimetal
Source
Drain
Gate
Gate
Back gate
Gate
Semimetal
Collector
Emitter
Back gate
Gate
VDS
Semiconductor 1
Semiconductor 2 Semiconductor 1
Fig. 2 | Seven proposed transistor structures based on 2D heterostructures. Left column: illustration of the device structure with main elements
highlighted (source, drain, gate, barrier). Middle column: sketch of the band-edge profile along the transport direction in the ON state. Right column:
sketch of the band-edge profile along the transport direction in the OFF state. 2DM, 2D material.
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186
PersPective
NaTure NaNoTechNology
applied to the graphene sheet, the ‘base, modulates the shape and
the height of the barrier. This structure is intrinsically vertical, since
its main asset is the exploitation of a one-atom-thick base, which—
at least in principle—can enable ultrafast traversal times. In practice,
radio-frequency operation of graphene base transistors is limited by
inter-electrode capacitances, which can dominate over the capaci-
tance associated with charge transport, and by the relatively small
tunnelling/thermionic currents.
Another option is represented by vertical and lateral tunnel
FETs, in which drain current flows via interband tunnelling through
a lateral or a vertical type-II heterostructure71. In this case, by vary-
ing the voltage applied to the top gate, the tunnelling barrier profile
can be modified, hence modifying its transmission coefficient and
the current (Fig. 2). Type-II heterostructures are particularly conve-
nient because they can provide a very transparent barrier in the ON
state, due to the staggered band alignment72.
All the transistor structures mentioned represent a revolution
in terms of materials and device structures, but they still must be
used in conventional digital logic, that is, the CMOS logic archi-
tectures used in present-day silicon technology. For this reason,
we can assess the prospects of each device type using as a bench-
mark the consensus on the expected evolution of silicon technol-
ogy illustrated in Fig. 3, reached by the International Technology
Roadmap for Semiconductors (ITRS) 2.0, 2015 edition40, and
by its successor, the International Roadmap for Devices and
Systems (IRDS)41.
According to these consensus documents and to more recent
experimental results43 and technology computer aided design
(TCAD) analysis44, in the short term the so-called FinFETs, pro-
posed by UC Berkeley in 199842 and first manufactured by Intel
in 2011 for the 22 nm node, and the lateral GAA FETs can sus-
tain Moore’s law up to the so-called 8/7 nm technology node
(expected in 2021) and possibly even beyond based on fabrication
considerations44. Fully-depleted Silicon-on-Insulator (FDSOI)
technology is expected to stop at the 11/10 nm technology node.
Both the ITRS and the IRDS acknowledge that there will be unre-
solved issues by 2021, indicating that vertical GAA transistors
or monolithic 3D integration, that is, vertical stacking of planar
transistors, will be the likely solutions. Increasing the number of
vertically stacked transistors enables the continued increase of the
number of transistors per chip, required by Moore’s law, even at
constant transistor size.
In this context, transistors based on 2D materials can have
intrinsic advantages, since the van der Waals interactions between
adjacent layers pose less stringent constraints on vertical stacking,
and therefore might be suitable to the stacking of many transistor
layers with no or limited performance degradation.
Limited interaction between adjacent layers is promising for
preserving charge carrier mobility in the case of very thin layers. It
is indeed well-known7375,77 that in the case of silicon, germanium
and InAs, charge carrier mobility sharply decreases with decreas-
ing layer thickness. Indeed, with decreasing layer thickness, we have
increased quantum confinement of electrons that causes an increase
in electron–phonon scattering rates, surface roughness scattering
rates and scattering due to thickness variations and remote pho-
nons, all mechanisms leading to mobility degradation (Fig. 4a).
On the contrary, semiconducting TMDs can provide thinner lay-
ers with a mobility value in the 20–200 cm2 V–1 s–1 range7882,84.
Graphene has been shown to achieve mobility at room temperature
exceeding 2,000 cm2 V–1 s–1 on SiO2 substrates76 and close to 80,000
cm2 V–1 s–1 on h-BN (ref. 61).
The corresponding mean free path (Fig. 4b) in TMD films is in
the range of 1–4 nm for TMDs and of 20–100 nm for graphene,
as extracted from mobility data of Fig. 4a, which is comparable
to the channel or barrier region of a 2D heterostructure-based
transistor22,24,27,31,70. This suggests that transport will be dominated
by the quality of the lateral heterojunctions, which are, however, still
insufficiently controlled and understood.
Bulk Si
Source Drain
Gate
Bulk Si
Source Gate
Drain Bulk Si
Source
Drain
Gate
Channel BOX
Gate
Drain
Oxide
Source
BOX
Gate Drain
Gate
Source
Drain
Gate
Semiconductor Oxide Metal
Channel
Channel
ChannelSource
Source
Drain
Year 2017 2019 2021 2024 2027 2030
Technology node (nm) “16/14” “11/10” “8/7” “6/5”“3/2.5” “2/1.5”
FinFET
FDSOI
Lateral GAA FET
Vertical GAA FET
Monolithic 3D
Fig. 3 | Consensus on the transistor device structure to be used in CMOS chips versus year of first shipment. Data according to the ITRS 2.0, 2015
edition40, and by its successor, the IRDS41 (yellow bars). The orange bars refer to the experimental results from ref. 43 on the 7 nm node FinFETs and to
TCAD analysis44.
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PersPective NaTure NaNoTechNology
Contact resistance (RC) of 2D materials is still an open issue89
given that present-day transistors have a
μR1m
C
and the best
results with graphene are of the order of 10
Ω μm
(ref. 90) and at
least one order of magnitude higher for metal–TMD contact resis-
tance86. However, the evolution of FETs to ultrathin body structures
reduces the difference between 2D materials and bulk semiconduc-
tors (Fig. 4c). In addition, requirements on RC can likely be relaxed
by one order of magnitude for digital applications, and heterostruc-
tures allow contact materials optimization. Still, this is one of the
most critical areas for the development of electronic devices based
on 2D materials.
To assess the transistor performance, the two main figures of
merit (FoM) for digital applications are the effective delay time,
which is a measure of device speed, and the power-delay product,
which is a measure of energy efficiency58. The effective delay time
is defined as:
τ=∕CV I(1)
DD ON
and the power-delay product as:
τ==
VI CVPDP(2
)
DDDD ON 2
where C is the transistor gate capacitance and VDD is the supply
voltage.
Here, we should stress that, in a n-type FET, both the so-called
OFF current IOFF and ON current ION are the drain currents when
the source is at zero voltage and the drain is at the supply voltage
bc
d e
Ge on
insulator
Si on insulator (electrons)
Si on insulator (
MoS2
WS2
InAs
Graphene
on SiO2
Graphene embedded in h-BN
(electrons)
(electro
Black
phosphorus
WSe2
ITRS
MoS2
MoS2/Au
Graphene/Pd
MoS2-2H/Au
MoS2-1T/Au
MoS2/Au
MoS2/Ni
Si on
insulator (electrons)
InAs
Graphene
on SiO2
Black
phosphorus
Ge on
insulator
MoS2
WS2
WSe2
a
VH-FET (graphene)
Graphene barristor
τ
(ps)
High performance
Thickness (nm)
Mobility (cm2V–1 s–1)
Mean free path (nm)
Contact resistance (Ωμm)
τ
(ps)
Low power
104
102
10–2
10–2
10–1
100
10–2
10–1
100
10–1 100
101
102
10–1
100
101
102
100
102
104
106
101
102
103
104
105
100
2015
ITRS
LH-FET (MoS2)
LH-FET (MoS2)
PDP (fJ
μ
m
–1
)
PDP (fJ μm–1)
LH-FET (graphene/h-BN)
LH-FET (graphene/h-BN)
MoS2 (planar barristor)
MoS2 (planar barristor)
2017
2019
2021
2015
ITRS
2017
2019
2021
6810402
Thickness (nm)
6810402
Thickness (nm)
6810402
Si on
insulator (holes)
Si on
insulator (holes)
Fig. 4 | Potential of heterostructure of 2D materials for transistor applications. a, Experimental mobility versus thickness for different 2D materials and
thin body semiconductors. b, Mean free path versus thickness for different 2D materials and thin body semiconductors, extracted from mobility and
carrier density measurements. Data sources for a,b: electrons in SOI73,74, holes in SOI74, holes in germanium-on-insulator75, graphene on SiO2 (ref. 76),
graphene embedded in h-BN (ref. 61), InAs (ref. 77), WSe2 (refs 78,79), WS2 (ref. 81), black phosphorus82,83, MoS2 (refs 84,85). c, Experimental RC of different
2D materials and thin body semiconductors compared with expectations of the ITRS. Data sources: ITRS40, MoS2 (ref. 84), MoS2-2H/Au and MoS2-1T/
Au (ref. 86), MoS2/Au (refs 87,88) and MoS2/Ni (ref. 87), Pd-Graphene90. d, Scatter plot of delay time and power-delay product for high-performance logic
of different 2D heterostructure-based FET and comparison with ITRS 2015. e, Scatter plot of delay time and power-delay product for low-standby-power
logic of different 2D heterostructure-based FET and comparison with ITRS 2015. Data sources for d,e are aligned to consider as transistor load the gate
capacitance of an identical transistor: ITRS40,41; Graphene-h-BN LHFETs, VH-FET, and Graphene barristor91; MoS2 LH-FET and MoS2 planar barristor70.
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VDD. ION is obtained when the gate is at VDD (ON state), whereas IOFF
is obtained when the gate is at zero voltage (OFF state).
The FoM must be referred to the two main application classes
for CMOS technology, high performance (HP) and low power (LP),
which put different constraints on the static power consumption.
At the transistor level, they translate into specifications for the OFF
current, that is, IOFF must be 100 nA μ m–1 in the case of HP devices
and 100 pA μ m–1 in the case of LP devices40,41.
A lower IOFF for the LP application class typically implies a lower
ION and therefore higher τ at fixed VDD. The route for device optimi-
zation is clear: the steeper the current modulation the better, since
increasing ION with low VDD and with low C—at fixed IOFF—has a
positive impact on both speed and energy efficiency. This requires
the barrier potential to be very sensitive to the gate voltage (in the
device engineers jargon, the device must have ‘good electrostat-
ics’)12,41 and the stray capacitance to be minimized40,41. Indeed, these
two aspects are the most important differentiators, in terms of
application prospects.
Recently, multiscale simulation approaches9194, ranging from ab
initio simulations of materials and interfaces to complete devices,
enabled the quantitative evaluation of the FoM and therefore the
optimization of each transistor structure. Here, we choose to con-
sider the best-case scenario of defectless transistors, ideal geom-
etries and ballistic transport. Transistor structures that even in
extremely optimistic conditions would not be competitive with the
ITRS requirements should be abandoned as candidate technolo-
gies. On the contrary, those that instead are competitive will require
some more critical testing and development.
Here, we compare optimized transistor structures based on 2D
heterostructures in terms of τ and PDP for the HP (Fig. 4d) and
for the LP (Fig. 4e) application classes. The ideal regions are the
lower left corners of the graphs in Fig. 4d,e. It is apparent that only
the lateral barristor and the LH-FETs have competitive FoM that
could meet the CMOS technology requirements (ITRS 2.0). All of
the vertical devices have worse FoM by three orders of magnitude.
The reason is that in the vertical devices there is a semimetal layer
(typically, the graphene layer) that is very close to the gate electrode
and that, on the one hand, screens the electric field induced by the
gate voltage, worsening device electrostatics and, on the other hand,
is responsible for an increased stray gate capacitance. Both effects
tend to degrade the FoM values.
Opportunities and conclusion
Transistors based on heterostructures of two-dimensional materials
offer new opportunities to sustain Moore’s law, but also pose many
challenges. The opportunities reside in the possibility to have atom-
ically thin layers that are only weakly coupled to adjacent ones, pro-
viding an easier path to three-dimensional stacking and enabling
further scaling of planar transistors with good electrostatics, if stray
capacitances are properly minimized. Both conditions are essential
to sustain the exponential increase of the number of transistors per
chip to sustain Moore’s law.
However, 2D semiconductor materials with a semiconducting
gap larger than 0.5 eV, required for thermionic FET operation, have
poor contact resistance and, at best, acceptable mobility. Lateral
heterostructures can provide a solution by enabling the optimiza-
tion of materials for different transistor building blocks (regions of
semiconducting material for the channel, and quasi-metallic mate-
rials for the source/drain regions and contacts). However, growth
or formation of lateral heterostructures is still at the infancy stage.
The road for a digital IC technology based on 2D materials
therefore cannot be discarded but is extremely narrow. To maxi-
mize the probability of success, it is important to focus the efforts
on the options that can provide competitive performance at least in
the most optimistic case. In our view, such options are represented
by planar transistors, using vertical 3D stacking as a further way to
improve transistor density and lateral heterostructures to optimize
device performance.
Received: 16 September 2017; Accepted: 30 January 2018;
Published online: 6 March 2018
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Acknowledgements
We acknowledge financial support from the European Union’s Horizon 2020 research
and innovation program under grant agreement no. 696656—GrapheneCore1, and a
Newton International Fellowship.
Competing interests
The authors declare no competing interests.
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Reprints and permissions information is available at www.nature.com/reprints.
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... Two-dimensional (2D) materials represent one of the most promising technology for next-generation beyond-CMOS electronics [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. Their layered structure makes them suitable to realize field-effect transistors (FETs) with atomically thin channels. ...
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Additional text is required to explain the relationship between Figure 5a and 5b. The revised caption of Figure 5b, shown below, contains the new text: Figure 5: (b) ID vs VD for the smallest device measured (LC ≈20 nm) showing ID > 300 µA/µm, a record for a TMD FET at ∼70 nm contact pitch. The data in Figure 5a and 5b were obtained before and after a reduction in threshold voltage from VT ˜≈2 V to -2 V, respectively, after device stress up to VD = 3 V. The device was stable before and after this point, as shown by dual forward-backward sweeps revealing minimal hysteresis. The analysis and conclusions of our work remain unaffected. We thank Professor Per Lundgren (Chalmers University of Technology) for bringing this to our attention.
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Chemical vapor deposition (CVD) of two-dimensional (2D) hexagonal boron nitride (h-BN) is at the center of numerous studies for its applications in novel electronic devices. However, a clear understanding of the growth mechanism is lacking for its wider industrial adoption on technologically relevant substrates such as SiO2. Here, we demonstrate a controllable growth method of thin, wafer scale h-BN films on arbitrary substrates. We also clarify the growth mechanism to be diffusion and surface segregation (D-SS) of boron (B) and nitrogen (N) in Ni and Co thin films on SiO2/Si substrates after exposure to diborane and ammonia precursors at high temperature. The segregation was found to be independent of the cooling rates employed in this report, and to our knowledge has not been found nor reported for 2D h-BN growth so far, and thus provides an important direction for controlled growth of h-BN. This unique segregation behavior is a result of a combined effect of high diffusivity, small film thickness and the inability to achieve extremely high cooling rates in CVD systems. The resulting D-SS h-BN films exhibit excellent electrical insulating behavior with an optical bandgap of about 5.8 eV. Moreover, graphene-on-h-BN field effect transistors using the as-grown D-SS h-BN films show a mobility of about 6000 cm² V⁻¹ s⁻¹ at room temperature.