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Detection and localization of appearance faults in reversible circuits
... The existing testing method in a quantum logic circuit is usually based on the ATPG [22][23][24][25]. Firstly, the size of input pattern sets for testing depend on the number of inputs, and test patterns need to be updated with different circuit constructs. ...
This article introduces a fault localization method to extract the exact location of single and multiple missing gate faults in reversible k-CNOT -based circuits. The primary target of the proposed method is to obtain the complete test set for localizing faults in k-CNOT circuits. We propose a fault localization algorithm to construct a fault localization tree that can be used to find equivalent and non-equivalent faults. For the non-equivalent faults, the test sequences can be obtained from the fault localization tree that uniquely localizes the non-equivalent faults. Finally, this article presents the experimental results and comparative analysis with existing works.
Quantum computation requires qubits that can be coupled and realized in a
scalable manner, together with universal and high-fidelity one- and two-qubit
logic gates \cite{DiVincenzo2000, Loss1998}. Strong effort across several
fields have led to an impressive array of qubit realizations, including trapped
ions \cite{Brown2011}, superconducting circuits \cite{Barends2014}, single
photons\cite{Kok2007}, single defects or atoms in diamond \cite{Waldherr2014,
Dolde2014} and silicon \cite{Muhonen2014}, and semiconductor quantum dots
\cite{Veldhorst2014}, all with single qubit fidelities exceeding the stringent
thresholds required for fault-tolerant quantum computing \cite{Fowler2012}.
Despite this, high-fidelity two-qubit gates in the solid-state that can be
manufactured using standard lithographic techniques have so far been limited to
superconducting qubits \cite{Barends2014}, as semiconductor systems have
suffered from difficulties in coupling qubits and dephasing \cite{Nowack2011,
Brunner2011, Shulman2012}. Here, we show that these issues can be eliminated
altogether using single spins in isotopically enriched silicon\cite{Itoh2014}
by demonstrating single- and two-qubit operations in a quantum dot system using
the exchange interaction, as envisaged in the original Loss-DiVincenzo proposal
\cite{Loss1998}. We realize CNOT gates via either controlled rotation (CROT) or
controlled phase (CZ) operations combined with single-qubit operations. Direct
gate-voltage control provides single-qubit addressability, together with a
switchable exchange interaction that is employed in the two-qubit CZ gate. The
speed of the two-qubit CZ operations is controlled electrically via the
detuning energy and we find that over 100 two-qubit gates can be performed
within a two-qubit coherence time of 8 \textmu s, thereby satisfying the
criteria required for scalable quantum computation.
A possible building block for a scalable quantum computer has recently been
demonstrated [M. Mariantoni et al., Science 334, 61 (2011)]. This architecture
consists of superconducting qubits capacitively coupled both to individual
memory resonators as well as a common bus. In this work we study a natural
primitive entangling gate for this and related resonator-based architectures,
which consists of a CZ operation between a qubit and the bus. The CZ gate is
implemented with the aid of the non-computational qubit |2> state [F. W.
Strauch et al., Phys. Rev. Lett. 91, 167005 (2003)]. Assuming phase or transmon
qubits with 300 MHz anharmonicity, we show that by using only low frequency
qubit-bias control it is possible to implement the qubit-bus CZ gate with 99.9%
(99.99%) fidelity in about 17ns (23ns) with a realistic two-parameter pulse
profile, plus two auxiliary z rotations. The fidelity measure we refer to here
is a state-averaged intrinsic process fidelity, which does not include any
effects of noise or decoherence. These results apply to a multi-qubit device
that includes strongly coupled memory resonators. We investigate the
performance of the qubit-bus CZ gate as a function of qubit anharmonicity,
indentify the dominant intrinsic error mechanism and derive an associated
fidelity estimator, quantify the pulse shape sensitivity and precision
requirements, simulate qubit-qubit CZ gates that are mediated by the bus
resonator, and also attempt a global optimization of system parameters
including resonator frequencies and couplings. Our results are relevant for a
wide range of superconducting hardware designs that incorporate resonators and
suggest that it should be possible to demonstrate a 99.9% CZ gate with existing
transmon qubits, which would constitute an important step towards the
development of an error-corrected superconducting quantum computer.
There is recently an interest in test generation for reversible circuits, but nothing has been published about fault localization in such circuits. This paper deals with fault localization for binary reversible (permutative) circuits. We concentrate on functional test based fault localization, to detect and locate "stuck-at" faults in a reversible circuit by creating an adaptive tree. A striking property of reversible circuits is that they exhibit "symmetric" adaptive trees. This helps considerably by being able to generate only half of the tree, and the other half is created as the mirror image of the first half. Because each test covers half faults [1] and the fault table has a high density of ones, it is relatively easy to generate the tree. The problem of fault localization of reversible circuits is therefore easier than the same problem for standard irreversible circuits. We present some preliminary results from an approach using traditional adaptive tree methods. We propose also a new efficient algorithm that eliminates the fault table generation and dynamically creates the adaptive fault tree.
The generation, manipulation and fundamental understanding of entanglement lies at the very heart of quantum mechanics. Entangled particles are non-interacting but are described by a common wavefunction; consequently, individual particles are not independent of each other and their quantum properties are inextricably interwoven. The intriguing features of entanglement become particularly evident if the particles can be individually controlled and physically separated. However, both the experimental realization and characterization of entanglement become exceedingly difficult for systems with many particles. The main difficulty is to manipulate and detect the quantum state of individual particles as well as to control the interaction between them. So far, entanglement of four ions or five photons has been demonstrated experimentally. The creation of scalable multiparticle entanglement demands a non-exponential scaling of resources with particle number. Among the various kinds of entangled states, the 'W state' plays an important role as its entanglement is maximally persistent and robust even under particle loss. Such states are central as a resource in quantum information processing and multiparty quantum communication. Here we report the scalable and deterministic generation of four-, five-, six-, seven- and eight-particle entangled states of the W type with trapped ions. We obtain the maximum possible information on these states by performing full characterization via state tomography, using individual control and detection of the ions. A detailed analysis proves that the entanglement is genuine. The availability of such multiparticle entangled states, together with full information in the form of their density matrices, creates a test-bed for theoretical studies of multiparticle entanglement. Independently, 'Greenberger-Horne-Zeilinger' entangled states with up to six ions have been created and analysed in Boulder.
An ESOP-based Toffoli gate cascade synthesis algorithm is presented. The algorithm is capable of generating a cascade of reversible gates for logic functions with large numbers of qubits. The algorithm is fast as it uses a simple cost metric heuristic during a recursive divide-and-conquer function to determine NOT and Toffoli gate placement.
Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test-set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test-set constructions for the standard stuck-at fault model, as well as the usually intractable cell-fault model. We also give a practical test-set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation.
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today's VLSI circuits, if current trends continue this will be a critical issue in the near future. Reversible circuits offer an alternative that, in principle, allows computation with arbitrarily small energy dissipation. Furthermore, reversible circuits are essential components of quantum logic. We consider the problem of testing these circuits, and in particular generating efficient test sets. The reversibility property significantly simplifies the problem, which is generally hard for the irreversible case. We discuss conditions for a test set to be complete, give a number of practical constructions, and consider test sets for worst-case circuits. In addition, we formulate the problem of finding minimal test sets into an integer linear program (ILP) with binary variables. While this ILP method is infeasible for large circuits, we show that combining it with a circuit decomposition approach yields a practical alternative.
Quantum error correcting codes have been shown to have the ability of making quantum information resilient against noise. Here we show that we can use quantum error correcting codes as diagnostics to characterise noise. The experiment is based on a three-bit quantum error correcting code carried out on a three-qubit nuclear magnetic resonance (NMR) quantum information processor. Utilizing both engineered and natural noise, the degree of correlations present in the noise affecting a two-qubit subsystem was determined. We measured a correlation factor of c=0.5+/-0.2 using the error correction protocol, and c=0.3+/-0.2 using a standard NMR technique based on coherence pathway selection. Although the error correction method demands precise control, the results demonstrate that the required precision is achievable in the liquid-state NMR setting. Comment: 10 pages, 3 figures. Added discussion section, improved figures
Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate faults (MMGF), are likely to be more suitable for modeling defects in quantum k-CNOT gates. This work proposes an algorithm for deriving the test set for the detection of all single missing gate faults in a reversible circuit implemented with k-CNOT gates. Instead of deriving test set directly for the detection of missing gate faults, a Boolean generator is developed by Boolean difference method to derive the test set and to detect all the single missing gate faults of a reversible circuit. Experimental results on some benchmark circuits are also reported.
Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations. In this method, the next test pattern is the response of the reversible circuit to the previous test pattern. A test generation algorithm to minimize test time and achieve 100% fault coverage is also presented. Simulation results on a set of reversible benchmark circuits confirm that this approach can detect all single missing/repeated gate faults as well as the majority of multiple faults.
Quantum computers promise to exceed the computational efficiency of
ordinary classical machines because quantum algorithms allow the
execution of certain tasks in fewer steps. But practical implementation
of these machines poses a formidable challenge. Here I present a scheme
for implementing a quantum-mechanical computer. Information is encoded
onto the nuclear spins of donor atoms in doped silicon electronic
devices. Logical operations on individual spins are performed using
externally applied electric fields, and spin measurements are made using
currents of spin-polarized electrons. The realization of such a computer
is dependent on future refinements of conventional silicon electronics.
Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an online resource for reversible functions and reversible circuits. RevLib provides a large database of functions with respective circuit realizations. RevLib is designed to ease the evaluation of new methods and facilitate the comparison of results. In addition, tools are introduced to support researchers in evaluating their algorithms and documenting their results.
The physical limitations, due to quantum mechanics, on the functioning of computers are analyzed.
Conservative logic is a comprehensive model of computation which explicitly reflects a number of fundamental principles of physics, such as the reversibility of the dynamical laws and the conservation of certainadditive quantities (among which energy plays a distinguished role). Because it more closely mirrors physics than traditional models of computation, conservative logic is in a better position to provide indications concerning the realization of high-performance computing systems, i.e., of systems that make very efficient use of the computing resources actually offered by nature. In particular, conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation. After establishing a general framework, we discuss two specific models of computation. The first uses binary variables and is the conservative-logic counterpart of switching theory; this model proves that universal computing capabilities are compatible with the reversibility and conservation constraints. The second model, which is a refinement of the first, constitutes a substantial breakthrough in establishing a correspondence between computation and physics. In fact, this model is based on elastic collisions of identical balls, and thus is formally identical with the atomic model that underlies the (classical) kinetic theory of perfect gases. Quite literally, the functional behavior of a general-purpose digital computer can be reproduced by a perfect gas placed in a suitably shaped container and given appropriate initial conditions.
Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances.
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a binary decision diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.
Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. This article presents an efficient algorithm to derive an optimal test set (OTS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that the OTS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on some benchmark circuits are also reported.
Reversible logic became a promising alternative to traditional circuits because of its applications in emerging technologies such as quantum computing, low-power design, DNA computing, or nanotechnologies. As a result, synthesis of the respective circuits is an intensely studied topic. However, most synthesis methods are limited, because they rely on a truth table representation of the function to be synthesized. In this paper, the authors present a synthesis approach that is based on Binary Decision Diagrams (BDDs). The authors propose a technique to derive reversible or quantum circuits from BDDs by substituting all nodes of the BDD with a cascade of Toffoli or quantum gates, respectively. Boolean functions containing more than a hundred of variables can efficiently be synthesized. More precisely, a circuit can be obtained from a given BDD using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, using the proposed approach, theoretical results known from BDDs can be transferred to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n · n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit. Keywords: Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
A computer is generally considered to be a universal computational device; i.e., it is believed able to simulate any physical computational device with a increase in computation time of at most a polynomial factor. It is not clear whether this is still true when quantum mechanics is taken into consideration. Several researchers, starting with David Deutsch, have developed models for quantum mechanical computers and have investigated their computational properties. This paper gives Las Vegas algorithms for finding discrete logarithms and factoring integers on a quantum computer that take a number of steps which is polynomial in the input size, e.g., the number of digits of the integer to be factored. These two problems are generally considered hard on a classical computer and have been used as the basis of several proposed cryptosystems. (We thus give the first examples of quantum cryptanalysis.) 1 Introduction Since the discovery of quantum mechanics, people have found the behavior of...
Imagine a phone directory containing N names arranged in completely random order. In order to find someone's phone number with a 50% probability, any classical algorithm (whether deterministic or probabilistic) will need to look at a minimum of N/2 names. Quantum mechanical systems can be in a superposition of states and simultaneously examine multiple names. By properly adjusting the phases of various operations, successful computations reinforce each other while others interfere randomly. As a result, the desired phone number can be obtained in only O(sqrt(N)) steps. The algorithm is within a small constant factor of the fastest possible quantum mechanical algorithm.
Reversible computing
- T Toffoli