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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008 371
Software-Based Resolver-to-Digital
Conversion Using a DSP
Santanu Sarma, Member, IEEE, V. K. Agrawal, and Subramanya Udupa
Abstract—A simple and cost-effective software-based resolver-
to-digital converter using a digital signal processor is presented.
The proposed method incorporates software generation of the re-
solver carrier using a digital filter for synchronous demodulation
of the resolver outputs in such a way that there is a substantial
savings on hardware like the costly carrier oscillator and associ-
ated digital and analog circuits for amplitude demodulators. In
addition, because the method does not cause any time delay, the
dynamics of the servo control using the scheme are not affected.
Furthermore, the method enables the determination of the angle
for a complete 360
◦
shaft rotation with reasonable accuracy using
a lookup table that contains entries of only up to 45
◦
. Computer
simulations and experimental results demonstrate the effective-
ness and applicability of the proposed scheme.
Index Terms—Angle measurement, resolver converter, resolver-
to-digital (R/D) conversion.
I. INTRODUCTION
R
ESOLVERS are very robust and cost-effective angular
position sensors that are extensively used in applications
like robots, machine tools, and radars. They are also used in
many safety critical systems like aircraft, satellite antennas,
and electromechanical braking systems [1], [2]. They resemble
small motors and have magnetically coupled rotor and stator
windings. The analog output of the resolver contains the angu-
lar position information that is obtained in digital form using
a resolver-to-digital (R/D) converter. Different methods [1]–[7]
exist in the literature, focusing on ways to improve the mea-
surement accuracy of the R/D converter; however, techniques
that are cost effective and reasonably accurate and that can
be implemented using less hardware to reduce the weight and
size, as preferred in space applications, are rarely found. For
instance, in [3], a method for reducing the position error caused
by the existence of nonideal resolver signal characteristics is
introduced by calibrating each resolver and R/D converter;
then, correction of the R/D converter output is performed in
real time. Although this method corrects most of the errors,
including those with an origin in the R/D converter, it is also
very labor intensive and time consuming, requiring excessive
signal processing and hardware. In [4], an R/D conversion
method that uses a bang-bang type phase comparator for fast
tracking is proposed. The concept of a phase-locked loop (PLL)
Manuscript received April 9, 2005; revised June 19, 2007.
The authors are with the Control Systems Group, Indian Space Re-
search Organization (ISRO) Satellite Centre, Bangalore 560017, India (e-mail:
santanu@isac.gov.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2007.903952
is used, which requires two low-pass filters to reject noise from
the R/D conversion loop. Consequently, this also results in a
considerable hardware requirement, in addition to that of the
amplitude demodulators, tracking errors at high speeds and
out-of-lock conditions of the PLL. In [5], a low-cost solution
for measuring the position by means of a standard resolver
and its implementation on a combined analog–digital board
is proposed. The method uses a digital clock, and filtering
of the harmonics from the digital clock is implemented to
generate the carrier of the resolver. The method compromised
the need for an accurate sinusoidal oscillator, resulting in a
harmonic content in the resolver carrier and deterioration of the
measurement performance. In [6] and [7], high-accuracy 360
◦
linearized converters are proposed. However, these techniques
also use considerable hardware, including analog amplitude
demodulators, analog multipliers, and glue logic for imple-
menting the arcsine function, which are generally affected by
nonideal behaviors like offset and nonlinearity.
In this paper, a novel and cost-effective 360
◦
linearized con-
verter is proposed, which includes software generation of the
resolver carrier using a single-multiplier sine–cosine generator
and synchronous demodulation of the output quadrature signals
using the generated carriers. This allows saving on the costly
oscillator and hardware-efficient demodulation of the resolver
output, even in the presence of wide variations in the resolver
carrier. In addition, because the method does not cause any
time delay, the dynamics of the servo control system using
the method is not affected. The delayless demodulation of the
resolver output is achieved by accurately sampling the positive
peak of the sinusoidal carrier using simple peak detection logic.
The obtained analog sine and cosine envelopes that contain
the angle information are digitized using an analog-to-digital
converter (ADC). The digitized envelopes are divided to obtain
the tangent of the angle. The corresponding angle is searched
from a lookup table (LUT) that contains values of only up to 45
◦
using the quadrant, octant, and tangent or cotangent relations to
determine the angle for a complete 360
◦
shaft rotation without
any singularity in the arctangent computation. Apparently, these
types of logic can easily be accommodated in the processor that
controls the servo system without the need for a separate R/D
converter card, saving cost, weight, and space.
II. P
RINCIPLE OF OPERATION OF A RESOLVER
This angular displacement sensor, which is widely used for
its fine resolution and accuracy, low output impedance, wide
temperature range of operation, small size, weight, and power
consumptions, and simple and robust construction, operates
0278-0046/$25.00 © 2008 IEEE
372 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 1. (a) Operating schematic diagram of the resolver. (b) Resolver output signals.
on the principle of mutual induction, as in a transformer. It
also provides the advantage of very high noise immunity when
combined with synchronous demodulator, as well as very long
distance transmission of the output data, without severe corrup-
tion by noise, before being converted to a digital format in the
vicinity of the processor at a reasonable cost. A simplified block
schematic diagram of a resolver and the associated signals is
shown in Fig. 1. The rotor contains the primary coil, which
consists of a single two-pole winding energized by an ac supply
voltage given by
v
ref
= V sin(ω
c
t) (1)
where ω
c
is the frequency of the excitation or carrier signal to
the rotor. The rotor is directly attached to the motor shaft whose
rotation is measured. The stator consists of two sets of windings
placed 90
◦
apart. In an ideal case, if the angular position of the
rotor with respect to one pair of stator windings is denoted by
θ, then the induced voltages in the pair of windings is given by
v
oc1
= g
v
v
ref
cos(θ)=A cos(θ)sin(ω
c
t) (2)
where A = g
v
V . The induced voltage in the other pair of
windings is given by
v
os1
= g
v
v
ref
sin(θ)=A sin(θ)sin(ω
c
t). (3)
These two output signals v
oc1
and v
os1
are called quadra-
ture signals. As the excitation or the carrier signal v
ref
is
an ac signal, clearly, the output voltages from the two-stator
windings are amplitude modulated, as shown in Fig. 2. In
other words, the carrier signal v
ref
is modulated by the angu-
lar displacement motion θ of the rotor. The determination of
the angular position in the first quadrant (0
◦
≤ θ ≤ 90
◦
) can
be obtained by using a constant gain. However, both signals
are needed to determine the angular displacement (direction
as well as magnitude) in all four quadrants (0
◦
≤ θ ≤ 360
◦
)
without causing any ambiguity. If the angular speed of the
rotor is denoted by ω such that θ = ωt, the differentiation of
the quadrature signals gives the parameter g
v
that depends
primarily on the geometric and material characteristics of the
device and, without loss of generality, can be taken as unity.
SARMA et al. : SOFTWARE-BASED RESOLVER-TO-DIGITAL CONVERSION USING A DSP 373
Fig. 2. Schematic diagram of software-based R/D conversion.
The differentiation of the two output signals v
oc1
and v
os1
is
given as
˙v
oc1
= − g
v
v
ref
ω sin(ωt),
˙v
os1
=+g
v
v
ref
ω cos(ωt). (4)
Hence, the speed of the rotation is
ω =˙v
os1
/v
oc1
= − ˙v
oc1
/v
os1
. (5)
The demodulation of the quadrature signals produces the
cosine and sine envelopes given by
v
c1
= V cos(θ)
v
s1
= V sin(θ) (6)
when g
v
=1. The angular displacement θ can be obtained from
the sine and cosine envelopes given by
θ = tan
−1
(v
s1
/v
c1
). (7)
For a multispeed resolver, another pair of quadrature signal
outputs that is a function of the multiple of the shaft angle θ
is available.
III. S
OFTWARE-BASED R/D CONVERSION
The block diagram of the R/D conversion scheme is shown in
Fig. 3. In this R/D conversion scheme, the sinusoidal carrier for
the resolver is generated in a digital signal processor (DSP),
and its peak is detected from the cosine part of the digital
sine–cosine carrier generator. The generated carrier is applied
to the resolver carrier terminals through a digital-to-analog
converter (DAC) of appropriate resolution. At the positive
peak, a pulse is simultaneously applied to the sample and hold
(SH) circuits for synchronous demodulation of the amplitude-
modulated output. Evidently, this undersampling of the resolver
output produces the carrier envelopes as a special case of
aliasing. The obtained envelopes of the amplitude-modulated
Fig. 3. Single-multiplier sine–cosine generator.
carrier are used to compute the shaft rotation θ by using an LUT
that contains arctangent values for a 360
◦
shaft angle.
Some of the major features of this software-based R/D con-
version that provide the potential for commercial use are listed
as follows:
1) flexibility of changing the resolver carrier parameters like
frequency and amplitude, which is obtained by simply
changing the constant of the sine–cosine generator;
2) noise-free carrier generation and precise detection of the
carrier peak for demodulation with very simple logic and
minimal computational effort;
3) synchronous demodulation of the quadrature signals that
does not introduce any time delay to affect the dynamics
of the servo loop;
4) reduction in cost due to a reduction in hardware like
oscillator, peak detectors, and other associated digital and
analog circuitry, evidently saving weight and size;
374 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 4. Tangent and cotangent of an angle.
5) performance and accuracy improvements as the effects of
parameter and environmental variations are reduced;
6) an LUT-based arctangent computation using quadrant and
octant logic to avoid singularities and computationally
efficient implementation of a 360
◦
linear converter.
It may be noted that the DAC that converts the digital carrier
to its analog equivalent and the ADC used for acquiring the sine
and cosine envelopes after demodulation should be selected
based on the performance and the accuracy requirements. High-
resolution DACs and ADCs can produce further improvement
in the performance and accuracy of the method.
The following subsection briefly describes the method of
generation of the sine carrier, associated peak detection logic
for synchronous demodulation, and arctangent computation us-
ing quadrant and octant logic for full shaft angle measurement.
A. Carrier Generation
The carrier signal to the resolver is generated by using a
digital sine–cosine generator [6], which is basically a second-
order digital filter with its pole on the unit circle. There are
many possible representations of this sine–cosine generator.
However, a single-multiplication structure with three associ-
ated addition steps is used for computation-efficient software
implementation.
Let s
1
[n] and s
2
[n] be the two outputs of a digital sine–cosine
generator given by
s
1
[n]=α
∗
sin(nω
c
)
s
2
[n]=β
∗
cos(nω
c
). (8)
From these equations, one can arrive at
s
1
[n +1]=α sin ((n +1)ω
c
)
= α sin(nω
c
)cos(ω
c
)+α cos(nω
c
)sin(ω
c
) (9)
s
2
[n +1]=β cos ((n +1)ω
c
)
= β cos(nω
c
)cos(ω
c
) − β sin(nω
c
)sin(ω
c
). (10)
Equations (9) and (10) can be rewritten in matrix form
using (8) as
s
1
[n +1]
s
2
[n +1]
=
cos(ω
c
)
α
β
sin(ω
c
)
−
β
α
sin(ω
c
)cos(ω
c
)
s
1
[n]
s
2
[n]
(11)
which is the state-space representation of the sine–cosine gen-
erator with a zero input. This representation requires many
multipliers and can be implemented using five of them. To
arrive at a computationally efficient structure of the sine–cosine
generator, a general second-order structure with no delay-free
loops [8] is considered, which is characterized by the following
equations:
s
1
[n +1]
s
2
[n +1]
=
0 a
00
s
1
[n +1]
s
2
[n +1]
+
cd
ef
s
1
[n]
s
2
[n]
=
a
∗
e + ca
∗
f + d
ef
s
1
[n]
s
2
[n]
. (12)
By comparing (11) and (12), one gets
e = −
β
α
sin(ω
c
)
f =cos(ω
c
)
a ∗ e + c =cos(ω
c
)
a ∗ f + d =
α
β
sin(ω
c
). (13)
By expressing the multiplier constants a and d as a func-
tion of the multiplier constant c, and with some simple
manipulation, one obtains the following five-multiplier repre-
sentation [8]:
s
1
[n +1]
s
2
[n +1]
=
0
α(c−cos ω
c
)
β sin ω
c
00
s
1
[n +1]
s
2
[n +1]
+
c
α(1−c cos ω
c
)
β sin ω
c
−
β
α
sin ω
c
cos ω
c
s
1
[n]
s
2
[n]
. (14)
SARMA et al. : SOFTWARE-BASED RESOLVER-TO-DIGITAL CONVERSION USING A DSP 375
Fig. 5. Quadrant selection conditions.
To reduce the total number of multipliers, different combina-
tions of the multiplier constant c have been used. For example,
c =cosω
c
gives the four-multiplier representation of (11). A
three-multiplier representation is achieved by using α sin ω
c
=
±β or α = ±β sin ω
c
[8] in (14). A single-multiplier structure
can be derived by setting β = α tan(ω
c
/2) in (14) for which
the expressions reduce to the following:
s
1
[n +1]
s
2
[n +1]
=
cos(ω
c
)cos(ω
c
)+1
cos(ω
c
) − 1cos(ω
c
)
s
1
[n]
s
2
[n]
=
cos ω
c
∗ (s
1
[n]+s
2
[n]) + s
2
[n]
cos ω
c
∗ (s
1
[n]+s
2
[n]) − s
1
[n]
. (15)
Another single-multiplier representation is derived by set-
ting α = −β tan(ω
c
/2) in (14) for which the expressions are
given by
s
1
[n +1]
s
2
[n +1]
=
cos(ω
c
)cos(ω
c
) − 1
cos(ω
c
)+1 cos(ω
c
)
s
1
[n]
s
2
[n]
=
cos ω
c
∗ (s
1
[n]+s
2
[n]) − s
2
[n]
cos ω
c
∗ (s
1
[n]+s
2
[n]) + s
1
[n]
. (16)
The block diagram representation of (15) and (16) is shown in
Fig. 3(a) and (b), respectively.
It can be noted that the single-multiplier structure gener-
ates the oscillations for any nonzero initial condition, and
the frequency of the oscillation is governed by the cos ω
c
multiplier constant term. Furthermore, the single-multiplier
structure retains its characteristic roots on the unit circle under
finite word-length constraints, and implementation in fixed-
point processors does not pose any limitations. On the other
hand, in other realizations of the sine–cosine generators, roots
may go inside or outside the unit circle due to the quantization
of the multiplier coefficients, causing the oscillations to decay
or build up. In addition, due to product roundoff errors, the
sequences that were generated by the sine–cosine generator
may not retain their sinusoidal behaviors, even in the case
of a single-multiplier generator. One way to overcome this
situation is to reset the state variables after some iterations at
prescribed points so that the accumulated errors do not become
unacceptable.
Fig. 6. Octant and corresponding shaft angle.
B. Synchronous Amplitude Demodulation
By using the generated sine and cosine carrier signals, the
resolver output can be demodulated by using any of the syn-
chronous demodulation techniques, specifically to avoid any
delay in the extracted sine and cosine envelopes. A simple way
to achieve this is by simultaneously sampling the quadrature
outputs of the resolver at the positive peak of the carrier. The
peak of the sinusoidal carrier is detected by using the cosine
signal and comparing it to a value greater than or equal to zero.
A pulse is produced during the positive half of the cosine signal
that directly coincides with the peaks of the sinusoid. The rising
edge of this pulse is used to simultaneously latch the value
of the quadrature outputs of the resolver to two SH circuits.
This results in the synchronous amplitude demodulation of the
resolver outputs.
The detection of the carrier peak plays an important role in
the accuracy of the measurement. In cases where a hardware
376 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 7. Software-based R/D conversion operation.
oscillator with zero-crossing detectors is used, the presence of
noise in the carrier will produce ambiguity in accurate peak
detection, thereby introducing deviations from the expected
envelopes. The software-based approach can overcome these
problems of noise and environmental degradation effects with
the added flexibility of easily configuring the carrier frequency
and amplitude. Furthermore, the change in the carrier frequency
and amplitude does not limit the method of demodulation and
R/D conversion.
C. Angular Position and Rate Computation for a
Full Shaft Rotation
The sine and cosine envelopes that were obtained after
demodulation of the resolver quadrature signal are used to
compute the angular rotation θ. The division of the sine en-
velope by the cosine envelope gives tan(θ), and the tangent
inverse of that provides θ. It is to be noted that any amplitude
imbalance in the demodulated envelopes will cause error in
the computed shaft angle, which can be avoided by calibrating
the resolver. Furthermore, the computation of tan(θ) will have
singular points at multiples of π/2 that will create numerical
problems while implementing in the processor, as shown in
Fig. 4. These singularities are avoided by suitably selecting
the quadrant, octant, and the tangent or cotangent part of θ
that is always bounded by ±1, as shown in Fig. 4. In addition,
symmetrical properties exist between the tangent and cotangent
curves in Fig. 5 that can be exploited to use an LUT that
contains either arctangent or arccotangent values of only up to
45
◦
and to use suitable reverse indexing to get θ for a full shaft
rotation. These conditions for selecting the quadrants are shown
in Fig. 5.
Care needs to be taken so that boundary points in the
quadrants will not be repeated. The octant selection logic
and the computation of θ using only the arctangent function
values are shown in Fig. 6. The values of the arctangent
function from 0
◦
to 45
◦
are stored in equal steps in an LUT
that determines the resolution of shaft angle measurement. By
increasing the number of points in the table, the resolution
can be improved. Furthermore, the computation of the rate can
be performed from the computed angular position either using
forward or backward derivative operation. A better estimate of
position, as well as speed, can be achieved by canceling the
systematic errors as in [9] and automatically calibrating the
system using adaptive techniques like recursive least squares
filters [10].
SARMA et al. : SOFTWARE-BASED RESOLVER-TO-DIGITAL CONVERSION USING A DSP 377
Fig. 8. Error for different ADC and DAC resolutions with (a) and (c) 12-bit ADC and DAC, 16-bit LUT, and (b) and (d) 10-bit ADC and DAC, 16-bit LUT, at
300 and 600 rpm, respectively.
IV. SIMULATION AND EXPERIMENTAL RESULTS
Simulation of the software-based R/D scheme is shown in
Fig. 7. The constant cos(ω
c
) is suitably set by using (8) to
get the required carrier frequency and an adequate number of
sample points per shaft rotation from the sine–cosine generator.
For instance, to have a carrier frequency of 1 kHz at a sampling
frequency of 15 kHz, cos(ω
c
) is set to 0.91354545764260.
The amplitude of the carrier is normalized and applied to a
zeroth-order hold DAC. The quadrature signal outputs of the
resolver at 600 rpm are shown in Fig. 7. The SH circuit is
simultaneously triggered at the zero crossing of the cosine
carrier, resulting in the synchronous amplitude demodulation
of the resolver outputs. These are used to compute the shaft
angle, as shown in Fig. 7. The errors in the measured an-
gle for a complete rotation for different cases are shown in
Fig. 8. As seen in Fig. 8, the simulated error produced by
this R/D conversion is within ±5e − 4 with floating-point
arithmetic. However, due to the quantization in the ADC and
DAC and the fixed-point representation of the LUT, the ac-
curacy reduces to ±1e − 3 for different cases, as shown in
Fig. 8.
The setup used for testing the proposed converter is shown
in Fig. 9. It includes an Analog Devices DSP-based resolver
simulator board for producing the quadrature signals using the
carrier generated in the proposed R/D converter DSP card.
This resolver simulator provides the flexibility of producing
a precise angular rotation for a large range in a controlled
manner. It samples the carrier signal and multiples with the
internally generated sine and cosine of the shaft rotations.
The quadrature outputs from the resolver simulator card are
mapped to fit the maximum range (±5 V) of the DAC and
ADC (AD1671) of the R/D converter. However, in practice,
suitable amplification may be needed to achieve the required
excitation voltage: for instance, 18-V peak-to-peak for the
Global Drive MDSKA 071-22 [11] resolver. For this resolver,
the amplitude of the output signals becomes 4.5 V with the
transformation ratio between the stator and rotor windings
being 0.5. However, the experimental results presented in
Fig. 10 are obtained for a 5-V resolver output that is sampled
through an ADC interface card to the ISA-based ADSP-21062
board for the proposed R/D converter. The software for the
proposed R/D converter is implemented in assembly language
of an ADSP-21062 processor using the EZ-LAB development
system.
Fig. 10(a) shows the resolver simulator outputs that are
produced using a 1-kHz carrier from the R/D converter. The
378 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 9. Experimental setup used for the proposed software-based R/D converter.
Fig. 10. Experimental results with the proposed R/D converter. (a) Resolver simulator outputs. (b) Demodulation of quadrature signal v
oc1
. (c) Demodulation
of quadrature signal v
os1
. (d) Demodulated envelopes. (e) Angle output with respect to the sine envelope. (f) Angle output with respect to the cosine envelope
at 300 and 600 rpm.
peak-to-peak voltage from the resolver simulator output is
±5 V. Fig. 10(b)–(d) illustrates the synchronous demodula-
tion of the resolver quadrature outputs. It can be observed in
Fig. 10(c) that there is a negligible delay caused by demodu-
lating the resolver outputs due to synchronous demodulation.
Fig. 10(e) and (f) shows the arctangent computation for a full
360
◦
rotation of the shaft in offset binary notations, with −5V
representing 000H and +5 V as FFFH. The plots reveal good
linearity of the converter from 0
◦
to 360
◦
. Furthermore, the
error difference between the angles that were measured by the
proposed R/D converter and that of the actual angle is close to
the computer simulations, as shown in Fig. 8.
V. C
ONCLUSION
A simple cost-effective software-based R/D converter has
been presented, which requires significantly less hardware and
computational resources for real-time implementation using a
DSP. The method includes processor-based generation of the
resolver carrier and innovative synchronous demodulation of
the outputs in such a way that the need for costly hardware
like oscillators and amplitude demodulators is avoided. The
sine–cosine carrier generator employs a single-multiplier struc-
ture to generate both the sine and cosine carriers that allow ac-
curate peak detection of the sinusoidal carrier by detecting the
zero crossover of the cosine part for synchronous demodulation
SARMA et al. : SOFTWARE-BASED RESOLVER-TO-DIGITAL CONVERSION USING A DSP 379
of the resolver outputs. A simple LUT-based angular position
computation provides the shaft angle for a complete 360
◦
shaft rotation without any singularity in the arctangent com-
putation. Moreover, the proposed method provides increased
flexibility and angle measurement with reasonable accuracy
without introducing any additional time delay in the measured
angle. Simulation and experimental results that illustrate the
effectiveness of the scheme are presented.
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Santanu Sarma (M’05) received the B.S. degree in
electrical engineering from Tripura Engineering Col-
lege (now National Institute of Technology), Tripura,
India, in 1999 and the M.Tech. degree in electron-
ics and communication engineering from Indian In-
stitute of Technology Guwahati (IITG), Guwahati,
India, in 2002.
Since 2002, he has been with the Control Systems
Group, Indian Space Research Organization (ISRO)
Satellite Center, Bangalore, India, as a Researcher.
He has been involved in the design and development
of the Attitude and Orbit Control System, the ASIC-based design of the bus
management unit for the INSAT and IRS class of satellites, UML modeling of
large software systems, and DSP-based system design. His research interests in-
clude modeling and analysis of control systems, embedded computing systems,
and VLSI signal processing.
Mr. Sarma is a member of the Institution of Electronics and Telecommuni-
cation Engineers, India. He is the recipient of the National Talent Scholarship,
the GATE Scholarship, and a gold medal from Tripura University.
V. K. Agrawal received the M.Tech. degree in elec-
trical and electronics engineering from the Indian
Institute of Technology, Kanpur, India, in 1978 and
the Ph.D. degree in computer science from the Indian
Institute of Science, Bangalore, India, in 1986.
He has been with the Indian Space Research Or-
ganization (ISRO) Satellite Center, Bangalore, since
1978, where he is currently the Group Director of the
Control Systems Group. He has worked on the de-
sign and development of onboard computer systems
for satellites with the state-of-the-art technology. His
research interests include parallel processing, fault-tolerant computing, VLSI
design, and microprocessor-based design.
Subramanya Udupa received the B.Eng. degree in
electronics and communication from Malnad Col-
lege of Engineering, Hassan, India, in 1984 and the
M.S. degree in software system from Birla Institue
of Technology and Science, Pilani, India, in 2005.
From 1985 to 1987, he was an R&D Engineer with
Integrated Process Automation, Bangalore, India. In
1987, he joined the Indian Space Research Organi-
zation (ISRO) Satellite Center, Bangalore, where he
is currently with the Control Systems Group. He has
been involved in the design and development of the
Attitude and Orbit Control Electronics and bus management unit for the INSAT
and IRS class of satellites. He is also the Head of the On-Board Software
Section, which is responsible for developing software for spacecraft.
