Article

Toward Ideal On-Chip Communication Using Express Virtual Channels

Princeton Univ., Princeton
IEEE Micro (Impact Factor: 1.52). 02/2008; 28(1):80 - 90. DOI: 10.1109/MM.2008.18
Source: IEEE Xplore

ABSTRACT

Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. we propose reducing energy and delay, and increasing throughput, using express virtual channels. packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

Download full-text

Full-text

Available from: Partha Kundu, Oct 16, 2015
  • Source
    • "To improve performance, express virtual channels are introduced in [20]. Beyond traditional wired interconnect solutions, different emerging approaches including 3D Network-on-Chip and Photonic Network-on-Chip were proposed [14] and [15]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in WNoCs. Thus, in this paper, we introduce a hierarchical WNoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are almost handled by single-hop wireless links. On top of that, we have also defined performance evaluation parameters. Simulation results show that the proposed architecture reduces average packet latency 16% and power consumption 14% in comparison with its conventional counterparts.
    Full-text · Conference Paper · Jul 2014
  • Source
    • "The EVC flow control mechanism proposed in [17] enables packets to entirely bypass routers. Figure 3 shows the router architecture supporting EVCs. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Manycore systems require energy-efficient on-chip networks that provide high throughput and low latency. The performance of these on-chip networks affects cache access latency and, consequently, system performance. This paper proposes solutions to address the performance limitations related to the use of snoop-based cache coherence protocol on switched network-on-chip (NoC). We propose a new network flow control technique, Express Virtual Channel with Taps (EVC-T), for transmitting both broadcast packets and data packets efficiently. In addition, we propose a low-latency broadcast packet notification tree network that maintains the order of broadcast packets on an unordered NoC. We evaluate our technique using both synthetic traffic and parallel benchmark suites through detailed system simulation. EVC-T reduces the average network latency by 24% with a negligible change in power for synthetic benchmarks. For NAS parallel applications, EVC-T increases the instructions per cycle (IPC) by 9% on average with minimal increase in power. Our technique reduces the energy-delay product (EDP) by 13% on average across all benchmarks.
    Full-text · Conference Paper · Aug 2011
  • Source
    • "This kind of network topology, commonly referred to as small-world, can be incorporated in NoCs by introducing long-range, high bandwidth and low power links between distant cores [1]. There have been efforts to improve NoC performance by introducing low-latency long-range links and low power express channels between highly separated nodes, where the performance gain is achieved by bypassing intermediate NoC switches/routers [1][2]. These communication channels are more efficient in terms of power and delay compared to their conventional counterparts, but they are still, basically, metal wires. "
    [Show abstract] [Hide abstract]
    ABSTRACT: While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This paper aims to present an overview of new, far-reaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.
    Full-text · Conference Paper · Mar 2011
Show more