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Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell
... With reducing supply voltage the memory cell becomes susceptible to variations, especially threshold voltage changes due to random doping fluctuations and memory cell NMOS transistors (M1, M3). which makes the memory cell less reliable during this operation. The 8T cell address this issue by having separate transistors, one where data is written and hold (M1 to M6) and the other where data is read from (M7-M8) [6]. ...
... In order to write the '1' into SRAM, WL is asserted as 1, and BL is made as high and BLB is low, the value of 0 is stored across 'BLB' and complement of B. After pre-charging Bit Line (BL=BLB=1), WL is pulling the one of the bit line low. But the stability of 8T SRAM data is increased, due to the single 8T SRAM, leakage current and data retention are greatly reduced among the major area of chip design today [6,7]. ...
... The two cross-coupled inverters M1, M6 and M2, M4 [6] are connected to back and M5, M6 are access transistors. In order to achieve Static Power Reduction. ...
As technology is increasing rapidly, the usage of low power devices has become more usable. One among such is transmission gate 8T SRAM. Static random access memory has now a day's become an important feature in the VLSI chip design. SRAM has become a sustainable research due to its fast development for low power. Static random access memory plays most prominent role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay parameters are the most common problems for SRAM cell which is basically designed for very low power applications. This paper presents architecture of TG8T SRAM cell with an improved version of existing 8T SRAM cell, where all pass transistors are replaced with transmission gates. The handy devices such as hand held mobile devices and special digital assistants are gaining more attractiveness as well as making changes in every phase of our daily life's. On chip cache represent a large portion of the chip and is expected to increase further in both moveable devices and high performance processors. Embedded memory access is more requisite in video applications, which results in momentous power consumption and confines the battery life. Owing to explosive growth of battery operated appliances, Power debauchery has become imperative reflection due to enlarged integration and operating speeds. Low power design has become a catchphrase now-a-days and deceitful of low power devices has become a foremost constraint in the locale of simulation such as power constrained applications. Researchers have recommended that operating a circuit in sub threshold region can condense the power utilization to bare minimum achievable range. It is only possible when its sub-threshold voltage (Vth) is greater than supply voltage (VDD) applied..With scaling of MOSFET to sub nanometer technology data stability of SRAM bit cells is major problem. Due to rapid increase in threshold voltage, 6T SRAM cannot operate in its efficient parameters in terms of Read &write operations[1], which results in the yield loss. Taking this drawbacks into consideration, we propose an transmission gate 8T SRAM cell (TG8T) where they can be operated both in terms of functionality and performance, and comparing their performance standards with standard 6T SRAM cell using synopsis tool and by using custom design model at 32nm technology. The rest of the paper is organized as section II explains the architecture of 6T SRAM and its operation, section III describes about the single bit 8T SRAM schematic design and its operation. Section IV describes about the TG8T SRAM cell with its read and writes operations. The Final section describes the about the functionality and performance is estimated by read &write operations[2] along with power and delay analysis & comparison is made between these different design types. II EXISTING 6TSRAM CELL The architectural designs of 6T SRAM cell undergoes several changes with read and write operations. The Static Noise Margin (SNM) is less due to no proper separation between read &write operations. The amount of leakage power is marginally high when the technology is scaling to the higher levels. The read and write operations can be analyzed by the given 6TSRAM as shown below. When
... Write & Read Operation Write operation The stability of the SRAM is enhanced by providing the isolation between reading port from the write bit line. Aanother set of stack transistors are used to Control the reading and write operation are done by write word line (WWL) & read word line (RWL) [4], [5]. ...
Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.
... The delay and rms power calculated in this work for 1-bit SET based SRAM has been compared with the 22 nm CMOS [21] based SRAM as shown in Table 3 and Table 4. Further, the average read and write delay of standard 6T SRAM cell at 0.8V presented in this work are 34.4ps and 3.9ps as compared to 3000ps and 60ps respectively at 1V demonstrated by Sharma et al. [22]. ...
In this paper, stability analysis of conventional 6-T SRAM cell and Schmitt trigger (ST) based 10-T SRAM cell with optimized sizing parameters has been performed and compared. The read stability, write ability, delay and dissipated power have been investigated. By using N-curve methodology a significant improvement of 4.49%, 5.13% and 28.65% in SVNM, SINM and WTI respectively was observed for Schmitt trigger (ST)
based 10-T SRAM cell as compared to optimized 6T SRAM cell. Furthermore, the effects of supply voltage and temperature on conventional 6T SRAM stability in read and write operational mode have also been examined. Furthermore, both read delay and read current were investigated for ST based 10-T SRAM cell and found in desirable limits. It is also interesting to note that read delay is improved by 66%. Monte-Carlo simulation
of the ST based 10-T SRAM cell circuit is carried out in order to find the deviation for power and the read current. The read current of the 10T topology is found to be 29.97μA with standard deviation of 4.55μA. Mean dynamic power for all process corners is also calculated by monte-carlo simulation of 4000 point each and deviation from the mean power was obtained. For simulation process 90nm technology node at 1V power supply was used on cadence virtuoso tool.
This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for superthreshold regions, the proposed cell is able to work at supply voltages lower than 200mV with significantly improved robustness without any leakage increase. The proposed SRAM design improves write margin of the SRAM cell in comparison to the standard 7T-SRAM cell. The proposed circuit is designed in TSMC 65nm CMOS technology.
In this paper, a novel 7T-SRAM cell for ultra-low power applications is proposed. The proposed SRAM cell is fully functional at subthreshold voltages down to VDDmin=200mV. In this technique, separate read/write bitlines and wordlines are used that makes read and write operation independent. The 7T-SRAM cell proposed in this paper, improves static read noise margin, write margin, and write time by 2.2X, 27%, and 6% in comparison to the standard 6T-SRAM cell. The 7T-SRAM cell proposed in this paper, improves write margin of the conventional 7T-SRAM cell, as well. The proposed 7T-SRAM cell is designed in 65nm CMOS technology.
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