Conference PaperPDF Available

A low power flash-FPGA based brain implant micro-system of PID control

July 2017
Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference 2017:173-176

DOI:10.1109/EMBC.2017.8036790

Conference: 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

Authors:

Lijuan Xia

Newcastle University

Nabeel Fattah

Hawler Medical University

Ahmed Soltan

Nile University

Andrew Jackson

Newcastle University

Show all 6 authorsHide

In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

A high level schematic of proposed low power FlashFPGA based micro-system of closed-loop PID Control operation for delivering further optogenetic stimulus.

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Measured optogentics stimulus modulation of which input test analog signal is 10Hz of sin wave.

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Figures - uploaded by Lijuan Xia

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Content uploaded by Lijuan Xia

Content may be subject to copyright.

A Low Power Flash-FPGA based Brain Implant Micro-System of PID

Control

Lijuan Xia, Nabeel Fattah, Ahmed Soltan, Andrew Jackson, Graeme Chester and Patrick Degenaar

Abstract— In this paper, we demonstrate that a low power

ﬂash FPGA based micro-system can provide a low power

programmable interface for closed-loop brain implant inter-

faces. The proposed micro-system receives recording local ﬁeld

potential (LFP) signals from an implanted probe, performs

closed-loop control using a ﬁrst order control system, then

converts the signal into an optogenetic control stimulus pattern.

Stimulus can be implemented through optoelectronic probes.

The long term target is for both fundamental neuroscience

applications and for clinical use in treating epilepsy. Utilizing

our device, closed-loop processing consumes only 14nJ of

power per PID cycle compared to 1.52µJ per cycle for a

micro-controller implementation. Compared to an application

speciﬁc digital integrated circuit, ﬂash FPGA’s are inherently

programmable.

I. INTRODUCTION

Closed-loop control is a promising strategy for suppressing

abnormal neuron disorders, such as epilepsy and Parkinson’s

diseases [1-3]. One of the core issues for closed-loop in-

terfaces is that there are a number of potential linear [4-5]

or non-linear [6] methods, which could be applied. These

could most efﬁciently be implemented onto an ASIC [7]

but at the cost of re-programmability [8]. Alternatively mi-

croprocessor platforms such as micro-controllers and digital

signal processors provide excellent programmability. But it

may cost much more in terms of energy consumed per pro-

cessing cycle. Field Programmable Gated Arrays (FPGAs)

can provide re-programmability at the circuit level but have

been traditionally power hungry [9].

Flash FPGAs utilize ﬂash memory elements rather than

SRAM in their architecture, and thus consume minimal static

power (as low as 2uW) and can be reliably reprogrammed

up to 500 times, which is more than sufﬁcient for most

tuning requirements. There are additional SRAM registers

which can store data which can be written indeﬁnitely. So

the key question we hope to answer in this effort is whether

or not it is a trustworthy platform for reprogrammable

closed-loop neural control. We therefore implement an ex-

emplar Proportional-Integral-Derivative (PID) control algo-

rithm. PID control theory has been employed theoretically

in the neuroscience research ﬁeld [10]. There are only a

few examples of it being implemented onto low power

Lijuan Xia is with School of Electrical & Electronics Engineering,

Newcastle University, United Kingdom, e-mail: (l.xia@ncl.ac.uk).

Nabeel Fattah, Ahmed Soltan, Graeme Chester, Patrick Degenaar are

with School of Electrical & Electronics Engineering, Newcastle University,

United Kingdom

Andrew Jackson is with Institute of Neuroscience, Newcastle University,

Newcastle upon Tyne, UK

implantable hardware of different re-programmability [11-

12].

Our target application is for closed-loop optogenetic con-

trol of epileptic brain activity. Our brain probe unit consists

of an intelligent probe with on-board micro-LEDs, recording

electrodes, and signal acquisition circuitry. The power con-

sumption of this probe is 1mW at a 10% optical duty cycle.

As such, a desirable power consumption for the control unit

is to be in the same range. Fig. 1 describes exploratory ﬂash

FPGA-based closed-loop brain implant interface. We have

implemented our control unit into a 50m x 25mm form factor.

And it will be miniaturized further for use in small rodent

research.

(a) Optrode

(b) Controller

PID

Control

Optical

control

ADC

ASIC Optrode FPGA controller

Electrode

LED

Neural Amplifier

Neural Stimulator

DAC

Fig. 1: A high level schematic of proposed low power Flash-

FPGA based micro-system of closed-loop PID Control operation

for delivering further optogenetic stimulus.

II. CLOSED-LOOP OPTICAL CONVERTER

ALGORITHM

A. PID Algorithm

This closed-loop microsystem is aimed at intervening neu-

ral network via generating closed-loop optogenetic feedback

to control epilepsy. The intervention philosophy is akin

to noise cancelling via destructive interference of signals

deemed outside a normal range. To achieve this approach

we are exploring a linear control methodology incorporating

proportional-integral-derivative (PID) components.

PID algorithm falls within the scheme of linear, time in-

variant (LTI) ﬁlters. In Fig. 2, we design our LTI Filter kernel

in the time domain for performing proportion, differentiation

and integration operation. The optrode sampling rate is 100

samples/second which represents every sample data costs

0.01 second, and the local ﬁeld potential frequency band

of interest is 1Hz to 100Hz. Accordingly, we set the ﬁlter

window taps as 100.

Table I theoretically describes the math methodology of

PID Filter kernel design. If a signal is convolved with Dirac

Linear Time Invariant

Digital Kernel

h(n)

Input

x(n)

Output

y(n)

Taps

(b)

Proportion Kernel Integral Kernel Derivative Kernel

Taps 𝑓/Hz Taps 𝑓/Hz Taps 𝑓/Hz

Taps

(c)

Taps

(d)

(a)

(b1) (b2) (c1) (c2) (d1) (d2)

FFT FFT FFT

Fig. 2: Linear time invariant digital design of The PID ﬁlter. (a)

Linear time invariant system. (b) Dirac delta kernel for bandpass

proportion. (c) Unit step kernel for integration. (d) Gaussian kernel

for derivative.

TABLE I: Proportion, Integral and Derivative Filter Kernel Design

P Ker nel y(t) = x(t)∗δ(t) = x(t)

IK ernel y(t) = x(t)∗Rδ(t)dt =Rx(t)dt ∗δ(t) = Rx(t)dt

DKernel y(t) = x(t)∗

dδ(t)

dt =dx(t)

dt ∗δ(t) = dx(t)

delta function δ(t), the result is identical to the original

signal. The proportion ﬁlter kernel is shown in Fig. 2 (b1),

the fast Fourier transform (FFT) of proportion kernel is

displayed in Fig. 2 (b2). In terms of integral ﬁlter design, if

an x(t) signal is convolved with integral δ(t), output signal

will be a time integral of the original signal. The integral

ﬁlter kernel is shown in Fig. 2 (c1), the FFT of integral

kernel is displayed in Fig. 2 (c2). Finally, If an x(t) signal

is convolved with differentiated δ(t), output signal will be

a time derivative of original signal. The derivative ﬁlter

kernel is shown in Fig. 2 (d1), and FFT of integral kernel is

displayed in Fig. 2 (d2).

The proportional, integral, and derivative kernel demon-

strated in Fig. 2 (b), (c) and (d) will be stored as lookup tables

in the ﬂash FPGA hardware implementation. Physically, they

are stored as three 100*1 column buffer banks consisting of

an 8-bit column registers implementing on novel ﬂash-based

logic arrays. These three kernels will be employed to do

multiplication with incoming digitalized local ﬁeld potential

for convolution operation.

B. Optical Stimulus

An optical optogenetic stimulus converter has been created

for converting output of PID module to optogenetic Pulse

Width Modulation (PWM) stimulus on the probe for mod-

ulating optogenetic infected neurons. Fig. 3 describes two

stages in the optical converter process, stage 1 is to adapt

output of PID controller to total optical stimulus following on

the non-linear inverse sigmoid transfer function shown in Fig.

3 (b), stage 2 employs a reciprocal counter for modulating

duty ratio of ﬁxed period pulses (10ms) for optogenetic

neural stimulation [13].

𝒌𝒈∗ 𝑷𝑰𝑫 − 𝒌𝑻

+𝒌𝒈𝒆𝒆

𝑷𝑰𝑫 𝑲𝒆

Inverse sigmoid function

inherently thresholds

(implemented as a look

up table)

Stage1: nonlinear adaptation Stage2: PWM output.

of PID output to total optical flux.

PWM

Clock

> 0?

Photons

Buffer

PWM

Output



(a) Optical Converter Schematic (b) Inverse Sigmoid

PID output intensity

PID Output

Stimulus intensity

Fig. 3: Intensity dependent optical stimulus mechanism: (a)

Schematic for converting output of PID controller to width modu-

lated pulse for delivering optogenetic stimulus (Kg =0.4, Kr = 128,

Kge=0.1, Ke=34). (b) Plot of non-linear inverse sigmoid function.

III. HARDWARE ARCHITECTURE

IMPLEMENTATION

Flash FPGA implementation architecture of PID control

design is shown in Fig. 4 which consists of the following

components:

1: A 100*1 row buffer bank of 8-bit row register is

receiving local ﬁeld potential from optrode for further PID

control.

2: Three 8-bit column registers (Kp, Ki and Kd) are

employed to store the gain parameters of proportion modules,

integral modules and derivative modules.

3: A 1*1 MUX is used for row buffer bank to select

corresponding row register for multiplication.

4: Three 100*1 column buffer banks of 8-bit column

registers are used to hold proportional Dirac Delta kernel,

integral unit step kernel, derivative Gaussian kernel (shown

in Fig. 2 (b), (c) and (d) respectively) as convolution kernels

to do further multiplication.

5: A 1*1 MUX is used for column buffer bank to select

corresponding column buffer bank for multiplication.

6: An accumulator adds all results of multiplication which

has been send to output buffer bank for generating further

closed-loop neural stimulation.

7: A 255*1 buffer bank of 8-bit register is sigmoid function

truth table for modulating further pulse width feedback to

optrode for closed-loop optogenetic stimulation.

8: A 1*1 MUX is applied for selecting corresponding

sigmoid look up table buffer to modulate pulse duty ratio.

9: A counter and a comparator are created to compare with

sigmoid look up table to decide PWM output (high or low).

Actel

IGLOO

AGLN250

VQG100

LT3080

Voltage Regulator

(5V 1.5V)

External Clock

25.9 mm

50 mm

Flash FPGA

(PID Algorithm)

Fig. 5: mini-PCB design of Flash-FPGA based brain implant

controller with PID control implementation in comparison with the

British decimal two pence coin.

174

ADC: 8-bit

ADCDAT[0]

ADCDAT[1]

ADCDAT[2]

ADCDAT[3]

…….

ADCDAT[99]

8-bit

Buffer Bank

Sigmoid

LUT









Optical

Converter



Coeff

[0]

Coeff

[1]

Coeff

[2]

Coeff

[3]

…….

Coeff

[99]

X

D Q

ADCDAT

[0]

…………

ADCDAT

[99]

MUX

PID Output

MUX

Sigmoid[1]

Sigmoid

[2]

Sigmoid

[3]

Sigmoid

[4]

…….

Sigmoid

[255]

Counter

Reference

LFP Input

Comp

PWM

Output

PWM

LFP

Kp/Ki/Kd



MUX

D Q D Q D Q

D Q

Fig. 4: FPGA architecture design of Proportion, Integration and Derivative (PID) Controller: Input buffer bank is for storing local ﬁeld

potential sampled by analogue-to-digital converter (ADC) of optrode , PID module is designed by linear time invariant ﬁlter , Output

buffer bank is for storing PID output for modulating further stimulus .

Proportion Output Integration Output

Derivative Output PID Output

(a) Proportion FPGA testing (b) Integral FPGA testing

Kp = 1 , Ki = 0 , Kd = 0 Kp = 0 , Ki =1, Kd = 0

Kp = 0 , Ki = 0 , Kd = 1 Kp = 1 , Ki =1, Kd = 1

Input

Input Input

Input

Fig. 6: The measured input and output test signal for verifying PID

ﬂash FPGA hardware implementation. (a) Proportion testing (b)

Integral testing: sawtooth wave of 10Hz, output of PID controller

is smooth and round integration signal which means contains a lot

of energy in low frequency band. (c) Derivative testing: input signal

is sawtooth wave of 10Hz, PID output is frequency modulated spiky

signal. (d) PID FPGA testing.

IV. RESULTS AND DISCUSSION

The whole design of PID algorithm has been implemented

in a ﬂash FPGA chip, with peripheral voltage regulator

circuit together, which have been fabricated in a mini-PCB

system shown in Fig. 5. The whole mini PCB body features a

size of 50mm*25mm which size is as twice as the prototype

size of British two pence coin. This node integrates a ﬂash

FPGA IGLOO nano (AGLN250V2-VQG100) device and a

voltage regulator peripheral circuit. Fig. 6 displays the mea-

Time/s Time/s

Amplitude /mV

Raw neuron data

(a) (b)

(c)

PID output: FPGA

Measurement

Frequency /Hz

Time/s

Fig. 7: (a) In-Vivo neural LFP recording (left). (b) PID control

FPGA output (right) (Kp=1, Ki=50, Kd=0.1). (c) Power spectrum

of PID control FPGA output.

surement of analogue input signal for testing the performance

of ﬂash FPGA-based PID control implementation which

exactly match Matlab simulation results. Fig. 7 describes

ﬂash FPGA-based PID control output for real neural local

ﬁeld potential for 1 second. As shown in Fig. 8, when input

is 10Hz sin wave, the output is width-modulated pulses of

10ms, the width is modulated non-linearly by intensity levels

of sin waves which represent output of PID Controller.

Table II shows that the whole PID design and inverse

sigmoid optical converter utilize totally 27.2% of the avail-

able of the logic cells on the ﬂash FPGA IGLOO nano

chip. The rest of logic cells can be employed for further

exploratory algorithm to perform better closed-loop neu-

ral stimulation algorithm. The power consumption of ﬂash

175

Optical Optical Input

Stimulus PWM Threshold Analog Signal

Input Signal 10Hz

Threshold for delivering stimulus

Optical Stimulus 10ms …… 10ms

NO Stimulus NO Stimulus

①

②

③

Fig. 8: Measured optogentics stimulus modulation of which input

test analog signal is 10Hz of sin wave.

TABLE II: PID and Inverse Sigmoid Optical converter Design

Utilization of Resources on the Flash FPGA IGLOO Nano Device

Memory Resource Used Available Utilization

Number of Look Up Tables 816 3000 27.20%

Working Frequency 1MHz

Power Consumption 0.168mW

FPGA IGLOO nano chip with PID controller implementation

costs 0.168mW which has been tested by a multimeter (Volt-

age rail: 1.2V, current: 0.12mA , standby power consumption:

0.024mW).

Table III compares power consumption of the same PID

micro-controller (ARM Cortex M4) implementation with

ﬂash FPGA (IGLOO Nano) implementation. In order to

provide a fair comparison, we operated both at a ﬁxed clock

rate of 1MHz. Furthermore, this is the internal clock rate

of the optrode, though the incoming LFP data rate is typi-

cally only 100 bytes per second. A comparison with recent

reported designs of proportion integral derivative hardware

implementation for closed-loop brain machine interface has

been listed in Table IV.

TABLE III: measured power consumption comparison between

ARM cortex M4 and ﬂash FPGA IGLOO nano

Hardware ARM Cortex M4 Flash FPGA nano

PID Execution time(clk cycles) 3300 100

Power(mW/MHz) 0.46 0.14

Energy(nJ/clk) 0.46 0.14

Energy per operation(nJ/PID) 1520 14.3

TABLE IV: Comparison With Bidirectional Neural Interface De-

sign

Reference Rhew[11] Xilin[12] This work

CMOS technology (nm) 180 180 130

Bandwidth (Hz) 0.64-6K 0.3-7K 0.1-10k

Feedback Control PI PID PID

Output Current (mA) 4.41 6 0.12

Voltage Rail (V) 1.8 0.9 1.2

Power Consumption (mW) 8 5.8 0.168

Reprogrammable Custom DSP ASIC ﬂash FPGA

V. CONCLUSIONS

In this paper, we have demonstrated a low power ﬂash

FPGA-based micro-system as closed-loop brain implant in-

terface. It sheds light on the potential possibility of applying

ﬂash FPGA in the general purpose brain machine interface

for beneﬁting more neuroscience research. This PID control

ﬂash FPGA implementation will also offer some inspirational

possibilities for closed-loop neural stimulus modulation in

neuroscience research and help neuroscientists to develop

better understanding of how to better perform closed-loop

stimulation.

ACKNOWLEDGMENT

The authors would like to thank the Wellcome

Trust and the EPSRC for funding the CANDO project

(www.cando.ac.uk). Lijuan Xia would also like to thank

Newcastle University SAGE Doctoral Training Awards

scheme and the Newcastle University Overseas Research

Scholarship for funding her PhD.

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Full-text available

Jun 2016

Closed-loop control is a promising deep brain stimulation (DBS) strategy that could be used to suppress high-amplitude epileptic activity. However, there are currently no analytical approaches to determine the stimulation parameters for effective and safe treatment protocols. Proportional-integral (PI) control is the most extensively used closed-loop control scheme in the field of control engineering because of its simple implementation and perfect performance. In this study, we took Jansen’s neural mass model (NMM) as a test bed to develop a PI-type closed-loop controller for suppressing epileptic activity. A graphical stability analysis method was employed to determine the stabilizing region of the PI controller in the control parameter space, which provided a theoretical guideline for the choice of the PI control parameters. Furthermore, we established the relationship between the parameters of the PI controller and the parameters of the NMM in the form of a stabilizing region, which provided insights into the mechanisms that may suppress epileptic activity in the NMM. The simulation results demonstrated the validity and effectiveness of the proposed closed-loop PI control scheme.

A Bidirectional Brain-Machine Interface Algorithm That Approximates Arbitrary Force-Fields

Article

Full-text available

Mar 2014
PLOS ONE

We examine bidirectional brain-machine interfaces that control external devices in a closed loop by decoding motor cortical activity to command the device and by encoding the state of the device by delivering electrical stimuli to sensory areas. Although it is possible to design this artificial sensory-motor interaction while maintaining two independent channels of communication, here we propose a rule that closes the loop between flows of sensory and motor information in a way that approximates a desired dynamical policy expressed as a field of forces acting upon the controlled external device. We previously developed a first implementation of this approach based on linear decoding of neural activity recorded from the motor cortex into a set of forces (a force field) applied to a point mass, and on encoding of position of the point mass into patterns of electrical stimuli delivered to somatosensory areas. However, this previous algorithm had the limitation that it only worked in situations when the position-to-force map to be implemented is invertible. Here we overcome this limitation by developing a new non-linear form of the bidirectional interface that can approximate a virtually unlimited family of continuous fields. The new algorithm bases both the encoding of position information and the decoding of motor cortical activity on an explicit map between spike trains and the state space of the device computed with Multi-Dimensional-Scaling. We present a detailed computational analysis of the performance of the interface and a validation of its robustness by using synthetic neural responses in a simulated sensory-motor loop.

On-demand optogenetic control of spontaneous seizures in temporal lobe epilepsy

Article

Full-text available

Jan 2013

Temporal lobe epilepsy is the most common type of epilepsy in adults, is often medically refractory, and due to broad actions and long-time scales, current systemic treatments have major negative side-effects. However, temporal lobe seizures tend to arise from discrete regions before overt clinical behaviour, making temporally and spatially specific treatment theoretically possible. Here we report the arrest of spontaneous seizures using a real-time, closed-loop, response system and in vivo optogenetics in a mouse model of temporal lobe epilepsy. Either optogenetic inhibition of excitatory principal cells, or activation of a subpopulation of GABAergic cells representing <5% of hippocampal neurons, stops seizures rapidly upon light application. These results demonstrate that spontaneous temporal lobe seizures can be detected and terminated by modulating specific cell populations in a spatially restricted manner. A clinical approach built on these principles may overcome many of the side-effects of currently available treatment options.

Low-Power Circuit Techniques for Epileptic Seizures Detection and Subsequent Neurostimulation

Article

Full-text available

Sep 2012

In this paper, we present low-power circuit techniques for implementing a closed-loop neurostim-ulator (CLNS) as an alternative treatment for medically refractory epilepsy. The proposed circuit has low-power dissipation with better detection sensitivity compared to the recently proposed circuit techniques for epileptic seizure detector. We demonstrate low-power circuit techniques for imple-mentation of an implantable CLNS, individual functional testing, and validation of the seizure detec-tor on real intracerebral EEG (icEEG) recordings and testing of self-triggering electrical stimulation. The CLNS comprises a low-power icEEG acquisition front-end, epileptic seizure detector, and a widely programmable current stimulator. Moreover, the tuneable parameters of the detector and stimulator are designed to adjust wirelessly. The detection algorithm was validated with Matlab tools and the detection circuits were implemented in 2 mm 2 chip area using CMOS 0.18-m process. The current-mode stimulator was assembled on two circular (Ø 20 mm) shape blocks in a printed circuit board (PCB). The proposed CLNS was tested using icEEG recordings from seven patients with medically refractory epilepsy. The icEEG recordings were assessed by the proposed CLNS and the predefined seizure suppression biphasic electrical stimulations were triggered ∼14.4 s after electrographical seizure onsets.

A low-power implantable device for epileptic seizure detection and neurostimulation

Conference Paper

Full-text available

Dec 2010

In this paper, we present the design of a low-power closed-loop neurostimulator (CLNS) as an adjunctive treatment for patients with refractory partial epilepsy. The CLNS combines epileptic seizure detection with simultaneous electrical stimulation feedback. The system amplifies the neural signal with adjustable gain, detects epileptic low-voltage fast-activity, and generates programmable stimulation currents. The implemented seizure detector is based on a detection algorithm validated in Matlab tools and was tested using intracerebral electroencephalographic (iEEG) recordings from a patient with drug-resistant epilepsy. The amplifier, epileptic-seizure detector and electric stimulator were implemented using CMOS 0.18-μm process. The iEEG were assessed by the proposed CMOS building blocks and the predefined seizure suppression biphasic electrical stimulations were administrated at 2 to 3 sec after electrographical seizure onsets. The simulated power consumption of the CLNS has showed that the system could run on a button cell battery for more than 8 years.

Optogenetic Activation of Normalization in Alert Macaque Visual Cortex

Article

Jun 2015
NEURON

Normalization has been proposed as a canonical computation that accounts for a variety of nonlinear neuronal response properties associated with sensory processing and higher cognitive functions. A key premise of normalization is that the excitability of a neuron is inversely proportional to the overall activity level of the network. We tested this by optogenetically activating excitatory neurons in alert macaque primary visual cortex and measuring changes in neuronal activity as a function of stimulation intensity, with or without variable-contrast visual stimulation. Optogenetic depolarization of excitatory neurons either facilitated or suppressed baseline activity, consistent with indirect recruitment of inhibitory networks. As predicted by the normalization model, neurons exhibited sub-additive responses to optogenetic and visual stimulation, which depended lawfully on stimulation intensity and luminance contrast. We conclude that the normalization computation persists even under the artificial conditions of optogenetic stimulation, underscoring the canonical nature of this form of neural computation. Copyright © 2015 Elsevier Inc. All rights reserved.

A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection

Article

Feb 2015

This paper presents a neural interface system-on-chip (SoC) featuring combined spike recording, electrical microstimulation, and real-time stimulus artifact rejection (SAR) for bidirectional interfacing with the nervous system. The SoC integrates a spike-recording front-end with input noise voltage of 3.42 mu V-rms (0.5 Hz-50 kHz), microstimulating back-end for delivering charge-balanced monophasic or asymmetric biphasic current pulses of < 100 mu A with passive discharge, and mu W-level digital signal processing (DSP) unit for real-time SAR based on template subtraction. The DSP unit initializes its embedded 16b, 4 K static random-access memory with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. Fabricated in AMS 0.35 mu m 2P/4M CMOS, the 3.1 x 3.1-mm(2) SoC has been characterized in benchtop tests and neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration up to similar to 115 ms from the contaminated neural data in real time and recover A mu V-range extracellular neural spikes that occur on the tail end of the artifacts. The average root-mean-square (rms) value of the pre-processed stimulus artifact is reduced by a factor of similar to 24-30 post-processing, with DSP unit power consumption of < 25 A mu W from 1.5 V.

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management

Article

Oct 2014

Although closed-loop deep brain stimulation (DBS) promises treatment of many neurological disorders, an implantable system-on-chip (SoC) implementing an effective closed-loop DBS algorithm has not been demonstrated. This work introduces a logarithmic, closed-loop DBS system that detects and processes low-frequency brain field signals to control and adapt stimulation currents. The system records and processes neural signals with four low-noise neural amplifier (LNA) channels, a multiplexed logarithmic ADC, and two high-pass and two low-pass digital logarithmic filters. Logarithmic processing saves power and achieves high dynamic range. A logarithmic domain digital signal processor (DSP) and PI-controller controls eight current stimulator channels and enables closed-loop stimulation. An RF transceiver, a clock generator, and a power harvester are also included in the system to achieve a complete implantable SoC. The 4 mm

^{2}

180 nm CMOS prototype consumes a total of 468 muW for recording and processing neural signals, for stimulation, and for two-way wireless communication.

Neurostimulation for the Treatment of Epilepsy: A Review of Current Surgical Interventions

Article

Sep 2012
NEUROMODULATION

Objectives: Epilepsy continues to provide challenges to clinicians, as a significant proportion of patients continue to suffer from seizures despite medical and surgical treatments. Neurostimulation has emerged as a new treatment modality that has the potential to improve quality of life and occasionally be curative for patients with medically refractory epilepsy who are not surgical candidates. In order to continue to advance the frontier of this field, it is imperative to have a firm grasp of the current body of knowledge. Methods: We performed a thorough review of the current literature regarding the three main modalities of vagus nerve stimulation, deep brain stimulation, and closed-loop stimulation (responsive neurostimulator [RNS]) for the treatment of refractory epilepsy. For each of these forms of treatment, we discuss the current understanding of the underlying mechanism of action, patient selection, outcomes to date, and associated side effects or adverse reactions. We also provide an overview of related ongoing clinical trials. Results: A total of 189 sources from 1938 to 2012 pertaining to neuromodulation for the treatment of epilepsy were reviewed. Sources included review articles, clinical trials, case reports, conference proceedings, animal studies, and government data bases. Conclusions: This review shows us how neurostimulation provides us with yet another tool with which to treat the complex disease of medically refractory epilepsy.