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Executable model based design methodology for fast prototyping of mobile network protocol: A case study on MIPI LLI
... En el presente trabajo se emplea una metodología similar a la planteada por Shah [15] (Figura 1), pues es utilizado ampliamente en la literatura descrita. A excepción de la primera etapa de la metodología, correspondiente al diseño en punto fijo del modelo, el resto de las etapas pueden ser acometidas dentro del flujo de trabajo del HDL Workflow Advisor. ...
Satellite broadcasting systems are an economical alternative for the deployment of television and other services in sparsely populated and difficult to access areas. This paper presents the modeling and hardware implementation of a DVB-S receiver according to the specifications contained in the EN 300 421 standard. The receiver is modeled and validated within the Simulink environment. From the validated model, an equivalent VHDL code is generated using the HDL Coder and HDL Verifier tools. Both Simulink synthesizable HDL modules and Xilinx Core Generator IP modules are used in the design for implementation and validation in a hardware environment, using the FPGA in the Loop tool. A comparison is made between implementation with native HDL blocks from the Simulink environment and the use of modules from the Xilinx platform.
Advanced driver assistance system (ADAS) performs an increasing improvement in active road safety and driving convenience. Controller Area Network (CAN) is now getting popular because of its expanding applications and widely utilizations in low-cost embedded systems from automation to medical industry. While implementing an effective and efficient mechanism for clock synchronization, serial operation causes the reduction of CAN transmission rate can have an adverse impact on the real-time applications of systems employing this protocol. Also, maintaining the reliability of this technology especially in safety services, a reliable system needs certain requirements like glitches management and troubleshooting in order to avoid certain occurrences of transmission error. In this paper we present a simulated Cyclic Redundancy Checking (CRC) encoder and decoder that perform high speed error detection for CAN using CRC-15. Digital Signal Processing (DSP) algorithms were used, namely pipelining, unfolding and retiming to attain the feasible iteration bound and critical path that is appropriate for CAN system. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL) from actual simulation to implementation of this CRC-15 for CAN system.
The design of complex digital signal processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory access constraints for the integration of dedicated hardware accelerators. Unfortunately, the traditional Matlab/Simulink design flows gather not very flexible hardware blocks. In this paper, we present a methodology and a tool that permit the high-level synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. The efficiency of our approach is demonstrated on the case study of an FFT algorithm.
In the last five years, the availability of powerful DSP and communications design software, and the emergence of relatively affordable devices that receive and digitize RF signals, has brought SDR to the desktops of many communications engineers. However, the more recent availability of very low cost SDR devices such as the RTL-SDR, costing less than $20, has brought SDR to the home desktops of undergraduate and graduate students, as well as professional engineers and the maker communities. Since the release of the various open source drivers for the RTL-SDR, many in the digital communications community have used this device to scan the RF spectrum and digitize I/Q signals that are being transmitted in the range 25 MHz to 1.75 GHz. This wide operating range enables the sampling of frequency bands containing signals such as FM radio, ISM signals, GSM, 3G and LTE mobile radio, GPS, and so on. In this article we will describe the opportunity and operation of the RTL-SDR, and the development of a handson, open-courseware for SDR. These educational materials can be integrated into core curriculum undergraduate and graduate courses, and will greatly enhance the teaching of DSP and communications theory, principles, and applications. The lab and teaching materials have recently been used in senior (fourth year undergraduate) courses and are available as open course materials for all to access, use, and evolve.
The paper deals with design and implementation of three phase Electromagnetic Interference phenomenon. A Harmonic passive filter has been proposed for the three phase electrical power system network. The Matlab Simulink analysis of the three phase EMI harmonic filter system is incorporated. The design and implementation of the filters are illustrated, with specific attention to the strict requirements of the given power supply application. The passive EMI, Harmonic filter is an attractive topology of power system. Factors such as the absence of harmonic, increased power density, reduced size and weight and good power quality are fundamental aspects of good design considerations. An improved control structure is proposed. This structure employs simple R, L, C elements in order to attenuate or eliminate the undesired harmonic distortion in the output waveforms in the power network. Proposed system having RLC filter is analyzed and verified by simulation. The indepth analysis of the input and output waveforms clearly indicate the constraints that need to be satisfied for successful operation of the proposed filter.
The paper deals with a solution for the compensation of a distorting regime from a distribution station for urban transport using a power active filter. Firstly the distorting regime is analyzed with a data acquisition system that provides the input data for the MATLAB/SIMULINK program used to size the active filter. The calculated parameters are afterward validated in MATLAB/SIMULINK. Experimental data obtained on stand validate the proposed solution.
Model based reference design projects with mathworks' HDL workflow advisor for custom-specific electronics with the Zedboard
- M Versen
- S Kipfelsberger
- F Sökmen
Synchronization in IEEE 802.15.4 Zigbee transceiver using Matlab Simulink
- K Gorantla
- V V Mani
Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms
- S Beek
- S Sharma