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Improved cryptanalysis of step-reduced SM3

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... For instance, in article [13], authors adopt the software/hardware co-design method to implement SM3, which is applied to the financial IC card. Moreover, the different optimized SM3 architecture and methods, such as the 3-stage pipeline approach, the parallel implementation strategy, the optimized architecture adopted the CSA adder, the implementation with the embedded ARM core, etc., are proposed [20][21][22][23][24][25]. Previous work promotes the development of SM3 VLSI architecture which has the characteristics of small hardware area and low power consumption. ...
... This solution is implemented in software and its throughput is not reported. In the work of [23], two different attacks on SM3 are introduced. The authors mainly studied the improvement of the resistance to attacks, but the internal details of the architecture were not reported, and thus we only discuss and compare the related implementation approaches. ...
... In [25], authors combine the implementation with the ARM processor to enhance the throughput. Because of lack of detailed data in [21][22][23], no direct comparison can be made with the work. ...
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Preimage attacks on stepreduced SM3 hash function
  • J Wu
  • W Wu