DC link capacitor voltage balancing of a dual three-level T-type AC drive using switching state redundancy

Full text

DC Link Capacitor Voltage Balancing of a Dual
Three-Level T-Type AC Drive Using Switching
State Redundancy.
A. Salem*§, F. De Belie†, T. Youssef ‡§ , J. Melkebeek†, O. Mohamad‡, and M. A. Abido*
*Electrical Engineering Department, King Fahd University for Petroleum & Minerals, Dhahran, KSA
†Electrical Energy System & Automation Department, EELAB, Ghent University, Belgium
‡Energy Systems Research Laboratory, ECE Department, Florida International University, Miami, Florida, USA
§Electrical Power & Machines Department, Helwan University, Cairo, Egypt
Abstract—Multilevel converters, which are supplied by cas-
caded capacitors and non-isolated DC sources, can not operate
without capacitor voltage balancing. This paper proposes a
capacitor voltage balancing technique for the dual three-level
T-type advanced converter topology. The reason behind the
capacitor voltage unbalance, of this topology, is discussed and
clarified by using the converter power circuit connected to an
open-end three-phase load. The converter switching states are
studied and classified to three different groups according to
their effect on the capacitor balancing. The proposed capacitor
balancing algorithm is implemented based on switching state
redundancy. This algorithm was tested both by simulation
through Matlab/Simulink as well as experimentally using a field
programmable gate-array digital controller and applied to a dual
three-level T-type converter AC drive system. The simulation
and the experimental results were compared and analysed. Both
the simulation and the experimental results are in agreement
verifying the proposed algorithm.
Index Terms—Multilevel converter, DC link capacitor balanc-
ing, SVPWM, redundant switching states.
I. INTRODUCTION
Multilevel converters are preferred in high-power applica-
tions thanks to the low harmonic content of their generated
output waveforms. The most popular topologies of multilevel
converters are the diode-clamped converter (DCC), the flying
capacitor converter (FCC), and the cascaded H-bridge (CHB)
converter. Each one of these converters has its own merits
and demerits [1]–[3]. In the DCC and FCC, capacitors are
supplied by splitting a single DC bus voltage using capacitor
banks. Although multilevel converters are preferred thanks to
low harmonic contents and supporting high power and voltage
levels, the DC link capacitor balancing of these converters is
considered one of the main drawbacks. This problem can be
solved in two different ways 1) by adding an auxiliary circuit
to transfer energy between capacitors as introduced in [4],
[5], or 2) by using PWM techniques to balance the capacitor
voltages as discussed in [6]–[18]. The first adds hardware
to the converter circuit in order to grantee the capacitor
balancing. This added hardware increases the converter size
as well as the converter losses as described in [19]. In [4],
three different auxiliary circuits are introduced to balance the
DC link capacitors of a modular DCC. These three circuits
are based on adding an auxiliary transformer supplied from an
additional passive inverter. In [5], an auxiliary circuit consists
of a buck and a boost converters is added to each switching
element of the NPC in order to balance the DC link capacitors.
PWM techniques, for three-phase multilevel converters,
offer a number of redundant switch states. These redundant
states can be used to balance the DC link capacitors. This
approach may minimize or eliminate the need for auxiliary
balancing circuits. However, the converter switching loss may
increase [19].
The T-type three-level converter is one of the advanced
DCC topologies, that has the advantages of lower number
of switching devices and higher efficiency compared to con-
ventional neutral point clamped (NPC) converters [20]–[23].
A dual three-level T-type converter (operate as a five-level
converter) has been studied in [24]. The capacitor balancing
for this converter topology is not studied yet as far as the
authors know.
The main target of this paper is to develop an algorithm to
balance the DC link capacitor voltages of the dual three-level
T-type converter by using space-vector pulse-width modulation
(SVPWM) redundant switching states. Hence, the proposed
topology is modelled and controlled by using SVPWM within
Matlab/Simulink program. A test-setup is implemented in
laboratory based on field programmable gate array (FPGA)
in order to validate the theoretical study.
This paper is organized as follows. In Section II, the
proposed converter operation and the implemented test-setup
are briefly described. Then, in Section III, the reason of the
DC link capacitor voltage unbalance of the proposed topology
is discussed. In Section IV, a complete study for the possible
switching states and their effect on the capacitor unbalance is
described. In Section V, the proposed control algorithm used
to balance the DC link capacitor voltages of the enhanced
converter topology is described. Section VI describes the
implemented test-setup used in this work.The simulation as
well as the experimental results are presented and discussed in
Section VII. Finally, the work conclusion is derived in Section
VIII.
II. PROPOSED SYSTEM
This section describes the proposed converter which has
the circuit diagram shown in Fig. 1. This system consists of
978-1-5090-4281-4/17/$31.00 ©2017 IEEE

Q1a'
C3
C4
P'
N'
O'
Q2a'
Q4a'
Q3a' Q3b' Q3c'
Q1b' Q1c'
Q4b'
Q4c'
Q2b'
Q2c'
A'
B'
C'
Q1a
C1
C2
P
N
O
Q2a
Q4a
Q3a Q3b Q3c
Q1b Q1c
Q4b
Q4c
Q2b
Q2c
A
B
C
Three-phase
open-ends IM
i1
ic1
i2
ic2
i'
1
ic3
ic4
i'
2
i'
3
i3
ia
ib
ic
Vdc/2
Vdc/2
idc1
idc2
Converte-1
Converte-2
Fig. 1. Dual T-type multilevel converter connected to a
three-phase OEWIM
a dual three-level T-type converter connected to an open-end
winding induction machine (OEWIM). The dual three-level
T-type converter possible switching states for phase UU′are
summarized in Table 1. There are nine different switching
states for phase UU′. Hence, the three-phases can operate with
93which are 729 switching states. For converter-1, to achieve
for phase U the voltage level of point-P, the switch Q3U should
be turned on. Another switching strategy is to turn on Q3U
and Q4U. The output voltage and the voltage stress of the
two switching strategies are the same. However, the switching
strategy which is listed in Table 1 reduces the number of
commutation of the two semiconductor switches Q2U and Q4U
as discussed in [25]. To deduce this high number of switching
states, a single T-type switching states and vector digram will
be presented firstly. The number of switching states for a single
three-level T-type converter is 27 ( listed in Table 2 and Table
3). In this paper, the switching state of the five-level proposed
converter will be two numbers i.e. K-Jwhere Krefers to the
converter-1 switching state, listed in Table 4, and Jrefers to
the switching state of converter-2. Each of Kand Ncan varies
between 1 to 27. Based on the proposed converter switching
states, the space vector can calculated by using (1) [26], [27].
V=2
3(vUU′+ ej2π/3.vVV′+ e–j2π/3.vWW′) (1)
The resultant vector diagram for the three-level T-type
converter is shown in Fig. 2. The topology of the dual three-
level T-type converter will obtain 729 switching states, which
are the square of the 27 switching states of each three-level
converter. By applying these switching states to the space
vector relation (1), the resultant vector diagram can described
as shown in Fig. 3. This vector diagram consists of 61 different
vectors, i.e. O, A1– A6,B1– B12, C1– C18, D1– D18.
a2
a3
a6
b1
b2
b3
b4
b5
b6
b7
b8
b9b10 b11
b12
Fig. 2. Vector diagram for a three-level T-type converter
Table 1: The possible switching states and the output voltage
for a single phase of a dual three-level T-type converter.
Converter-1 Converter-2 Connected points VUU′
Q3U, Q4U Q1U′, Q2U′P-N’ + Vdc
Q3U, Q4U Q4U′, Q2U′P-O’ + Vdc/2
Q2U, Q4U Q1U′, Q2U′O-N’
Q3U, Q4U Q3U′, Q4U′P-P’
Q2U, Q4U Q2U′, Q4U′O-O’ 0
Q1U, Q2U Q1U′, Q2U′N-N’
Q2U, Q4U Q3U′, Q4U′O-P’ - Vdc/2
Q1U, Q2U Q2U′, Q4U′N-O’
Q1U, Q2U Q3U′, Q4U′N-P’ - Vdc
Table 2: Three-level T-type converter switching states
state 1 2 3 4 5 6 7 8 9
U 0 0 0 0 0 0 0 0 0
V 0 0 0 1 1 1 2 2 2
W 0 1 2 0 1 2 0 1 2
vector O a5b9a3a4b8b5b6b7
state 10 11 12 13 14 15 16 17 18
U 1 1 1 1 1 1 1 1 1
V 0 0 0 1 1 1 2 2 2
W 0 1 2 0 1 2 0 1 2
vector a1a6b10 a2O a5b4a3a4
state 19 20 21 22 23 24 25 26 27
U 2 2 2 2 2 2 2 2 2
V 0 0 0 1 1 1 2 2 2
W 0 1 2 0 1 2 0 1 2
vector b1b12 b11 b2a1a6b3a2O
Table 3: Meaning of different switching states
Switch Q1U Q2U Q3U Q4U Obtained point
0 1 1 0 0 N
1 0 1 0 1 O
2 0 0 1 1 P
III. CAPACITOR VOLTAGE IMBALANCE INA DUAL
THREE-LEVEL T-TYPE CONVERTER TOPOLOGY
In this section, the reason behind the capacitor voltage
imbalance of the dual three-level T-type converter is discussed.
The problem comes from the fluctuation of the DC link mid-
points (O and O’ in Fig. 1). This fluctuation is a result of the
non-uniform switching across the series connected capacitors
which makes one capacitor carry a load current for larger
intervals compared to the other series connected capacitor. The
charging and discharging of the series connected capacitors
for similar intervals and currents can keep these capacitors
balanced.

C4
C7
C
C13 15 16
17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17 D18 D19 D20 D21
D22
D23
D24
Fig. 3. Vector diagram for a five-level dual T-type converter
An example for the capacitor unbalance is as follows. For
instance, assume a vector has a modulation index of 0.85
and an angle of 12o. By using the analysing this vector and
detecting its location in the vector diagram, it can be observed
that this vector is located in a region surrounded by the vectors
C1, C2and D2. The vectors C1and C2(Fig. 3) can be
obtained by the different switching states given in Table 4.
By selecting the state (10-9) to obtain vector C1followed
by the state (10-6) to obtain vector C2, the upper capacitor of
converter-1 DC link is charging during the intervals of the
two switching states. This results in discharging the lower
capacitor as shown in Fig. 4-a. If the switching state (23-
6) is selected instead of (10-6) to obtain the vector C2, the
upper capacitor will discharge and the lower capacitor will
charge as shown in Fig. 4-b. This example shows how the
switching state selection affects the capacitor voltage. The
selection from the redundant switching states is the base of
the capacitor balancing algorithm which will be discussed in
details in Section V.
IV. SWITCHING STATES EFFECTS ON CAPACITOR
VOLTAGE BALANCING
To realise capacitor balancing, the converter switching states
(729 switching states) are analysed to show their effects on the
capacitor voltages. By analysing the vector diagram, of Fig. 3,
and its corresponding switching states, it is observed that the
’A’ vectors can be achieved by 216 switching states, the set of
Table 4: The possible switching states for
C1and C2vectors.
Vector C1C2
State 19 20 22 10 23 19 19 20 22 10 23 25 13 26 19 22
U 222122 2221221222
V 001010 0010121201
Conv.-1
W 010010 0100100100
State 5 6 8 9 9 18 2 3 5 6 6 8 9 9 15 18
U’000001 0000000011
V’112222 0011122212
Conv.-2
W’121222 1212212222
’B’ vectors can be achieved by 264 switching states, the set
of ’C’ vectors can be achieved by 156 switching states, and
the set of D vectors can be achieved by 48 switching states.
Therefore, the total number of switching states which produce
a non-zero vector is 684. The zero-vector O can be achieved
by 45 passive switching states. It is observed that the 729
switching states have three different effects on the capacitor
balancing.
Assume the voltage imbalance is ∆Vc=Vc1 –Vc2 for
converter-1 and is ∆V’c=V’c1 –V’c2 for converter-2. Ac-
cording to the imbalance value, the switching state effects can
be classified as follows:
•Major effect group, in which ∆Vcor ∆V’ctends to
1/2Vdc.
•Minor effect group, in which ∆Vcor ∆V’ctends to
1/4Vdc.
•No effect group, in which ∆Vcor ∆V’ctends to zero.
A summary for the 729 switching states effect is given in Table
5. This table shows that the vectors A, B, C and D have states
that can be classified as having major effects on the imbalance.
These major states can be used to change the capacitor statue
from charging to discharging or visa versa.
The following is an example illustrating the different
aforementioned effects based on circuit diagrams that describe
the DC link capacitors connection to a three-phase load. The
symmetrical connection of the midpoints of the two DC links
to the three-phase load keeps the capacitors in a balanced state.
Fig. 5-a, b and c show some balanced states where the current
flow from the midpoints of the two DC links to the connected
load is absent. Another balanced state is shown in Fig. 5-
d where the two DC links are in a symmetrical connection
with the three-phase load. In Fig. 5-e-i, the unsymmetrical
connection of the two DC links to the three-phase load causes
capacitor voltage imbalance.
C1C2
Vdes
Vector
Vdes
vc1(t)
vc2(t)
(a)
t
t
C1C2
Vdes
Vector
Vdes
vc1(t)
vc2(t)
(b)
t
t
Fig. 4. Effect of the switching state selection on the capacitor
charging for (a) unbalanced case and (b) balanced case.
Table 5: Vectors and corresponding switching states
classification
Vector O A’s B’s C’s D’s
No effect 45 - 132 - 24
Major effect - 216 84 156 24
Minor effect - - 48 - -

Vdc/2 O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
(i)
(d)
Vdc/2
O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
v'c1
+
-
v'c2
UU`
VV`
WW`
N'
Vdc/2
O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
(a) (b)
Vdc/2 O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
(c)
Vdc/2 O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
(e)
N
Vdc/2 O
P
vc2
+
-
vc1
+
-
Vdc/2
+
-
+
-
P`
N' (f)
Vdc/2 O
P
vc2
+
-
vc1
+
-
Vdc/2
+
-
+
-
P`
N'
(g)
Vdc/2 O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
Vdc/2 O
P
N
vc2
+
-
vc1
+
-
Vdc/2
O`
P`
+
-
+
-
N'
(h)
v'c1
v'c2
v'c1
v'c2
v'c1
v'c2
v'c2
v'c1
v'c2
v'c1
v'c1
v'c2
v'c2
v'c2
v'c1
v'c1
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
UU`
VV`
WW`
Fig. 5. Converter power-circuit for different group-effect; no
effect group cases are [a, b, c, d], major effect group cases
are [e, f, g] and minor effect group cases are [h, i].
V. CAPACITOR BALANCING ALGORITHM
The strategy for the redundant switching state selection is
shown in Fig. 6 and summarised as follows. The capacitor
balancing procedure is based on a comparison between the
voltage imbalance ∆Vc,∆V’cand an acceptable imbalance
band (-∆V:∆V). This comparison results in 9 different possi-
ble cases as listed in Table 6. After determining the imbalance
case, the algorithm selects the proper redundant switching
states to balance the DC link capacitors. It is important to note
that not all of vectors have the different nine cases in order to
select between them. However, this algorithm is implemented
to select the most suitable case even if the optimum case is
absent. Also, it is worthy to note that the proposed algorithm
will not affect the switching frequency of the SVPWM tech-
nique. This results from that the proposed algorithm checks
the capacitor voltages and only change the switching states
at the normal state transitions. This proposed algorithm has
been tested and implemented on FPGA digital controller as
will be discussed later in this article. The following section
describes the hardware test-setup that has been implemented
in laboratory.
Table 6: Voltage imbalance cases
Comparison ∆Vc≥∆V∆V≥∆Vc≥-∆V∆Vc≤-∆V
∆V’c≥∆V Case-1 Case-2 Case-3
∆V≥∆V’c≥-∆V Case-4 Case-5 Case-6
∆V’c≤-∆V Case-7 Case-8 Case-9
Fig. 6. A flow chart for the capacitor balancing algorithm
VI. HARDWARE DESCRIPTION
A test-setup for a dual three-level T-type converter, shown
in Fig. 7, is implemented based on IXKR 40N60C discrete
MOSFETs. The converter is loaded by a three-phase OEWIM
which has the parameters in Appendix A. This IM is me-
chanically coupled to a DC machine in order to measure the
performance of the system at full-load condition. The converter
is supplied from two rectifiers which are supplied from two
isolated AC sources to prevent the zero-sequence current flow
in the machine phases. The output of each rectifier is splinted
by two capacitors. The capacitor balancing algorithm, based
SVPWM redundant switching states, is implemented on an
FPGA type VERTIX2. This digital controller is preferred
here as the required I/O-pins for PWM include 24 chan-
nels, while most DSPs have a lower number of I/O-pins
assigned for PWM channels and for digital I/O channels.
Moreover, the FPGA has the advantage of performing parallel
computations and sharing resources which results in a high

T-type
converter-2
T-type
converter-1
+
Vc2
-
P
N
O
+Vdc/2 -
idc1
+
Vc1
-
Ca
Cb
v
v
v
v
P'
N'
O'
idc2
+
Vc1'
-
+
Vc2'
-
Ca'
Cb'
U
V
WOEWIM
U'
V'
W'
Variable
R-load
Coupling
DC Machine
+
Va
-
v
v
v
Adjustable
dc power
supply
Differential
measuring
circuits
VIRTEX-II PRO
FPGA
ADC and
isolation
cicuits
AC supply
Single-phase of a
12-winding transformer
190-190/140-140
-Vdc/2+
Fig. 7. Dual T-type multilevel converter
number of operations each clock cycle. Differential voltage
measuring units, with high slew rate (500V/µs), are designed
and implemented to accurately measure the voltage signals.
The DC side voltages are measured and interfaced to the
FPGA controller in order to perform the capacitor balancing.
ADC modules, followed by an isolation stage, have been used
in order to converter analogue measured voltage signals to
digital values and transfer these signals to FPGA. Once FPGA
receives the voltage signals, it delivers the proper switching
state based on the capacitor balancing algorithm. Then, the
FPGA delivers the steering pulses to the converter drivers in
order to operate the proposed converter. The following sections
describes the simulation and the experimental results for the
proposed system.
VII. RESULTS AND DISCUSSION
To test the capacitor voltage balancing algorithm, it is
assumed to start the connected OEWIM by a variable DC
link voltage. This may not be the best way to start the IM, but
this test is carried out in order to show how the algorithm can
follow the desired reference voltage. Two variable DC sources
are used to supply the dual converter DC links. The desired
voltage is assumed to have steps of 20%, 40%, 60%, 80% and
100% of the desired steady state voltage 1/4Vdc.
Firstly, an open-loop SVPWM is applied to the proposed
converter without considering the capacitor balancing algo-
rithm to show the unbalance effect of the capacitor voltages on
the converter output and on the connected load. Fig. 8 shows
the capacitor voltages for the converter-1 DC link, wherein
the upper graph shows the two capacitor voltages compared
to the desired capacitor voltage, and the lower graph shows the
difference between these two capacitor voltages. This figure
shows that a high value voltage unbalance is resulted. The
corresponding voltages for the converter-2 DC link are shown
in Fig. 9. Fig. 10-a shows the output phase voltage during
0 0.5 1 1.5 2 2.5 3 3.5
0
50
100
150
t [s]
vc1, vc2 [V]
(a) Converter-1 DC link capacitor voltages compared to Vdesired
0 0.5 1 1.5 2 2.5 3 3.5
-100
-50
0
50
100
t [s]
∆V [V]
(b) Voltage imbalance in converter-1 DC link
vc2
vc1
Vdesired
Fig. 8. Simulated results for converter-1 DC link capacitor
voltages and imbalance voltage in an unbalanced case
0 0.5 1 1.5 2 2.5 3 3.5
0
50
100
150
t [s]
v′c1, v′c2 [V]
(a) Converter-2 DC link capacitor voltages compared to Vdesired
0 0.5 1 1.5 2 2.5 3 3.5
-100
-50
0
50
100
t [s]
∆V′ [V]
(b) Voltage imbalance in converter-2 DC link
v’c2
v’c1
Vdesired
Fig. 9. Simulated results for converter-2 DC link capacitor
voltages and imbalance voltage in an unbalanced case
the different voltage steps (20% - 100% of 1/4Vdc), while the
voltage at steady state is shown in Fig. 10-b. The voltage levels
are distorted as a result of the capacitor voltage unbalance. The
corresponding machine current from the starting instant till the
steady operation is shown in Fig. 11-a, while the steady state
current is shown in Fig. 11-b. The current looks distorted as
well as the phase voltage. The motor torque and speed for this
case study are shown in Fig. 12. The torque ripples are high
as a result of the distorted current.
By applying the capacitor balancing algorithm to the dual
three-level T-type converter, the simulation results can be
summarised as follows. Fig. 13 shows the capacitor voltages
for converter-1 DC link, wherein the upper graph shows
the two capacitor voltages and the lower graph shows the
difference between these two voltages. The figure clarifies how
the capacitor voltages are balanced. A small voltage difference
between the two series capacitors is shown in Fig. 13-b. The
corresponding voltages for converter-2 DC link are shown in
Fig. 14. The phase voltage from the starting instant till the
steady state is shown in Fig. 15-a, while the steady state
voltage is shown in Fig. 15-b. The voltage levels appeared right
(17 voltage levels in the phase voltage). The corresponding

0 0.5 1 1.5 2 2.5 3 3.5
-200
0
200
t[s]
vUU′[V]
3.44 3.45 3.46 3.47 3.48 3.49 3.5
-200
0
200
t[s]
vUU′[V]
(b) Steady-state phase voltage
(a) Phase voltage from starting to steady state using variable DC link
Fig. 10. Simulated results for phase voltage in an unbalanced
case
0 0.5 1 1.5 2 2.5 3 3.5
-40
-20
0
20
40
t[s]
iU[A]
3.44 3.45 3.46 3.47 3.48 3.49 3.5
-10
0
10
t[s]
iU[A]
(a) Current from starting to steady state using variable DC link
(b)
Fig. 11. Simulated results for phase current in an unbalanced
case
0 0.5 1 1.5 2 2.5 3 3.5
0
10
20
30
40
t [s]
T [N.m.]
0 0.5 1 1.5 2 2.5 3 3.5
0
500
1000
1500
t [s]
Speed [RPM]
10
12
Steady state torque ripples
Telectrical
Tload
(a) Machine and load torque
(b) Machine speed
Fig. 12. Simulated results for machine torque and speed in
an unbalanced case
machine current from the starting instant till the steady state
is shown in Fig. 16-a, while the steady state current is shown
in Fig. 16-b. The current looks ripple free. The motor torque
and speed for the balanced case study are shown in Fig. 17.
The steady state torque ripple is lower than the corresponding
torque ripple during the unbalanced case. This indicates that
the current ripple here is lower than in the unbalanced case.
0 0.5 1 1.5 2 2.5 3 3.5
0
50
100
t [s]
vc1, vc2 [V]
0 0.5 1 1.5 2 2.5 3 3.5
-10
0
10
t [s]
∆V [V]
3.48 3.5
60
80
vc2 vc1
(a) Converter-1 DC link capacitor voltages
(b) Voltage imbalance in converter-1 DC link
Fig. 13. Simulated results for converter-1 DC link capacitor
voltages and imbalance voltage in a balanced case
0 0.5 1 1.5 2 2.5 3 3.5
0
50
100
t [s]
v′c1, v′c2 [V]
0 0.5 1 1.5 2 2.5 3 3.5
-10
0
10
t [s]
∆V′ [V]
3.48 3.5
60
80
v′c2 v′c1
(b) Voltage imbalance in converter-2 DC link
(a) Converter-2 DC link capacitor voltages
Fig. 14. Simulated results for converter-2 DC link capacitor
voltages and imbalance voltage in a balanced case
0 0.5 1 1.5 2 2.5 3 3.5
-200
-100
0
100
200
t [s]
vUU′ [V]
3.44 3.45 3.46 3.47 3.48 3.49 3.5
-200
-100
0
100
200
t [s]
vUU′ [V]
(a) Phase voltage from starting to steady state using a variable DC link
(b) Steady-state phase voltage
Fig. 15. Simulated results for phase voltage in a balanced
case
Another test is performed by starting the converter
operation with a different pre-charged capacitor voltages. The
algorithm succeeded to balance the capacitor voltages as
shown in Fig. 18. The upper graph of this figure shows the four
capacitor voltages and the lower graph shows the case index
which selects the switching state case (from case 1- case 9).

0 0.5 1 1.5 2 2.5 3 3.5
-40
-20
0
20
40
t [s]
iU [A]
(a) Current from starting till steady-state using a variable DC link
3.44 3.45 3.46 3.47 3.48 3.49 3.5
-10
0
10
t [s]
iU [A]
(b) Current at steady state
Fig. 16. Simulated results for machine current in a balanced
case.
0 0.5 1 1.5 2 2.5 3 3.5
0
10
20
30
t [s]
T [N.m.]
0 0.5 1 1.5 2 2.5 3 3.5
0
500
1000
1500
t [s]
Speed [RPM]
10
12
Steady state torque ripple
TElectrical
Tload
(b) Machine speed
(a) Machine and load torque
Fig. 17. Simulated results for machine torque and speed in a
balanced case
0 0.05 0.1 0.15 0.2
40
60
80
100
120
t[S]
Capacitor voltages [V]
0 0.05 0.1 0.15 0.2
0
5
10
t[S]
Case index
vc1 vc2 v'
c1 v'
c2
(a) Capacitor voltages at the case study of different pre-charged voltages
(b) Case index variation
Fig. 18. Capacitor voltages at different pre-charging voltage
values and the corresponding case index.
For the experiments of this study, the results at the steady
state of the full-load operation of the IM can be described
as follows. The capacitor voltages for converter-1 DC link
are shown in Fig. 19-a, while the voltage difference ∆Vcis
shown in Fig. 19-b. The corresponding voltages for converter-
2 DC link are shown in Fig. 20. These figures show that the
capacitor voltages are following the reference voltage (which
is 72 V in this study). A small difference between the two
0 0.005 0.01 0.015 0.02
0
50
100
t[s]
vC1, vC2 [ ]
0 0.005 0.01 0.015 0.02
-10
-5
0
5
10
t[s]
∆VC[ ]
0.01 0.012
0
0
vC1 vC2
(a) Converter- ges
(b) Converter- voltage
Fig. 19. Measurements of Converter-1 DC link capacitor
voltages, and the voltage imbalance ∆Vc
0 0.005 0.01 0.015 0.02
0
50
100
t[s]
v′
C1, v′
C2 [ ]
0 0.005 0.01 0.015 0.02
-10
-5
0
5
10
t[s]
V′
C[ ]
v′
C1 v′
C2
0.01 0.012
0
0
(a) Converter- ges
(b) Converter- voltage
Fig. 20. Measurements of Converter-2 DC link capacitor
voltages, and the voltage imbalance ∆Vc
0 0.005 0.01 0.015 0.02
-200
0
200
(a) Measured phase voltage at a balanced case
t [s]
vUU′ [V]
0 0.005 0.01 0.015 0.02
-10
0
10
t [s]
iU [A]
(b) Measured phase currenr at a balanced case
Fig. 21. Measurements at a balanced case (a) phase voltage,
(b) phase current
series capacitors is observed and is within the band limit
(–∆V : ∆V). The measured phase voltage and current at
this balanced case are shown in Fig. 21. The measurements
indicate that the capacitor voltage balancing algorithm is
working properly and validate the theoretical study.

VIII. CONCLUSION
The capacitor balancing for a dual three-level T-type
converter has been presented in this paper. The converter
switching states using SVPWM has been analysed and
classified into three different groups according to their effect
on the capacitor balancing. The major effective group is
used in order to balance the capacitor voltages. A capacitor
balancing algorithm has been introduced, discussed and
implemented based on the switching state redundancy. This
algorithm is applied to the proposed converter while supplying
an OEWIM at full load condition. The algorithm is tested
both theoretically and experimentally. The simulation and the
experimental results are well agreed. The study showed that
the algorithm is succeeded to balance the DC link capacitor
voltages and followed the reference voltage well. The study
shows also that the algorithm is working properly even when
the DC link capacitors are pre-charged by different voltage
values. Finally, the study reflected the validity of using this
capacitor balancing algorithm for the dual three-level T-type
converter in AC drive application.
APPENDIX A
INDUCTION MACHINE PARAMETERS
Parameters of a 2 HP, 200 V, 50 Hz, four poles IM.
rs= 1.11 Ω, rr=1.03Ω, Lls = Llr = 0.0903 H Lm= 0.0851 H,
J = 0.089 kg/m2
ACKNOWLEDGMENT
Dr. A. Salem and Dr. M. A. Abido would like to ac-
knowledge the support provided by the deanship of scientific
research, King Fahd University of Petrol & Minerals through
the power research group funded project RG1420- 1&2.
REFERENCES
[1] A. M. Ghias, et al. " Voltage Balancing Method Using Phase-Shifted
PWM for the Flying Capacitor Multilevel Converter." IEEE transaction
on Power Electron., vol. 29, no. 9, pp. 4521 – 4531, Sept. 2014.
[2] A. M. Ghias, et al. " Initial Capacitor Charging in Grid-Connected Flying
Capacitor Multilevel Converters." IEEE transaction on Power Electron.,
vol. 29, no. 7, pp. 3245 – 3249, July 2014.
[3] F Salinas, et al. " Voltage Balancing Scheme for Flying Capacitor
Multilevel Converters ." Power Electronics, IET, vol. 6, no. 5, pp. 835 –
842, 2013.
[4] Gao, Congzhe, et al. "A dc-link voltage self-balance method for a diode-
clamped modular multilevel converter with minimum number of voltage
sensors." Power Electronics, IEEE Transactions on vol. 28, no. 5, pp.
2125-2139, 2013.
[5] , Von Jouanne, Annette, Shaoan Dai, and Haoran Zhang. "A multilevel in-
verter approach providing DC-link balancing, ride-through enhancement,
and common-mode voltage elimination." Industrial Electronics, IEEE
Transactions on, vol. 49, no. 4, pp. 739 – 745, 2002.
[6] Sharifzadeh, Mohammad, et al. "Hybrid SHM-SHE Modulation Tech-
nique for Four-Leg NPC Inverter with DC Capacitors Self-Voltage-
Balancing." Industrial Electronics, IEEE Transactions on, vol. 62, no.
8, pp. 4890 – 4899, 2015.
[7] Yazdani, Amirnaser, and Reza Iravani. "A neutral-point clamped con-
verter system for direct-drive variable-speed wind power unit." Energy
Conversion, IEEE Transactions, vol. 21, no. 2, pp. 596 – 607, 2006.
[8] Pou, Josep, Rafael Pindado, and Dushan Boroyevich. "Voltage-balance
limits in four-level diode-clamped converters with passive front ends."
Industrial Electronics, IEEE Transactions on, vol. 52, no. 1, pp. 190-
196, 2005.
[9] Kanchan, R. S., P. N. Tekwani, and K. Gopakumar. "Three-level inverter
scheme with common mode voltage elimination and dc-link capacitor
voltage balancing for an open end winding induction motor drive."
Electric Machines and Drives IEEE International Conference on, pp.
1445-1452. IEEE, 2005.
[10] Wang, Kui, Zedong Zheng, Lie Xu, and Yongdong Li. "A Four-level
Hybrid-Clamped Converter With Natural Capacitor Voltage Balancing
Ability." Power Electronics, IEEE Transactions on, vol. 29, no. 3, pp.
1152 – 1162, 2014.
[11] Ghias, Amer MYM, Josep Pou, Mihai Ciobotaru, and Vassilios Georgios
Agelidis. "Voltage-balancing method using phase-shifted PWM for the
flying capacitor multilevel converter." Power Electronics, IEEE Transac-
tions on, vol. 29, no. 9, pp. 4521 – 4531, 2014.
[12] Amini, Jalal. "An Effortless Space-Vector-Based Modulation for-level
Flying Capacitor Multilevel Inverter With Capacitor Voltage Balancing
Capability." Power Electronics, IEEE Transactions on, vol. 29, no. 11,
pp. 6188 – 6195, 2014.
[13] Saeedifard, Maryam, Reza Iravani, and Josep Pou. "Analysis and control
of DC-capacitor-voltage-drift phenomenon of a passive front-end five-
level converter." Industrial Electronics, IEEE Transactions on, vol. 54,
no. 6, pp. 3255 – 3266, 2007.
[14] Bendre, Ashish, Giri Venkataramanan, Don Rosene, and Vijay Srini-
vasan. "Modeling and design of a neutral-point voltage regulator for
a three-level diode-clamped inverter using multiple-carrier modulation."
Industrial Electronics, IEEE Transactions on, vol. 53, no. 3, pp. 718 –
726, 2006.
[15] Celanovic, Nikola, and Dushan Boroyevich. "A comprehensive study
of neutral-point voltage balancing problem in three-level neutral-point-
clamped voltage source PWM inverters." Power Electronics, IEEE Trans-
actions on, vol. 15, no. 2, pp. 242 – 249, 2000.
[16] Pou, Josep, Rafael Pindado, Dushan Boroyevich, and Pedro Rodriguez.
"Evaluation of the low-frequency neutral-point voltage oscillations in the
three-level inverter." Industrial Electronics, IEEE Transactions on, vol.
52, no. 6, pp. 1582 – 1588, 2005.
[17] Bouhali, O., B. Francois, E. M. Berkouk, and C. A. S. C. Saudemont.
"DC link capacitor voltage balancing in a three-phase diode clamped
inverter controlled by a direct space vector of line-to-line voltages." Power
Electronics, IEEE Transactions on, vol. 22, no. 5, pp. 1636 – 1648, 2007.
[18] Yamanaka, Katsutoshi, Ahmet M. Hava, Hiroshi Kirino, Yoshiyuki
Tanaka, Noritaka Koga, and Tsuneo Kume. "A novel neutral point
potential stabilization technique using the information of output current
polarities and voltage vector." Industry Applications, IEEE Transactions
on, vol. 38, no. 6, pp. 1572 – 1580, 2002.
[19] Adam, Grain P., Stephen J. Finney, Ahmed M. Massoud, and Barry
W. Williams. "Capacitor balance issues of the diode-clamped multilevel
inverter operated in a quasi two-state mode." Industrial Electronics, IEEE
Transactions on, vol. 55, no. 8, pp. 3088 – 3099, 2008.
[20] M. Schweizer, et al. " Design and implementation of a highly efficient
three-level T-type converter for low-voltage applications." IEEE Trans.
on Power Electron., vol. 28, no. 2, pp. 899 – 907, Feb. 2013.
[21] M. Schweizer, et al. " High efficiency drive system with 3-level T-type
inverter." Power Electronics and Applications (EPE 2011), Proceedings
of the 2011-14th European Conference on., pp. 1 5 – 10, Birmingham,
2011.
[22] T. B. Soeiro, et al. " The New High-Efficiency Hybrid Neutral-Point-
Clamped Converter." IEEE Trans. on Ind. Electron., vol. 60, no. 5, pp.
1919 – 1935, May 3013.
[23] T. B. Soeiro, et al. " Comparison of 2-and 3-level active filters with
enhanced bridge-leg loss distribution." Power Electronics and ECCE Asia
(ICPE & ECCE), 2011 IEEE 8th International Conference on, pp. 1835
– 1842, Jeju, 2011.
[24] A. Salem, F. D. Belie, et al. "Evaluation of a dual-T-type converter sup-
plying an open-end winding induction machine." Industrial Electronics
Society, IECON 2013-39th Annual Conference of the IEEE..pp. 749 – 754
Vienna, 2013.
[25] A. Salem, "Design and analysis of five-level T-type power converters
for rotating field drives", Doctoral dissertation, Ghent University, 2015.
[26] Holmes, D.G., Lipo, T.A.," Pulse Width Modulation for Power Convert-
ers: Principles and Practice," Book, USA: Wiley-IEEE Press, John Willy
and Sons, Inc., Oct. 2003
[27] B. K. Bose, " Modern power electronics and AC drives " , vol. 123.
USA: Prentice Hall, 2002.