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Evidence of Hot-Electron Effects during Hard Switching of AlGaN/GaN HEMTs
Abstract
This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic RON increase when they are submitted to soft switching up to VDS= 600 V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic-RON). The increase in dynamic RON induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in RON is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic RON becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.
... This is consistent with the increased free carrier's concentration. This confirms once again the involvement of hot electrons and can further help in the understanding of underlying physics [31]. To this end, a relevant indication is provided by the transients shown in Figure 16. ...
... This is consistent with the increased free carrier's concentration. This confirms once again the involvement of hot electrons and can further help in the understanding of underlying physics [31]. To this end, a relevant indication is provided by the transients shown in Figure 16. Figure 16. ...
In this paper, a new method for evaluating hot-electron degradation in p-GaN gate AlGaN/GaN power HEMTs is proposed. The method exploits a commercial parameter analyzer to study VTH and RON drifts induced by on-state stress at VDS = 50 V. The results show that VTH drift and part of the RON degradation induced by the on-state stress are recoverable and likely due to the ionization of C-related acceptors in the buffer. This was confirmed by a preliminary characterization of C-related buffer traps. Conversely, the remaining part of RON degradation (not recovered in 1000 s) was strongly affected by the surface treatment. The current level set during on-state stress affected the amount of non-recoverable degradation, confirming the involvement of hot electrons. Thanks to the monitoring of the parameters’ recovery, the proposed method provides important insights into the physical mechanisms governing the parameters’ degradation. This extends the capabilities of state-of-the art systems, without the need for custom setup development.
... The HEMT GaN transistor has several advantages over its silicon counterpart in power applications where high efficiency, high power density, and high frequency are important. However, its functional reliability is still a concern for some even though significant results have been obtained in hard switching regimes in [1] [2]. To extend the functional reliability of the p-GaN HEMT from a use within its nominal ratings to overload regimes (near or just above its maximum ratings), a no-loaded halfbridge inverter topology is considered in this study. ...
... The current and high electric field distribution might alter the GaN layer quality through the emission of hot electrons that transfer energy to the lattice and change its quality as the stress is an aggravated semi-ON/Hard switching stress [2]. The high VDS chosen in the stress of boards #1-5 eases this location degradation compared to 67V stress. ...
The GaN HEMT power device emerges as a promising wide-bandgap component for obtaining ultra-compact and very high efficiency power converters. Nevertheless, its long-time switching operation capability in high overload regimes near or just above its maximum ratings remains unknown. The physical degradation mechanisms specific to GaN HEMT as well as the associated electrical signatures must now be established and better understood. In this article a stress protocol is proposed combining or not functional drain-source over-voltage switching and transient low dead-time cross-conduction stresses. A no-loaded Half Bridge (HB) is used. All stress parameters studied have been associated to electric changes such as drain-source, gate-source leakage currents, and threshold voltage drifts of intrinsic values and even some physical degradation by LIT compound analysis. After analysis, it appears that both the electric field and the current are very stressful for the devices and lead to current leakage caused by physical degradation. The aging observed might be generated from the injection of hot electrons and located depending upon the drain voltage value which influences the depletion region and thus the electric field peak. DOI : 10.1016/j.microrel.2023.115172
... EL signal detected during DGD pulse measurement from 0.4 to −1 µs[28] 图 6. DGD 从 0.4 到−1 µs 脉冲测量过程中检测到的 EL 信号[28] 2.4. 锁相锁定红外热成像(LIT)LIT 是在 GaN HEMT 器件中用于观察内部缺陷位置和局部热量的有力工具[29] [30]。 LIT 以脉冲式电 信号的形式对被测器件应用定期热激发，然后使用热成像摄像机监测温度变化。高灵敏度红外摄像机(光 谱范围 3~5 μm)能够捕捉器件表面产生的热响应，锁定过程可以记录热响应的幅值和相位信号，再通过对 多个周期进行微积分可以获得非常高的信号噪音比。 这种信号能够使 LIT 具有高空间分辨率(高达 1.5 μm) 和高热灵敏度(几 μK)，满足观察缺陷位置的要求[31]。当泄露路径或者缺陷部位局部电阻率增加时，PEM 不能直接显示出局部电阻率在增加，而高分辨率的 LIT 可以测量电流流动产生的局部热量，显示电阻率 安蒙恩，修慧欣 DOI: 10.12677/app.2023.136032 ...
... EL signal detected during DGD pulse measurement from 0.4 to −1 µs[28] 图 6. DGD 从 0.4 到−1 µs 脉冲测量过程中检测到的 EL 信号[28] 2.4. 锁相锁定红外热成像(LIT)LIT 是在 GaN HEMT 器件中用于观察内部缺陷位置和局部热量的有力工具[29] [30]。 LIT 以脉冲式电 信号的形式对被测器件应用定期热激发，然后使用热成像摄像机监测温度变化。高灵敏度红外摄像机(光 谱范围 3~5 μm)能够捕捉器件表面产生的热响应，锁定过程可以记录热响应的幅值和相位信号，再通过对 多个周期进行微积分可以获得非常高的信号噪音比。 这种信号能够使 LIT 具有高空间分辨率(高达 1.5 μm) 和高热灵敏度(几 μK)，满足观察缺陷位置的要求[31]。当泄露路径或者缺陷部位局部电阻率增加时，PEM 不能直接显示出局部电阻率在增加，而高分辨率的 LIT 可以测量电流流动产生的局部热量，显示电阻率 安蒙恩，修慧欣 DOI: 10.12677/app.2023.136032 ...
... Hard switching applied to a lateral GaN component, named High Mobility Transistor (HEMT), induces hot carriers in the 2DEG conductive channel [3][4] [5]. These hot carriers have a high probability of being trapped in the passivation layer of the component [6]. ...
... The DUT is not permanently under voltage, so the decrease in current in the anode after a cycle of switching is mainly due to hard switching. These findings were in agreement with the literature where it has been proved that hot-electron effects play a major role in the dynamic performance under hard switching [3]. Direct characterization has been applied to the diode to calculate the static resistance before and after stress. ...
... This sequence consisted of stressing the device with a drain voltage for 60 s while it was in the off state and then switching the device to the on state for two pulses of 200 µs, which were separated by an off state of 20 µs. These consecutive pulses that followed the voltage stress provided information about the main trappings, which were the trappings that were induced by the voltage stress and hot electron effects during the switching events [16,17]. For all tests, the drain voltage stress was 500 V, which represented a derating of 80% as it was fixed [18]. ...
... This sequenc of stressing the device with a drain voltage for 60 s while it was in the off sta switching the device to the on state for two pulses of 200 μs, which were sepa off state of 20 μs. These consecutive pulses that followed the voltage stress p formation about the main trappings, which were the trappings that were indu voltage stress and hot electron effects during the switching events [16,17]. For a drain voltage stress was 500 V, which represented a derating of 80% as it was For the electrical measurements, we used a 98 mΩ shunt resistor (SDN measure the current and a passive voltage probe (300 V and 500 MHz PP018 Lecroy, CA, USA) to measure the voltage. ...
Dynamic RON is a key parameter in terms of device reliability and the efficiency of power-switching converters. In this study, commercial off-the-shelf GaN-on-Si power high-electron-mobility transistors (HEMTs) were irradiated using different regimes of accumulative gamma rays with a ⁶⁰Co source of photon energy (1.33 MeV), while a base temperature of 53 °C and 133 °C during the irradiation test was applied. This test campaign had the objective of investigating how the combination of gamma irradiation and temperature affects dynamic on-resistance (RON) behaviour. The results indicated that gate voltage bias stress affected the degradation of dynamic on-resistance when irradiation was applied, and that temperature was an accelerating factor in dynamic on-resistance degradation. Finally, we obtained a partial reduction in dynamic RON when a total ionising dose of around 140 krad(SiO2) was applied and the base temperature during the irradiation test was not high.
... For instance, higher supply voltages (V DD ) can intensify electron trapping, leading to current collapse [18,19]. In particular, GaN-based transistors are highly sensitive to hard switching operation, which induces dynamic threshold voltage shifts and on-resistance degradation [20]. Similarly, as the operating frequency (f m ) increases, devices drain the current and the switching speed declines due to the dominance of trapping, resulting in degrading performances [21,22]. ...
The trapping mechanism at the AlGaN/GaN interface in the p-GaN high electron mobility transistors (HEMTs) and its impact on the turn-on characteristics of direct-coupled FET logic (DCFL) inverters were investigated across various supply voltages (VDD) and test frequencies (fm). The frequency-conductance method identified two trap states at the AlGaN/GaN interface (trap activation energy Ec-ET ranges from 0.345 eV to 0.363 eV and 0.438 eV to 0.47 eV). As VDD increased from 1.5 V to 5 V, the interface traps captured more electrons, increasing the channel resistance (Rchannel) and drift-region resistance (Rdrift) of the p-GaN HEMTs and raising the low-level voltage (VOL) from 0.56 V to 1.01 V. At fm = 1 kHz, sufficient trapping and de-trapping led to a delay of 220 µs and a VOL instability of 320 mV. Additionally, as fm increased from 1 kHz to 200 kHz, a positive shift in the threshold voltage of p-GaN HEMTs occurred due to the dominance of trapping. This shift caused VOL to rise from 1.02 V to 1.40 V and extended the fall time (tfall) from 153 ns to 1 µs. This investigation enhances the understanding of DCFL GaN inverters’ behaviors from the perspective of device physics on power switching applications.
... 7-9 During the hard-switching operations, the GaN devices undergo both high current and high voltage, resulting in the generation of hot electrons. 10,11 The hot electrons with high kinetic energy are more prone to scattering toward the surface layer and buffer layer, and continually bombard them, releasing the kinetic energy. Over an extended period of bombardment, newly generated defect/traps are formed in GaN power devices. ...
The hot-electron-related reliability is an important issue for GaN power devices under harsh operation condition or environment. These high-energy electrons can scatter toward the device surface or buffer layer, introducing newly generated traps/defects and resulting in the degradation of dynamic ON-resistance (RON). This work investigates the dynamic characteristics in active-passivation p-GaN gate HEMTs (AP-HEMTs) after hot-electron stress (HES). Unlike the dielectric passivation whose dynamic RON performance is often reported to severely worsen as hot-electron-induced defects/traps accumulate, the active passivation is found to have a superior robustness against hot-electron stress. In this study, after an HES of 30 min with VD = 200 V and IS = 10 mA/mm, the dynamic RON/static RON of a conventional HEMT increases dramatically from 3.63 to 9.35 for VDS-OFF = 650 V, whereas that of AP-HEMT only shows a slight increase from 1.51 to 1.85. Two mechanisms have been experimentally proved for the improved hot-electron robustness in AP-HEMT. (i) The mobile holes in active passivation layer can effectively screen the preexisting and/or newly generated surface defects/traps from affecting the 2DEG channel. (ii) The recovery of buffer trapping is accelerated by hole injection from gate and active passivation.
... Turn-off and turn-on timing measurements are then captured at the turning off of the first pulse and the turning on of the second pulse. This "double-pulse" technique only sends two pulses to the device, which is not periodically sustained, and the current in the third step is always higher than 0 A [28][29][30]. In order to fully obtain the characteristics of the periodic operation of the device in the high-frequency circuit, we make the device continuously work periodically and stably in the CCM or DCM state by controlling the L value and the V ds_off [31,32]. With the "double-pulse-current-mode" technique, we are able to focus on the impact of the starting current and peak current on the transition time of the device, which is not easy to do with the conventional "double-pulse" technique. ...
In this work, we present an analytical model of dynamic power losses for enhancement-mode AlGaN/GaN high-electron-mobility transistor power devices (eGaN HEMTs). To build this new model, the dynamic on-resistance (Rdson) is first accurately extracted via our extraction circuit based on a double-diode isolation (DDI) method using a high operating frequency of up to 1 MHz and a large drain voltage of up to 600 V; thus, the unique problem of an increase in the dynamic Rdson is presented. Then, the impact of the current operation mode on the on/off transition time is evaluated via a dual-pulse-current-mode test (DPCT), including a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM); thus, the transition time is revised for different current modes. Afterward, the discrepancy between the drain current and the real channel current is qualitative investigated using an external shunt capacitance (ESC) method; thus, the losses due to device parasitic capacitance are also taken into account. After these improvements, the dynamic model will be more compatible for eGaN HEMTs. Finally, the dynamic power losses calculated via this model are found to be in good agreement with the experimental results. Based on this model, we propose a superior solution with a quasi-resonant mode (QRM) to achieve lossless switching and accelerated switching speeds.
... These requirements can be met by the above for the past decades' work on transistors is processed to reduce the size of the transistor [22]. But too much reduction in the size of the transistor results increase in leakage current, increase in power dissipation losses [23], so hetero materials with high electron mobility are loosening to overcome the limitation of existing conventional transistors. Marino et al. [24] proposed HEMTs increase conductivity drain current (ID), trans conductance (gm), on resistance (Ron), and threshold voltage (Vth). ...
Advanced high electron mobility transistor (HEMT) with dual front gate, back gate with silicon nitride/aluminum oxide (Si3N4/Al2O3) as passivation layer, has been designed. The dependency on DC characteristics and radio frequency characteristics due to GaN cap layers, multi gate (FG and BG), and high K dielectric material is established. Further compared single gate (SG) passivated HEMT, double gate (DG) passivated HEMT, double gate triple (DGT) tooth passivated HEMT, high K dielectric front Pi gate (FG) and back Pi gate (BG) HEMT. It is observed that there is an increased drain current (Ion) of 5.92 (A/mm), low leakage current (Ioff) 5.54E-13 (A) of transconductance (Gm) of 3.71 (S/mm), drain conductance (Gd) of 1.769 (S/mm), Cutoff frequency (fT) of 743 GHz maximum oscillation frequency (Fmax) 765 GHz, minimum threshold voltage (Vth) of -4.5 V, on resistance (Ron) of 0.40 (Ohms) at Vgs=0 V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation high-speed GHz frequency applications.
... Reliability concerns of AlxGa1−xN/GaN HEMTs have been caused by trap effects related to a drain, gate lag, and current collapse with various types of degradation [11][12][13]. The AlGaN layer, which is usually the surface layer and has an interface with the GaN channel, is a source of reliability instability, including trapping in the gate-to-drain access region, deep-level, and AlxGa1−xN/GaN interface [14]. Although most surface traps can be passivated with different kinds of passivation layers (e.g., SiNx, SiO2, and Al2O3), optimization of the traps inside the AlxGa1−xN layer and the AlxGa1−xN/GaN interface is still an ongoing investigation. ...
In this study, we present a detailed analysis of trapping characteristics at the AlxGa1−xN/GaN interface of AlxGa1−xN/GaN high-electron-mobility transistors (HEMTs) with reliability assessments, demonstrating how the composition of the Al in the AlxGa1−xN barrier impacts the performance of the device. Reliability instability assessment in two different AlxGa1−xN/GaN HEMTs [x = 0.25, 0.45] using a single-pulse ID–VD characterization technique revealed higher drain-current degradation (∆ID) with pulse time for Al0.45Ga0.55N/GaN devices which correlates to the fast-transient charge-trapping in the defect sites near the interface of AlxGa1−xN/GaN. Constant voltage stress (CVS) measurement was used to analyze the charge-trapping phenomena of the channel carriers for long-term reliability testing. Al0.45Ga0.55N/GaN devices exhibited higher-threshold voltage shifting (∆VT) caused by stress electric fields, verifying the interfacial deterioration phenomenon. Defect sites near the interface of the AlGaN barrier responded to the stress electric fields and captured channel electrons—resulting in these charging effects that could be partially reversed using recovery voltages. The quantitative extraction of volume trap density (Nt) using 1/f low-frequency noise characterizations unveiled a 40% reduced Nt for the Al0.25Ga0.75N/GaN device, further verifying the higher trapping phenomena in the Al0.45Ga0.55N barrier caused by the rougher Al0.45Ga0.55N/GaN interface.
... The triple sense protocol can help establish the medium-and long-term impact of typical stressing elements known to degrade GaN HEMTs, such as static drain-source stress in the OFF state, or hard switching [25,30,31]. ...
The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage bias stress on both drain and gate.
... Next, we turn our focus to the application reliability needs for GaN FETs. Power conversion involves hard-switching transitions, which can be stressful on devices [167], [168]. For Si power FETs, a combination of technology and product-level tests is typically used to validate operational robustness, for example, unclamped inductive switching (UIS), hot carrier injection (HCI), and high-temperature operating life (HTOL). ...
This article provides an overview of power semiconductor devices (PSDs) for the distributed energy resource (DER) system. To begin with, an overview of electrically triggered silicon carbide (SiC) and gallium nitride (GaN) devices followed by a brief narration of ultrawide bandgap (UWBG) PSDs and, subsequently, an overview of optically activated PSDs encompassing photoconductive semiconductor switch (PCSS) and optical bipolar PSDs are provided. Finally, an overview of PSD packaging and reliability is captured.
... As mentioned, electrons need a certain amount of energy to be trapped. There are two main mechanisms that generate the required energy to get electrons trapped [43], [44], [49]. ...
Wide Bandgap (WBG) semiconductor materials present promising electrical and thermal characteristics for Power Electronics applications. This WBG devices make possible the development of more efficient converters with higher power densities. In contrast to Silicon Carbide (SiC) devices, Gallium Nitride (GaN) devices are several steps behind in terms of development, standardization and achievable power levels. This makes more challenging the use and integration of these devices in real power applications. Commercially available current Power GaN devices are based on lateral normally ON HEMT transistors. In order to get normally OFF power transistors, two transistor structures have been proposed: enhancement mode (e-mode) and hybrid transistors. Current E-mode transistors present a low gate threshold voltage which could lead to crosstalk problems. In contrast, hybrid transistors have higher gate threshold voltages, however, the use of a Silicon MOSFET in their structure limits their performance. The lack of a standard power GaN device makes difficult the adoption of these promising devices by the industry. Thus, in order to make easier the adoption of these power GaN devices, this paper presents a State of the Art of power Gallium Nitride devices focusing on their structures, basics and gate terminal requirements.
... This is repeated with a period T period for a xed quiescent bias and various measurement pulses. The gate and drain pulse alignment are in this work chosen such, that hard switching [34] or high current on state stress during the switching from the quiescent bias point to the pulsed state is avoided. A schematic waveform for an o-state quiescent point with negative gate voltage is shown in Fig. 2 FOMs for high frequency power applications is briey presented in the following. ...
In this work, a novel fully scalable source-connected field plate (FP) concept of GaN-on-Si HEMTs for high frequency applications is studied with the aid of device simulations and measurements. The device fabrication is enabled by an advanced CMOS compatible GaN-on-Si technology on 200 mm substrates. TCAD device simulations are established to support the novel field plate concept study. Furthermore, challenges related to the silicon substrate, in comparison to silicon carbide, are evaluated by measurements of substrate-related loss. Device simulations of GaN-on-Si HEMTs are set up for several electrical characteristics by comparing simulations with measurements. In particular, the velocity-field relationship is determined by measurements. Additionally, the bias dependence of the transistor capacitances is discussed and the FP pinch-off voltage is introduced. Furthermore, the effect of the FP pinch-off voltage on the gate-drain and drain-source capacitance is explained. The small-signal current gain and power gain are evaluated with device simulations as well as small-signal circuit simulations. Additionally, a novel TCAD based delay analysis of the cutoff frequency is presented. With the help of the established TCAD device simulations and measurements, the novel field plate concept is studied. First, the fundamental electrical device characteristics of GaN-on-Si HEMTs with deeply scaled field plate (DSFP) are discussed. In this work a measured small-signal power gain of 26.4 dB at 5.0 GHz is achieved using the deeply scaled field plate concept. To the best knowledge of the author, this is the highest reported value for single-gate GaN-on-Si metal-semiconductor HEMTs. Second, the influence of several transistor and field plate design variations on the electrical characteristics are presented showing the geometric scalability of this field plate concept. Third, the scalability of GaN-on-Si HEMTs with deeply scaled field plate to Ka band frequencies is considered using device simulations. There, it is shown that the DSFP concept can be used to increase the power gain to around 22 dB at 28 GHz for devices with a gate length of 0.1 um. Additionally, the challenges originating from the silicon substrate are studied by measurements of substrate-related loss. A p-type layer in the silicon substrate at the interface to the GaN epitaxial layers is identified as a major loss contributor and is electrically characterized. Finally, a new loss mechanism is considered, which originates from a compressively stressed silicon substrate after eutectic die attach.
In recent years, the rapid popularization of GaN HEMT devices in power applications has made the traditional GaN static SPICE model unable to meet the requirements of high-voltage and high-frequency circuit design, due to the dynamic ON-resistance (
R
) effect. In this article, we evaluate the dynamic
R
effect of a commercial 100-V Schottky-type p-GaN HEMT in the hard switching mode and propose an empirical dynamic model. The pulse test results show that the gate-to-drain voltage stress is the main cause of the dynamic
R
effect. The peak electric field located at the AlGaN barrier layer and channel of the device will cause threshold voltage positive shift and hot electron effect. These two physical mechanisms that cause the dynamic
R
effect are verified by the TCAD simulation. Meanwhile, we calculated the contribution of the two physical mechanisms to the dynamic
R
under different operation conditions. Based on the test and analysis results, the equivalent circuit is added to the static SPICE model of the device. The proposed empirical model could well simulate the dynamic
R
characteristic and switching behavior of the device in hard switching mode.
Dynamic
E
OSS
of Schottky p-GaN gate GaN devices is investigated by a proposed novel circuit. The easy-to-implement circuit allows for the analysis of dynamic
E
OSS
under different stress types, varied stress times and temperatures. It is observed that, the
E
OSS
is significantly reduced when the device is under continuous hard-switching stress (HSW) compared to devices subjected to OFF-state high voltage drain stress (HDC) and fresh devices, especially under relatively low bus voltage conditions (e.g., 100 V). These findings, linked to the dynamic change of 2DEG, provide new insights into Schottky p-GaN gate HEMT behavior and application understanding.
It is only recently that the electric vehicle (EV) has evolved into a contemporary invention. There has been a rapid acceleration in the development of EVs in a number of nations in order to lessen their reliance on oil and their contribution to environmental pollution. In the tangible world, fully EVs do not release any carbon dioxide (CO2) emissions from their tailpipes, unlike any other conventional vehicles. This results in a 50%–70% CO2 reduction in air pollution per year. The achievement of electrification in transportation has led to a reduction in the weight and size of the vehicles as the need for internal combustion engines can be eliminated. Wide bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN) offer advantages in the manufacturing of EVs. Beginning the late 2000s, the EV industry has begun to adopt GaN devices in their manufacturing processes. The semiconductor material GaN stands out as a material for power electronic systems in EVs owing to its high switching frequency, higher temperature limit, and high voltage breakdown. This review aims to provide a comprehensive overview of semiconductor GaN materials for EV applications, which could be useful to provide insights for researchers and scientists to accelerate their innovation for the improvement of EVs. This review begins with an introduction to EVs, followed by the anticipated demand for EVs. The application of GaN devices in EVs, compared to the traditional Si and SiC devices, which are the primary power devices in current EVs, is discussed. The recent advancement in GaN devices that are capable of being used in various components of a fully automated EV, such as the battery, energy storage system, auxiliary power unit, and motor drive, in addition to their use in different non-automotive vehicles such as electric aircraft, electric ships, electric railways, electric submarines, and heavy duty vehicles, is also discussed. Finally, the challenges posed by GaN devices and potential solutions to overcome these shortcomings have been addressed.
In this work, an automatic reconfigurable inductive-load evaluation platform is built to investigate the stress-time-dependent dynamic
under various operation modes, i.e., Hard-Switching in Continuous Conduction Mode (HS-CCM), Soft-Switching in Continuous Conduction Mode (SS-CCM), and Soft-Switching in Discontinuous Conduction Mode (SS-DCM). The automatic measurement allows real-time monitoring of dynamic
and switching of operation modes rapidly. This study is conducted on commercial Schottky-type PGaN gate device and HD-GIT device. The result shows that the dynamic
will gradually saturate under continuous stress without self-heating effect, which is related to the stabilization time of the dynamic trapping/de-trapping process in the gallium nitride (GaN) buffer layer, and the saturated
is defined by the stabilized
. For Schottky-type p-gate HEMTs, hard-switching (HS) stress exhibits the worst saturated
, due to the hot electrons trapped, compared with the case under soft switching (SS) condition. In contrast, for HD-GIT device, HS condition delivers undetectable dynamic
, attributed to the hole injection from p-GaN near the drain. These findings provide important new insights on the time-dependent stability of p-GaN gate GaN HEMTs.
In this work, the electrical performance degradation and circuit burnout in gallium nitride (GaN)-based microwave monolithic integrated circuit (MMIC) power amplifiers (PAs) under on-state with high drain bias have been studied in-depth. It is found that when the drain bias increases from 30 to 90 V, the saturation drain current decreases by 16%, and the output power drops significantly by 4.5 dB. With the aid of photon emission measurements (PEMs) and scanning electron microscopy (SEM), it is found that catastrophic burnout occurs in the power-stage GaN HEMTs and the MIM capacitors, respectively. For the GaN HEMT, electrons in the channel can gain enough energy with the transverse high electric field to become hot electrons. One part of hot electrons can surmount the AlGaN/GaN interface barrier and then induce leakage paths in the AlGaN layer, resulting in a significant leakage current. The other part of hot electrons will collide with the lattice near the drain edge (DE) and induce significant electron trapping, which will result in a significant longitudinal local electric field. When a critical electric field is achieved, catastrophic burnout occurs. The results obtained from the TCAD simulation verified it. For the MIM capacitor, the failure is attributed to the dielectric breakdown at the edge of the capacitor, which also plays an important role in the circuit deterioration.
In power conversion systems, the power devices often need to block high voltage levels during the OFF-state. The impact of such voltage stress can cause instability for the device. This article presents the investigation of the pulsed
I
–
V
(PIV) OFF-state drain stress test for the etch-free hydrogen plasma-treated p-GaN gate HEMT (H-treated devices). To quantitatively demonstrate the effect of the hydrogen plasma treatment process, the device with conventional p-GaN etching at the access region (etched devices) is monolithically fabricated. Remarkably, the hydrogen treatment could eliminate surface damage from the conventional etching process and provide passivation at the access region. The direct comparison of devices’ threshold voltage (
V
) shift and dynamic ON-resistance (
R
) is obtained. Under a 200-V OFF-state drain stress, the H-treated device has a low
V
shift of 0.18 V, and the dynamic
R
could also be efficiently suppressed by 24%. Meanwhile, the H-treated device has only a marginal 5% current reduction compared with 48% for the etched device at 200-V stress. An exploration of the origin of the superior device performances is carried out with the TCAD simulation, activation energy derivation, and capacitance measurement. For the H-treated device, the surface state improvement at the region and the reduction of the peak electric field at the gate edge become major reasons for the improved performance.
As promising candidates for high-performance power system applications, gallium nitride high electron mobility transistors (GaN HEMTs) have received a lot of attention from the market. However, reliability issues, particularly the dynamic
on
-resistance (
dR
), also known as the current collapse effect, severely limit the promotion and application of GaN HEMTs. This article investigates and compares the
dR
under various power cycle aging conditions for hybrid drain-embedded gate injection transistors (HD-GITs), which serve as representative devices of GaN HEMTs. For the purpose of this, HD-GITs are prepared using power cycling tests, and a voltage clamping circuit is employed to accurately measure the
dR
during the switching applications in both the double-pulse test and the multipulse test. Experimental results demonstrate that, under certain conditions, the
dR
of the device deteriorates as it ages. Furthermore, the primary mechanisms responsible for the deterioration of
dR
characteristics under different aging states are discussed based on systematic electrical test results and reasonable inference. The finds are of great significance for guiding the design, manufacture, and application of GaN devices.
GaN power devices exhibit deteriorated dynamic
RON
after hot electron stress (HES) as new defects/traps are generated at surface or in buffer layer. In this work, we propose a virtual-body p-GaN gate HEMT (VB-HEMT) to improve the ruggedness against hot-electron induced degradation. In the ON-state, the holes injected from p-GaN gate reach the interface between the GaN channel layer and the buried AlGaN layer, forming a hole channel that serves as a “virtual body”. The virtual body screens the hot-electron induced buffer trapping. Additionally, the surface trapping effect is also alleviated in the VB-HEMT, which is likely caused by the spillover of holes from virtual body to the surface or by the hole/electron recombination that emits photons to accelerate the recovery of surface trapping. The suppression of hot-electron induced dynamic
RON
degradation is verified by HES test with various stressing time, stressing voltage, and stressing current.
This study investigates the trapping characteristics present at the interface of Al x Ga 1‐x N/GaN High‐Electron‐Mobility Transistors (HEMTs) and explores the influence of the Al composition within the Al x Ga 1‐x N barrier on the device’s performance. Using a single pulse I D ‐V D characterization technique, we evaluated the reliability instability in two different Al x Ga 1‐x N/GaN HEMTs: one with an Al composition of 25% (Al 0.25 Ga 0.75 N/GaN) and the other with an Al composition of 45% (Al 0.45 Ga 0.55 N/GaN). The results unveiled a notable higher drain current degradation ( ΔI D ) in Al 0.45 Ga 0.55 N/GaN devices, attributed to fast transient charge trapping. Conversely, the Al 0.25 Ga 0.75 N/GaN device exhibited a substantial 35% reduction in interface trap density ( D it ) and an impressive 73% decrease in border trap density ( N bt ), solidifying its reduced trapping behavior compared to Al 0.45 Ga 0.55 N/GaN due to the rougher barrier/channel interface of the latter device. Furthermore, load‐pull measurements unveiled a noteworthy 60% power‐added efficiency (PAE) for the Al 0.25 Ga 0.75 N/GaN device, presenting a 10% performance improvement over the Al 0.45 Ga 0.55 N/GaN device. These findings provide valuable insights into the trapping phenomena within AlGaN/GaN HEMTs, paving the way for enhanced device design and performance optimization.
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In this paper, the device degradation of Schottky-type p-GaN gate high electron mobility transistors (HEMTs) were studied under repetitive short circuit (SC) with various stress parameters. Moreover, for the first time, the device characteristics recovery kinetics were recorded and analyzed to reveal the device degradation mechanism. During the repetitive SC stress, prominent threshold voltage (
V
TH
) shift and substantial drain current reduction were observed. For the stringent SC stress (e.g. 100 SC cycles with
V
gs
= 6 V &
V
dc
= 60 V), the device exhibits irreversible degradation (e.g. Δ
V
TH
& Δ
I
D
). However, in contrast, the device shows a complete recovery after lenient SC stress. The device degradation mechanisms under repetitive SC stress were revealed by carrying out delicate device characterization including high temperature SC stress and gate current together with device simulation. The trap states filling in p-GaN gate region during stress and subsequent electron de-trapping after stress responsible for the recoverable device degradation under lenient SC stress. For the stringent SC stress, driven by the higher electric-field, hot-electron induced defects in the p-GaN gate region together with electron trapping at passivation/III-Nitride interface close to the drain side lead to the irreversible device degradation. Potential guidelines are proposed for mitigating the repetitive SC degradation.
Effects of impact ionization on hard switching in AlGaN/GaN HEMTs are studied by 2-D analysis where undoped semi-insulating buffer including deep-donor traps is assumed. When the OFF-state drain voltage
is near the breakdown voltage, the current collapse or the dynamic ON-resistance
in the hard switching becomes smaller with impact ionization than those without impact ionization and in the case of soft switching. This is because in the case of hard switching with impact ionization, when the gate voltage becomes on and the drain voltage is high, generated holes by impact ionization flow into the buffer and are trapped by deep donors. Then, the buffer layer’s positive space charges increase, resulting in the smaller current collapse or
. The dependence of
on
is also studied. It is shown that when
is relatively low,
increases with
and becomes higher in the hard switching than soft switching. This is because in the hard switching, electron can be injected into the buffer and trapped by deep donors when the gate voltage becomes on, and the buffer layer’s negative space charges can increase. However, when
is high in the case of hard switching,
tends to saturate with increasing
or decreases slightly because of hole’s impact ionization and the hole trapping by the deep donors. Then,
becomes smaller in the hard switching than in the soft switching when
becomes high.
Gallium nitride (GaN) is an emerging wide-bandgap material with superior physical characteristics, including critical electric field, electron mobility, and specific
on
-resistance compared to silicon counterparts. GaN's inherent material properties allow for the development of power electronics with improved performance, such as efficiency, power density, and weight. However, GaN high-electron-mobility transistors (HEMTs) exhibit a parasitic phenomenon of time-varying
on
-resistance, known as dynamic
on
-resistance or “current collapse,” largely due to charge trapping and hot-electron injection in undesirable locations of the device structure. Evaluating and characterizing this phenomenon based on GaN's intended operating conditions is crucial to perform design tradeoff studies for target applications. Therefore, this article provides an extensive review of prior research related to GaN dynamic
on
-resistance, while identifying limitations, challenges, and opportunities based on a survey of the state-of-the-art approaches in literature. Converter-based dynamic operations can create electric fields and leakage paths that are not seen in dc operation, which can lead to serious reliability concerns that should be factored into a device design optimal for power electronic applications. In light of understanding time-dependent stress effects linked to dynamic
on
-resistance, this article provides several simulation studies analyzing field distribution on the field plates when varying voltage stress slew rates are applied. Such simulation studies seek to identify key elements and analysis missing in prior literature and foreshadow the importance of the research topic to realize the true dynamic behavior of
on
-resistance in GaN HEMTs.
Hot electron effects have been studied in multichannel AlGaN/GaN-based Superlattice Castellated Field Effect Transistors (SLCFET). Current-Voltage (I-V) and simulations could identify channel position-dependent impact ionization within the device fins. Electroluminescence (EL) emission is observed simultaneously with the impact ionization, whose spectral analysis shows the signature of hot electron scattering (Bremsstrahlung radiation) and not electron-hole recombination.
In this work, we reveal a correlation between the evolution of the channel electric field profile and dynamic ON resistance (
{\Delta} \textit{R}_{\bios{on}}
) behavior of AlGaN/GaN HEMTs when subjected to cyclic nanosecond pulse stress on the drain terminal. Two scenarios of field profile evolution were studied: 1) field peak shifting from gate/field plate edge (GE/FP) to drain edge (DE) and 2) field peaking near GE/FP edge but not showing any shift. The devices exhibiting a shift in the electric field peak to DE in response to the cyclic stress showed a unique increase in
{\Delta} \textit{R}_{\bios{on}}
which was absent in devices that did not show any such field shift. Factors accelerating this field shift to DE, including drain bias, channel current, and stress pulsewidth (PW), were found to accelerate the increase in
{\Delta} \textit{R}_{\bios{on}}
. Furthermore, the devices exhibiting such an increase in
{\Delta} \textit{R}_{\bios{on}}
showed a slower recovery of the ON-resistance when compared to devices with field peak only near the GE/FP edge. Physical insights were developed using detailed experimentation and well-calibrated computations, which could capture the observed phenomenon. The developed insights and proposed mechanisms were then experimentally validated by studying the dependence of the
{\Delta} \textit{R}_{\bios{on}}
behavior on: 1) passivation thickness-induced electric field profile modulation and 2) substrate temperature-induced trapping/detrapping rate modulation.
In this article, the temperature-dependent dynamic ON-resistance (
\textit{R}_{\biosc{on}}
) behaviors of GaN enhancement-mode (E-mode) high-electron-mobility transistors (E-HEMTs) with and without a p-GaN drain (PD) structure under both hard-switching (HS) and soft-switching (SS) have been systematically studied and analyzed, whereby the influences of temperature, OFF-state voltage stress, the PD structure, HS/SS, switching transients during HS, and ON-state current on dynamic
\textit{R}_{\biosc{on}}
of GaN E-HEMTs have been revealed. It is found that higher temperature, higher OFF-state voltage stress, or larger ON-state current particularly under HS can facilitate the turn-on of the PD hetero-junction and enhance hole injection, which can effectively compensate the negative trapped charges and alleviate dynamic
\textit{R}_{\biosc{on}}
degradation. The characterizations and analysis in this work can provide valuable insights into the mechanisms of superior dynamic performance in high-temperature and high-power applications.
Accurate characterization of the dynamic
on
-resistance (R
{}_\textsc{on}
) degradation is important to predict conduction losses for gallium nitride (GaN) high-electron-mobility transistors. However, even for the same device, many inconsistent results of dynamic R
{}_\textsc{on}
based on pulsed measurements are reported in the literature. This letter reveals that insufficient test time leads to spurious dynamic R
{}_\textsc{on}
results and even contradictory conclusions. We show that the time required for the dynamic R
{}_\textsc{on}
to stabilize can be very long (∼ 3 min) for some commercial GaN devices and pulsed measurements fail to give accurate results. These findings are enabled by our proposed steady-state method using a hard-switching half-bridge with an active measurement circuit. It minimizes the influence of temperature on the R
{}_\textsc{on}
, enabling to capture trap-related effects independently from the operation conditions. This letter raises awareness of the effect of poorly measured dynamic R
{}_\textsc{on}
and highlights that steady-state methods should be applied for accurate measurements to predict their performance in real power converter operations.
In this work, we report a unique dependence of dynamic
\textit{R}_{\biosub{on}}
on gate-stack of AlGaN/GaN high electron mobility transistors (HEMTs) on carbon (C)-doped GaN buffer under semi-on condition. Unlike the OFF-state stress, semi-ON state stressing of the devices revealed a significantly lower dynamic
\textit{R}_{\biosub{on}}
in the Schottky HEMTs when compared to
-gated HEMTs. Detailed experiments including substrate bias dependence, electro-luminescence (EL) spectrum, and electric field analysis established electron trapping in the GaN buffer to be the source of dynamic
\textit{R}_{\biosub{on}}
in both the HEMT types. An on-the-fly thermal analysis, using thermoreflectance technique, revealed Schottky HEMTs to have a higher hot electron-induced self-heating near the field plate (FP) edge as compared to SiN
-gated devices. The higher lattice temperature was found to result in a significantly higher electron de-trapping from the buffer traps. The higher de-trapping reduced the dynamic
\textit{R}_{\biosub{on}}
in the Schottky HEMTs as compared the
-gated devices.
In this work, we report a unique time-dependent evolution of drain current and hot electron distribution along the width of AlGaN/GaN HEMTs on C-doped GaN buffer during semi-ON state stressing. The drain current evolution with stress time exhibited two distinct phases, i.e., first, drain current reduction at lower stress times, which, second, is followed by an increase in the magnitude for longer stress times. Electroluminescence (EL) measurements revealed this to be accompanied by a transition in the hot electron distribution along the device width, from being uniform (during the current reduction phase) to being confined near the center of the device (during current increase phase). Detailed experiments involving measure-stress-measure (M-S-M) routine showed a gate-stack-dependent threshold voltage shift in
-gated MISHEMTs to be responsible for the reduction in the drain current. On the other hand, increase in the drain current and hot electron confinement were observed in Schottky as well as MIS-gated devices. Furthermore, in situ thermoreflectance-based temperature monitoring showed a nonuniform temperature distribution along the device width. Detailed computations, taking into account the nonuniform temperature distribution, established heating induced nonuniform hole emission along the device width and their subsequent lateral redistribution to be responsible for the experimentally observed current increase and hot electron confinement.
Transistor-based on Gallium Nitride (GaN) technology, has enabled energy-saving power electronics to alleviate global energy utilization. Being the initial stages of the development as compared to mature Silicon (Si) technology, the critical issues related to the reliability of GaN-based devices are not much explored. To better understand the device reliability, the article reviews and summarizes, the trapping induced threshold voltage (VTH) instability and dynamic ON-resistance (RDS,ON) degradation specifically, for normally-off p-GaN gate HEMTs in power applications. The variation in threshold voltage and dynamic ON-resistance is examined for different operating regimes, which include biasing voltage and temperature. Furthermore, the characterization methods and test setups are discussed in detail to extract the true value of RDS,ON observed in the GaN power converter. Various models and techniques are reviewed as well which improves the converter conduction losses, introduced by dynamic ON-resistance. Additionally, different techniques are discussed in the review to control the VTH instability. It is observed that the point and extended defects created during device fabrication or charge trapping in GaN buffer, AlGaN layer, surface, or at their interface, induce variation in (VTH) and RDS,ON, for both the gate and drain stress regimes. Threshold voltage stability is mainly affected by the traps below the gate region, while the traps across the gate to drain access region influence the RDS,ON. The variation in RDS,ON value, is seen to be dependent on stress time, different device technology, and, switching conditions (frequency and duty cycle). In power application, the dynamic resistance shows a more pronounced effect on converter efficiency as compared to the VTH.
Computer-aided analysis of impact ionization effects on turn-on characteristics or current collapse of AlGaN/GaN HEMTs is performed. Here, an intrinsic semi-insulating buffer is adopted in which deep donors are assumed to compensate deep acceptors, then the ionized deep donor usually plays a role as an electron trap. Calculated turn-on characteristics show that when impact ionization is not included, the drain current begins to increase relatively slowly because electrons are emitted from the deep donors, showing a large current collapse. On the other hand, when impact ionization is included and an ON-state drain voltage
\textit{V}_{\text{D}\biosub{on}}
is high, generated holes between the gate and drain flow toward the buffer and are captured by neutral deep donors, particularly at the source side. The hole capturing time becomes relatively short when
\textit{V}_{\text{D}\biosub{on}}
is high and the hole density is high. Because of these increases in positive space charges in the buffer, the drain current increases relatively fast before the electron emission under the gate starts. Therefore, the current collapse becomes weaker when the impact ionization is considered and
\textit{V}_{\text{D}\biosub{on}}
is higher. The situation may be similar with a different type of buffer such as an Fe-doped semi-insulating buffer in which the Fe-originated level (deep acceptor) is above the midgap and it usually plays a role as an electron trap.
This paper investigated electroluminescence (EL) in AlGaN/GaN HEMTs fabricated on a free-standing GaN substrate (GaN-on-GaN) with ones on a SiC substrate (GaN-on-SiC) as a reference. When a drain voltage ( V ds ) of the GaN-on-GaN was increased, EL peak was kept to beside the gate, indicating that the highest electric field region stayed at a vicinity of the gate. On the other hand, EL of the GaN-on-SiC shifted from the gate to the drain electrode under an increased Vds. Our results indicate that high-electric-field tolerance of GaN-on-GaN is higher than that of GaN-on-SiC, indicating GaN-on-GaN is more suitable for high-voltage operation.
Hot electrons with high kinetic energy could be generated in the channel of GaN high-electron-mobility transistors (HEMTs) during hard switching operation. Those “lucky” hot electrons scattered to the vulnerable interface between the passivation and barrier layers could bombard the interface region and create new defects that would lead to degradation of the dynamic on-resistance (
) after long-term operations. In this work, we propose a solution to the hot-electron induced device degradation through channel engineering, i.e., deploying a double-channel structure in place of the conventional single-channel structure in
-GaN gate HEMTs. It is revealed that hot electrons are mostly generated in the lower channel and thus the additional scattering interface can effectively deter the hot electrons from reaching the vulnerable surface. Dynamic
degradation induced by long-term stresses at “semi-on” states is shown to be substantially suppressed in the
-GaN gate HEMT with the double-channel structure.
In this study, the threshold voltage (V
T
) degradation mechanism for a hot electron stress (HES) under semi-ON state conditions in AlGaN/GaN high electron mobility transistors is analyzed. The drain current versus gate voltage (I
D
–V
G
) characteristic curves indicate that V
T
shifts in the positive direction after the stress. However, an abnormal phenomenon that V
T
continuously shifts in the positive direction even after recovery is observed. A result comparison of a negative bias stress (NBS) experiment indicates that a hole recombination in pre-existing buffer defects is crucial. Therefore, a complete model of V
T
degradation mechanism is proposed. Moreover, the proposed model is confirmed through an illumination experiment and a Silvaco simulation.
The nature of hot electron electroluminescence (EL) in AlGaN/GaN high electron mobility transistors is studied and attributed to Bremsstrahlung. The spectral distribution has been corrected, for the first time, for interference effects due to the multilayered device structure, and this was shown to be crucial for the correct interpretation of the data, avoiding artefacts in the spectrum and misinterpretation of the results. An analytical expression for the spectral distribution of emitted light is derived assuming Bremsstrahlung as the only origin and compared to the simplified exponential model for the high energy tail commonly used for electron temperature extraction: the electron temperature obtained results about 20% lower compared to the approximated exponential model. Comparison of EL intensity for devices from different wafers illustrated the dependence of EL intensity on the material quality. The polarization of electroluminescence also confirms Bremsstrahlung as the dominant origin of the light emitted, ruling out other possible main mechanisms.
Despite the potential of GaN-based power transistors, these devices still suffer from certain parasitic and reliability issues that limit their static and dynamic performance and the maximum switching frequency. The aim of this paper is to review our most recent results on the parasitic mechanisms that affect the performance of GaN-on-Si HEMTs; more specifically, we describe the following relevant processes: (i) trapping of electrons in the buffer, which is induced by off-state operation; (ii) trapping of hot electrons, which is promoted by semi-on state operation; (iii) trapping of electrons in the gate insulator, which is favored by the exposure to positive gate bias. Moreover, we will describe one of the most critical reliability aspects of Metal-Insulator-Semiconductor HEMTs (MIS-HEMTs), namely time-dependent dielectric breakdown.
This paper reports a comprehensive time dependent dielectric breakdown (TDDB) evaluation of recessed-gate devices with five different AlGaN barrier thicknesses with characteristics ranging from a D-mode MIS-HEMT to an E-mode MIS-FET. First, the fitted parameter β (the slope of the Weibull distribution) was smaller for a deeper recessed gate and larger for a thicker gate dielectric. Secondly, the extrapolated V G (criterium of 0.01% failures after 20 years) for the devices with Wg (gate width) = 10µm was lower when less AlGaN barrier remains under the gate. However, the extrapolated V G was increased when the AlGaN barrier was completely removed. Thirdly, a deeper recessed gate could result in a dominant percolation path due to a thinner gate dielectric on the sidewall of the gate recess edge. Fourthly, the Weibull distribution could scale with the gate width, indicating an intrinsic failure. Finally, the lifetime was extrapolated to 0.01% of failures for W g =36mm at 150 o C after 20 years by fitting the data with a power law or an exponential law to gate voltages of 4.9V and 7.2V, respectively.
In this paper, we studied the vertical leakage/breakdown mechanisms in AlGaN/GaN structures grown on low resistivity p-type (111) Si substrate by temperature-dependent current-voltage measurements. We suggested that the top-to-substrate vertical leakage/breakdown is dominated by the space-charge-limited current (SCLC) conduction mechanism involving both acceptor and donor traps in buffer/transition layer. Based on temperature-dependent transient backgating measurements, the acceptor level and donor level were determined to be at EV+543 meV and EC-616 meV, respectively.
Standard qualification methodology or “qual” does not specify product-level testing due to the diverse range of products and use conditions, a limited ability for system-level acceleration, and complication from system-level failures. This is a concern for emerging power-management technologies, since the fundamental switching transitions are not covered. We show that hard-switching with the well-known double-pulse tester is predictive of device performance under system-level testing. It simplifies the problem of product reliability testing to one of a device and a tester. It enables us to detect devices that pass qual but perform poorly in application. As a result, our devices pass qual and perform well in application.
Dynamic RON and ramped substrate bias measurements are used to demonstrate size- and geometry-dependent dispersion in power transistors. This is due to a novel lateral transport mechanism in the semi-insulating carbon-doped GaN buffer in AlGaN/GaN high-electron-mobility transistors. We propose that the vertical field generates a 2-D hole gas (2DHG) at the bottom of the GaN:C layer, with hole flow extending outside the isolated area. The device-to-device variation is due to a combination of widely spaced preferential leakage paths through the structure and lateral transport from those paths to trapping sites. The spread of the 2DHG outside the active area of the device strongly affects the result of substrate ramp measurements producing major differences between single and multifinger devices. In dynamic RON recovery measurements, single-finger devices show large device-to-device variation, with multifinger devices showing a small variation with the transient comprising the superposition of the recovery transient of multiple small single-finger devices.
A 2D TCAD-based approach is proposed to investigate the leakage current and breakdown regime of GaN/AlGaN/Si structures at different ambient temperatures. Deep-level traps originated by Carbon doping, impact-ionization generation and thermally activated Poole-Frenkel conduction have been modeled to assess the role of such physical mechanisms on the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing conduction and valence mini-bands within the deeper transition layer created by conductive dislocation defects or by superlattice structures. A 2D isolation device has been investigated up to breakdown and, for the first time to our knowledge, we prove with 2D TCAD simulation that in GaN based devices both impact-ionization and Poole-Frenkel conduction effects must be taken into account to correctly match experimental data.
A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.
We have investigated current collapse in GaN heterojunction field effect transistors (HFETs) for high voltage power switching applications. With a novel technique in which the gate and drain pulses are controlled independently, we have measured the current collapse under various switching conditions. We found that the current collapse improves under hard switching in which the loadline passes through high current and high voltage area. This was attributed to holes that are generated through impact ionization and compensate trapped electrons at device surface. We show that optimized field plate and surface treatment significantly improves the current collapse for high voltage GaN HFETs.
This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.
This paper presents a detailed analysis of the electroluminescence (EL) and short-term degradation processes related to hot electrons that occur in AlGaN/GaN-based high-electron mobility transistors (HEMTs) submitted to on-state stress. Based on optical and electrical characterization, we demonstrate that: 1) when biased in on-state, HEMTs emit a luminescence signal, which is uniformly distributed along gate width, and related to intraband transitions of hot electrons; the intensity of the luminescence has bell-shaped dependence on gate voltage; 2) when submitted to on-state stress (with V-D = 30 V and several V-G levels), HEMTs show a significant degradation, mostly consisting in an increase in on-resistance and in a decrease in drain current; and 3) stress tests carried out at several V-G levels (with V-D = 30 V) indicate that the degradation rate does not increase monotonically with V-G, as would be expected if temperature and/or power dissipation were the main driving forces for degradation. On the contrary, degradation rate was found to have bell-shaped dependence on V-G, similarly to what was found for the intensity of the EL signal. The observed degradation process is ascribed to trapping of negative charge in the gate-drain access region, activated by hot electrons. The degradation mechanism cannot be recovered at room temperature but only through exposure to UV light.
This paper reports on an extensive analysis of the degradation of AlGaN/GaN HEMTs submitted to on-state stress tests. By means of combined electrical and electroluminescence characterization we demonstrate that: (i) exposure to on-state stress can induce a remarkable decrease in drain current; (ii) degradation rate strongly depends on the intensity of the EL signal emitted by the devices during stress, while it has a negligible dependence on temperature. On the basis of the experimental evidence collected within this work, degradation is ascribed to electron trapping in the gate-drain access region, induced by hot electrons. Finally, we derived an acceleration law for GaN HEMT degradation, by using the intensity of the EL signal as a measure of the stress acceleration factor.
This paper presents a fast methodology for the investigation of trapping and hot-electron effects in GaN-based high-electron mobility transistors (HEMTs). The presented method is based on pulsed ID - VG measurements and electroluminescence characterization and provides a rapid and effective evaluation of the following: 1) the presence of traps in the region under the gate; 2) trapping phenomena occurring in the gate-drain access region; 3) the role of traps in limiting the maximum gate-drain electric field and the equivalent electron temperature. The method is validated by means of a split-wafer experiment carried out on GaN-based HEMTs with different gate materials with and without passivation.
On conduction mechanisms through SiN/AlGaN based gate dielectric and assessment of intrinsic reliability
- A Banerjee
- P Vanmeerbeek
- L De
- S Schepper
- P Vandeweghe
- P Coppens
- Moens
A. Banerjee, P. Vanmeerbeek, L. De Schepper, S. Vandeweghe,
P. Coppens, and P. Moens, "On conduction mechanisms through
SiN/AlGaN based gate dielectric and assessment of intrinsic reliability,"
in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2016, pp. 1-5.
Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs
- T Wu
T. Wu et al., "Time dependent dielectric breakdown (TDDB) evaluation
of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode
MIS-HEMTs and E-mode MIS-FETs," in Proc. IEEE Int. Rel. Phys.
Symp., Apr. 2015, pp. 4-9.
Application reliability validation of GaN power devices
- S R Bahl
- J Joh
- L Fu
- A Sasikumar
- T Chatterjee
- S Pendharkar
S. R. Bahl, J. Joh, L. Fu, A. Sasikumar, T. Chatterjee, and S. Pendharkar,
"Application reliability validation of GaN power devices," in IEDM Tech.
Dig., Dec. 2016, pp. 544-547.