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An outline of Qucs-S compact device modelling: History and capabilities: Part 1: Equation-Defined Device (EDD) modelling to Verilog-A module synthesis

Authors:
  • London Metropolitan University, Holloway, London, Uk

Abstract

The purpose of this two part presentation is to provide the compact device modelling community with a detailed introduction to the history and capabilities of the modelling features implemented in the Qucs-S multi-simulator software package. Roughly ten years ago the Qucs Development Team started the process of adding compact device modelling features to the widely used Qucs circuit simulator. In 2017 the first stable version of the multi-simulator version of Qucs, called Qucs-S, was released. This GPL software package provides users with an extensive range of simulation and modelling tools, including (1) Ngspice, SPICE OPUS and Xyce and (2) subcircuits, non-linear EDD, SPICE B style sources, Verilog-A modules, XSPICE Code Models, SPICE netlist synthesisers, Verilog-A, module and XSPICE Code Model synthesisers. The properties and use of these simulation modelling tools are introduced and their application described with a series of semiconductor device models. The slides from this presentation are intended to be a reference source when developing Qucs-S compact device models.
An outline of Qucs-S compact device modelling: History and
capabilities: Part 1: Equation-Defined Device (EDD) modelling
to Verilog-A module synthesis
Mike Brinson 1,mbrin72043@yahoo.co.uk.
Vadim Kuznetsov 2,ra3xdh@gmail.com
1Centre for Communications Technology, London Metropolitan University,
UK
2Bauman Moscow Technical University, Russia
Presented at IEEE ED Mini-Colloquium, Bygoszcz, Poland, 21 June 2017
May 24, 2017
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Qucs-S Internet facilities: documentation and software download sites
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History of Qucs-S compact device modelling
21 Feb 2007 : Implementation of subcircuit parameters. Allow equation variables and sweep parameters in
component properties and subcircuit parameters. Equations can be placed in subcircuits.
24 Feb 2007 : Input parameters of components can be used in Qucs-S equations.
21 Apr 2007 : Support for symbolically defined devices (EDD). ONLY explicit equations allowed.
2 Sep 2007 : Allow number engineering notation in equations (pre- and post-processing as well as EDD).
Oct 2007 : Using ADMS to translate Verilog-AMS device models into C++ co de. Manual compiling and
linking of model C++ CODE.
2008 to 2011 : Generation of Verilog-A compact semiconductor device models.
3 Mar 2011 : Implementation of interactive GNU Octave connection to Qucs-S.
31 Aug 2014 : Dynamic compilation and loading of Verilog-A modules, Addition of a full ADMS/Qucs ”turn
key” Verilog-A compact device modelling system to Qucs. Users are no longer required to manually edit
C++ code and build system to be able to run Verilog-A models. Uses ADMS 2.3.4.
23 Nov 2014 : Synthesis/translation of Qucs-S schematics/netlists to SPICE style netlists.
2014 to 2015 : Full set of SPICE commands added, for example .PARAM, and .OPTION.
2014 to 2015 : Full set of SPICE components added.
24 Aug 2015 : Verilog-A ”Turn-Key” module synthesiser added.
28 Sept 2015 : Qucs PlotVs() function added to Qucs-S.
9 March 2016 : XSPICE distributed analogue device models and user defined Co de Models added.
8 April 2016 : Addition of XSPICE Code Mo dels in user generated model libraries.
4 Nov 2016 : Start developing XSPICE ”Turn-Key” Code Model synthesiser.
1 Feb 2017 : EDD maximum number of branches increased from 8 to 20.
5 March 2017 : Added .FUNC and .include-script components.
2017 ........ : Continuing Qucs-S development in preparation for release 0.0.20.
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A flow chart showing Qucs-S compact modelling facilities and data
movement
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Building compact device models with Qucs-S: 1 Specification of the static
and dynamic device properties of a semiconductor step recovery diode
example
In this presentation a compact model for a semiconductor step diode has been
chosen to illustrate the different model building tools implemented by Qucs-S.
This choice of model is deliberate because it’s properties are well known, making
the operation of the modelling tools easier to follow and understand.
Non-linear static Id-Vd characteristics :
Id =IST 2·(exp(Vd /(N·Vt(T2)))) 1.0) + GMIN ·Vd ,where
Vd =V(Anode,Cathode),
T1 = TNOM + 273.15,
T2 = TEMP + 273.15,
Vt(T2) = (k·T2)/q,
IST 2 = IS ·AREA ·(T2/T1)XTN/N·exp(Eg(300)/Vt(T2)),
Eg(T) = Eg (7.02e4·T·T)/(1108.0 + T), here
kis the Boltzmann constant and qthe elementary charge. Other physical
parameters have their usual meaning: AREA = 1,N= 1,IS = 1e14,
XTI = 3.0,Eg = 1.16,TNOM = 26.85,TEMP = 26.85 and GMIN = 1e9.
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Building compact device models with Qucs-S: 1 Specification of the static
and dynamic device properties of a semiconductor step recovery diode
example
Reverse breakdown voltage :
K2=1.0/(N·Vt(T2)),K5 = N·Vt (T2),IBVEFF =IBV ·AREA
IDBV =IST 2·(limexp(BV ·K2) 1.0),
BVEFF = (IBVEFF >IDBV )?BV K5·ln(IBVEFF /IDBV ) : BV ,
Id =IST 2·(limexp((BVEFF Vd )·K2) 1.0 + BVEFF ·K2), where the
breakdown physical parameters have their usual meaning: BV = 4.5, and
IBV = 1e3.
Basic semiconductor diode depletion charge :
Qdep = (Vd >= 0.0)?CJ0T2·(Vd +P11 ·Vd ·Vd ) : P6·(1 (1 Vd /JT 2)P7),
where
CJ0T2 = CJ 0·AREA,P11 = M/(2 ·VJ ),P6=(CJ0T2·VJT 2)/P7,
P7=1M, and
VJT 2=(T2·VJ)/T12·Vt (T2)·ln(T2/T1)1.5((T2·Eg (T1)/T1)Eg(T2),
where the depletion capacitor physical parameters have their usual meaning:
CJ0=1e12,VJ = 1.0 and M= 0.5.
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Building compact device models with Qucs-S: 1 Specification of the static
and dynamic device properties of a semiconductor step recovery diode
example
Noise current :
i2= 2 ·q·Id ·f+Kf ·Id Af
f·f+4·K·T
Rs ·f,
where the noise physical parameters have their usual meaning:
Kf = 0.0,Af = 1.0.
Basic semiconductor diode diffusion charge :
Qdiff =TT ·Id
Step recovery diode charge :
Qd = (Vd <= 0.0)?CJ0Vd : 0.0,
Qd = (Vd >0.0)&&(Vd <FCP)?C1(Vd +C2)2C3:0.0,
Qd = (Vd >0.0)&&(Vd >FCP)?Cf Vd Cf : 0.0, where
FCP =FC VJ,Cf =TAU/Rs,Cm =Cf CJ 0,C1 = Cf CJ)/2FCP,
C2=(CJ0FCP )/Cn,C3=(CJ 0CJ0FCP )/(2 Cm),C4 = Cm FCP/2,
where the capacitor physical parameters have their usual meaning:
TAU = 2e9,Rs = 0.1,FC = 0.5.
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Qucs-S Equation-defined components - subcircuit/macromodel design
equations
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Qucs-S: Subcircuit / macromodels
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Qucs-S: Nonlinear equation defined devices (EDD)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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20
D1
I1=0
In
Vn
I = I(V), g = dI/dV
Q = Q(V,I), C = dQ/dV = ∂Q(V)/∂V + ∂ Q(I)/∂I·g, where
the current flowing in branch n is In = I(Vn) + d/dt(Qn), and 1 <= n <= 20.
Qucs-S Equation-Defined Device (EDD)
• EDD is a multiterminal nonlinea r component with branch currents that can be functio ns of EDD branch
voltage, and stored charge that can be a function of both EDD branch voltages and currents
• EDD is similar, but more advanced to the SPIC E 3f5 B type I or V controlled so urces
• EDD can be combined with conventional circuit components and Qucs-S equa tion blocks when constructing
compact device models and subcircuit mac romodels
• EDD is an advanced component , allowing users to construct prototype experimental models from a set o f
equations derived from physical device properties
• EDD operator d/dt is under taken internally by Qucs-S
• Qucs-S EDD can h ave a maximum of 20 two terminal branches
Jahn S. & Brinson M.E. (2008 ). Interactive compact device modelling using Qucs equation-defined devices. International Journal of Numerical Modelling:
Electrical Networks, Devices and Fields, 21:33 5-349, DOI:10.1002/jnm.676, John Wiley & Sons, Ltd .
Brinson M.E. & Jahn S. (2009 ), Qucs: A GPL software package for simulation, compact d evice modelling and circuit macromodelling from DC to RF and beyond,
International Journal of Numerical Mode lling: Electrical Networks, Devices and Fields, 22:297-319, DO I:10.1002/jnm.702, John Wiley & Sons, Ltd.
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Qucs-S: An EDD compact model of a semiconductor diode, including noise
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Qucs-S: An EDD compact model of a semiconductor diode, typical
simulation data
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Qucs-S: An EDD compact model of a step recovery semiconductor diode
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Qucs-S: Test circuit and simulation data for the step recovery
semiconductor diode model
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Generating Qucs-S Verilog-A compact device models: Introduction
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Relationships between Qucs-S schematic symbols and Verilog-A code
fragments
A maximum of 20 two port branches are now allowed per EDD.
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MOT-ADMS: Introduction to the basic Verilog-A subset available with
ADMS
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MOT-ADMS: Introduction to the basic Verilog-A subset available with
ADMS; continued
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MOT-ADMS: Introduction to the basic Verilog-A subset available with
ADMS; continued
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Generating Qucs-S Verilog-A compact device models: original user
controlled construction of Verilog-A models using static C libraries
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Generating Qucs Verilog-A compact device models: C++ code patches;
model REGISTRATION process
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part I
Qucs-0.0.19S includes the first release of a GPL Verilog-A synthesis tool for
compact device modelling.
The Qucs-0.0.19-S Verilog-A synthesizer is a basic working version of this
new open source ECAD tool.
Generated synthesized Verilog-A code is relatively basic and has to be
optimized manually for speed. However, it is expected that in the future its
operation will improve as development of the Qucs synthesizer progresses.
Circuits and Verilog-A synthesized models can be constructed from the
following Qucs/SPICE built in components:
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part II
Data flow through the Qucs GPL compact device modelling tool set.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part IV
Synthesis of a SPICE like compact semiconductor diode model: static Idand
dynamic capacitance model plus synthesized Verilog-A module code.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part V
Synthesis of a SPICE like semiconductor diode model: simulated static and
dynamic characteristics.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part VI
Verilog-A synthesis of a SPICE like semiconductor diode model: temperature
effects
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part VII
Verilog-A synthesis of a SPICE like semiconductor diode model: simulated
IdVdtemperature effects.
Simulation data for
Qucs EDD model and built-in diode model
Simulation data for
Verilog-A model and built-in diode model
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part VIII
Verilog-A synthesis of semiconductor device shot and flicker noise: EDD
models and Verilog-A module code.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part IX
Verilog-A synthesis of semiconductor device shot and flicker noise: small signal
AC domain simulation data.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part X
Verilog-A synthesis of multi-EDD models: EKV2p6 nMOS
Ids =f(Vd,Vg,Vs,Vb) model for a transistor operating in long channel mode.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part XI
Verilog-A synthesis of multi-EDD models: EKV2p6 nMOS
Ids =f(Vd,Vg,Vs,Vb) swept DC simulation data.
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Introduction to the Qucs GPL Verilog-A module synthesizer: Part XII
Verilog-A synthesis of multi-EDD models: Optimization of Qucs synthesized
Verilog-A module code for speed.
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An outline of Qucs-S compact device modelling: History and capabilities:
Part 1– From Equation-Defined Device (EDD) modelling to Verilog-A
module synthesis
End of Part 1
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