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An economical class of digital filters for decimation and interpolation
Abstract
A class of digital linear phase finite impulse response (FIR) filters for decimation (sampling rate decrease) and interpolation (sampling rate increase) are presented. They require no multipliers and use limited storage making them an economical alternative to conventional implementations for certain applications. A digital filter in this class consists of cascaded ideal integrator stages operating at a high sampling rate and an equal number of comb stages operating at a low sampling rate. Together, a single integrator-comb pair produces a uniform FIR. The number of cascaded integrator-comb pairs is chosen to meet design requirements for aliasing or imaging error. Design procedures and examples are given for both decimation and interpolation filters with the emphasis on frequency response and register width.
... For both, the transition width is selected to be w lb = 0.01π, or 50 Hz for F s = 10 kHz, guaranteeing that the filter response is within the ripple specifications at and beyond the nominal frequency. Initially, evaluating signals in the range of [48,52] Hz, this transition width was found to be sufficient and the primary factor affecting performance was the ripple limit. However, for 1 frequencies below this range, ω lb should be decreased to avoid distortion of the analytic signal, as discussed in Section V-B1. ...
... The calculation of D T F R x ϕ becomes a recursive, sliding accumulator with distinct similarities to Cascaded Integrator-Comb filters (CIC) [48], involving a feed-forward and feedback portion, as shown in Fig. 3. CIC filters are guaranteed stable when implemented in fixed-point, rather than floating point, as the arithmetic operations are performed exactly [48]. ...
... The calculation of D T F R x ϕ becomes a recursive, sliding accumulator with distinct similarities to Cascaded Integrator-Comb filters (CIC) [48], involving a feed-forward and feedback portion, as shown in Fig. 3. CIC filters are guaranteed stable when implemented in fixed-point, rather than floating point, as the arithmetic operations are performed exactly [48]. ...
With the integration of distributed energy resources and the trend towards low-inertia power grids, the frequency and severity of grid dynamics is expected to increase. Conventional phasor-based signal processing methods are proving to be insufficient in the analysis of non-stationary AC voltage and current waveforms, while the computational complexity of many dynamic signal analysis techniques hinders their deployment in operational embedded systems. This paper presents the Functional Basis Analysis (FBA), a signal processing tool capable of capturing the broadband nature of common single-component signal dynamics in power grids while maintaining a streamlined design for real-time monitoring applications. Relying on the Hilbert transform and optimization techniques, the FBA can be user-engineered to identify and characterize combinations of several of the most common signal dynamics in power grids, including amplitude/phase modulations, frequency ramps and steps. This paper describes the theoretical basis and design of the FBA as well as the deployment of the algorithm in embedded hardware systems, with adaptations made to consider latency requirements, finite memory capacity, and fixed-point precision arithmetic. For validation, a PMU calibrator is used to evaluate and compare the algorithm’s performance to state-of-the-art static and dynamic phasor methods. The test results highlight the potential of the FBA method for implementation in embedded systems to enhance grid situational awareness during critical grid events. Future work will investigate the extraction of multicomponent broadband signals with empirical mode decomposition for harmonic analysis.
... The design of computationally efficient decimation filters for Σ∆ A/D converters is a well-known research topic [1], [2], [3]. Given a base-band analog input signal x(t) with bandwidth [−f x , +f x ], a Σ∆ A/D converter of order B produces a digital signal x(nT s ) by sampling x(t) at rate f s = 2ρf x ≫ 2f x , whereby ρ is the so called oversampling ratio. ...
... The first decimation filter is usually an N -th order comb filter decimating by This work was partially supported by EuroConcepts., S.r.l. D [2], [3], [5], whereby the order N has to be greater or equal to B + 1 [1], [3]. The design of a multistage decimation filter for Σ∆ converters poses stringent constraints on the shape of the frequency response of the first decimation stage. ...
... In connection with the first decimation stage in the multistage architecture shown in Fig. 1, the required aliasing protection around the folding bands is usually guaranteed by a comb filter, which provides an inherent antialising function by placing its zeros in the middle of each folding band. We recall that the transfer function of a N -th-order comb filter is defined as [2]: ...
Generalized comb filters (GCFs) are efficient anti-aliasing decimation filters with improved selectivity and quantization noise (QN) rejection performance around the so called folding bands with respect to classical comb filters. In this paper, we address the design of GCF filters by proposing an efficient partial polyphase architecture with the aim to reduce the data rate as much as possible after the Sigma-Delta A/D conversion. We propose a mathematical framework in order to completely characterize the dependence of the frequency response of GCFs on the quantization of the multipliers embedded in the proposed filter architecture. This analysis paves the way to the design of multiplier-less decimation architectures. We also derive the impulse response of a sample 3rd order GCF filter used as a reference scheme throughout the paper.
... The design of cascade-integrator comb (CIC) filters was first addressed in [11], while multirate architectures embedding comb filters have been discussed in [12]. Since then, many papers [13] have focused on the computational optimization of CIC filters even in the light of new wide-band and recofigurable receiver design applications [14]- [16]. ...
... By virtue of the different ways to factorize the integer 60, property (12) can be applied with the following combinations p = 5, q = 12, p = 3, q = 20 whereby in both cases p is a prime integer not dividing q. Property (11) can be applied with m = 15, n = 2, k = 2. In Table IV we show only both the recursive and the non recursive architectures yielding the lowest complexities. ...
... The last relation in (24) can be simplified as follows: (25) A recursive implementation of filter H 8,2 (z) in (25) is shown in Fig. 4e. It is obtained in the same way as for a classic cascade integrator-comb (CIC) implementation [11]. In other words, the numerator in (25) corresponds to the comb sections at the right of the decimator by 2 D, while the denominator is responsible for the integrator sections at the left of the decimator by D = 8. ...
This paper focuses on the design of multiplier-less decimation filters suitable for oversampled digital signals. The aim is twofold. On one hand, it proposes an optimization framework for the design of constituent decimation filters in a general multistage decimation architecture. The basic building blocks embedded in the proposed filters belong, for a simple reason, to the class of cyclotomic polynomials (CPs): the first 104 CPs have a z-transfer function whose coefficients are simply {-1,0,+1}. On the other hand, the paper provides a bunch of useful techniques, most of which stemming from some key properties of CPs, for designing the proposed filters in a variety of architectures. Both recursive and non-recursive architectures are discussed by focusing on a specific decimation filter obtained as a result of the optimization algorithm. Design guidelines are provided with the aim to simplify the design of the constituent decimation filters in the multistage chain.
... FPGA implementation and comparisons are briefly discussed in Sect. 4. Section 5 concludes this paper. ...
... This methodology reduces black and grey cells significantly. The sparse index (SPI) parameter is defined as SPI BW adder w/w A (4) where BW adder and w A indicate the bit width of the adder (here, adder represents ripple carry adder (RCA)) and the number of carriers, respectively. The number of black cells and grey cells can be computed as ...
... The highly efficient CIC filter is the second block of the DDC filter chain to reduce the large sampling rate [4]. The multi-stage CIC filter consists of integrators, followed by a programmable decimation factor and comb sections. ...
This paper presents a new method for implementing an efficient digital down converter (DDC) using a field-programmable gate array (FPGA) for software-defined radio standards. The DDC consists of a pipeline coordinate rotation digital computer (CORDIC) rotator to produce a complex waveform, followed by a cascade of multi-stage cascaded integrator comb (CIC) filter and a polyphase transposed finite impulse response (PTFIR) filter to reduce large sample rates with lowpass filtering. The canonical signed-digit encoding in the CORDIC architecture reduces many adders and shifters. The CIC filter works with a new polynomial function that reduces passband droop by 34.29% and stopband ripple by 41.35% when compared with the traditional approach. The proposed PTFIR filter considerably reduces delay units. Again, the adder is the basic functional unit of the DDC structure. In this brief, each component of the DDC is examined with hybrid parallel prefix adders. The presented HPPA utilizes less critical path delay and less area when compared to conventional structures. The design has been simulated in the Xilinx Vivado 2022.1, which implements the FPGA Kintex-7 device. According to comparison results, the proposed DDC reduces approximately 30.51% of the area-delay product and 29.32% of the power-delay product associated with the best design. A verification test certifies the functionality of the prototype architecture.
... The DDC is implemented using a Coordinate Rotation Digital Computer (CORDIC) fixed-point algorithm [11] and the decimator relies upon a Cascaded Integrator Comb (CIC) [12] filter with a final two-stage halfband Finite Impulse Response (FIR) filter [13] to steepen the overall frequency response. The combined filters enable integer decimation factors up to 500. ...
... Although the down-conversion and decimation filter algorithms (CORDIC and CIC) are implemented in 24-bit fixed-point arithmetic [14], the CIC filter offers only as little as 53 dB of stopband attenuation [12]. Therefore, we implemented single-precision floating-point down-conversion and FIR-based decimation on the host PC, so both DSP implementations can be directly compared (see Section V-A). ...
This paper addresses simultaneous, high-precision measurement and analysis of generic reference signals by using inexpensive commercial off-the-shelf Software Defined Radio hardware. Sine reference signals are digitally down-converted to baseband for the analysis of phase deviations. Hereby, we compare the precision of the fixed-point hardware Digital Signal Processing chain with a custom Single Instruction Multiple Data (SIMD) x86 floating-point implementation. Pulse reference signals are analyzed by a software trigger that precisely locates the time where the slope passes a certain threshold. The measurement system is implemented and verified using the Universal Software Radio Peripheral (USRP) N210 by Ettus Research LLC. Applying standard 10 MHz and 1 PPS reference signals for testing, a measurement precision (standard deviation) of 0.36 ps and 16.6 ps is obtained, respectively. In connection with standard PC hardware, the system allows long-term acquisition and storage of measurement data over several weeks. A comparison is given to the Dual Mixer Time Difference (DMTD) and Time Interval Counter (TIC), which are state-of-the-art measurement methods for sine and pulse signal analysis, respectively. Furthermore, we show that our proposed USRP-based approach outperforms measurements with a high-grade Digital Sampling Oscilloscope.
... The calculation of D T F R x ϕ becomes a recursive, sliding accumulator with distinct similarities to Cascaded Integrator-Comb filters (CIC) [43], involving a feed-forward and feedback portion, as shown in Fig. 2. CIC filters are guaranteed stable when implemented in fixed-point, rather than floating point, as the arithmetic operations are performed exactly [43]. ...
... The calculation of D T F R x ϕ becomes a recursive, sliding accumulator with distinct similarities to Cascaded Integrator-Comb filters (CIC) [43], involving a feed-forward and feedback portion, as shown in Fig. 2. CIC filters are guaranteed stable when implemented in fixed-point, rather than floating point, as the arithmetic operations are performed exactly [43]. ...
With the integration of distributed energy resources and the trend towards low-inertia power grids, the frequency and severity of grid dynamics is expected to increase. Conventional phasor-based signal processing methods are proving to be insufficient in the analysis of non-stationary AC voltage and current waveforms, while the computational complexity of many dynamic signal analysis techniques hinders their deployment in operational embedded systems. This paper presents the Functional Basis Analysis (FBA), a signal processing tool capable of capturing the full broadband nature of signal dynamics in power grids while maintaining a streamlined design for real-time monitoring applications. Relying on the Hilbert transform and optimization techniques, the FBA can be user-engineered to identify and characterize combinations of several of the most common signal dynamics in power grids, including amplitude/phase modulations, frequency ramps and steps. This paper describes the theoretical basis and design of the FBA as well as the deployment of the algorithm in embedded hardware systems, with adaptations made to consider latency requirements, finite memory capacity, and fixed-point precision arithmetic. For validation, a PMU calibrator is used to evaluate and compare the algorithm's performance to state-of-the-art static and dynamic phasor methods. The test outcomes demonstrate the FBA method's suitability for implementation in embedded systems to improve grid situational awareness during severe grid events.
... To minimize the on-chip area, the decimation filter is implemented as a Cascaded Integrator Comb (CIC) filter. This filter structure is a computationally efficient implementation of a narrow-band FIR low-pass filter that does not require multipliers, which greatly relaxes the area and power dissipation required to implement the CIC filter [16]. The implementation of the CIC filter is shown in Figure 8. Droop compensation as well as low-pass filtering are implemented off-chip in order to achieve the desired 30 kS/s sampling rate. ...
... In this case, the decimation factor for the pre-filter is 128. This leads to a required word width of 22 bits [16] in the prototype CIC filter. It is possible to shrink the word width as data progresses down the pipeline, but this was not completed here, because we determined that the possible reduction in area was small relative to the additional effort required. ...
The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.
... A low-pass filter operates by allowing low-frequency components to pass through while attenuating high-frequency components, effectively smoothing the image and reducing noise (Butterworth 1930;Hogenauer 1981). Building on the low-pass filter concept, the spatial neighboring filter uses information from a n × n kernel and a user-defined weighting matrix, Sw, to determine whether the center element should change its tree species code. ...
Improving tree species classification accuracy often involves complex workflows, constrained by high computational costs, extensive data requirements, and sensitivity to spatiotemporal variations. This study introduces the Change Resistance Filter (CR-Filter), inspired by the stable growth patterns of the Climax Community. The CR-Filter, applied as a post-processing tool, integrates Change Resistance on Timelines and Change Resistance on Spatial Neighboring into a unified framework, enhancing classification precision by mitigating spatiotemporal fluctuations. Liupan Mountain Nature Reserve was selected as the study area for its ecological stability. Multi-temporal Sentinel-2 data spanning several years were used to extract and correct phenological indices, which were combined with Sentinel-1 and terrain data to generate interannual tree species classification maps. These maps were subsequently refined using the CR-Filter. Compared to traditional methods, robustness in highly heterogeneous regions was improved by leveraging interannual map integration, yielding species distribution maps with greater spatial consistency and temporal stability. Overall accuracy increased by 8.44%, from 85.85% to 93.10%, effectively reducing misclassification from noise or transient changes. This approach highlights the CR-Filter’s efficacy with limited samples and medium-to-low resolution, providing strong technical support for remote sensing-based species mapping and ecological research.
... 2. Overview of Cic algorithm and cuda architecture 2.1. Cascaded integrator-comb (CIC) decimation lter Over two decades ago, Eugene B. Hogenauer rst introduced this concept [10], which has since been employed for both interpolation and decimation purposes [9]. Notably, it boasts a multiplier-free architecture, requiring minimal memory and hardware complexity, comprising solely of adders and delay elements. ...
The Cascaded Integrator Comb (CIC) decimation filter is a pivotal technology extensively employed in digital signal processing (DSP). This paper delves into a comprehensive examination of the CIC algorithm within software-defined radio (SDR) systems from the perspective of parallel computing and introduces a novel Non-Recursive Implementation (NR-I) on an NVIDIA GPU using CUDA. The NR-I approach significantly reduces computational load by unfolding the recursive CIC structure with pre-derived Unfold Factors. Further optimization was achieved through data-transfer enhancements using PM Implementation (PM-I) and ODT Implementation (ODT-I). Experimental results demonstrate that NR-I achieves a speedup of over 449.48. Additionally, the data-transfer optimizations resulted in substantial performance improvements, with PM-I and ODT-I reducing execution time by 43.24% and 64.22%, respectively. The GPU implementation’s speedup is significantly greater than that of OpenMP, ranging from 3.34 to 10.22 times. These results underscore the effectiveness of the proposed Non-Recursive Implementation in accelerating time-intensive and data-intensive computations.
... 4) Cascaded Integrator-Comb (CIC): As a baseline for the decimation stage we consider the Cascaded Integrator-Comb (CIC) filter proposed by Hogenauer [38] and used in [26]. This CIC filter used here is composed of a cascade of N = 6 integrators and comb filters. ...
Neural networks have become ubiquitous in audio effects modelling, especially for guitar amplifiers and distortion pedals. One limitation of such models is that the sample rate of the training data is implicitly encoded in the model weights and therefore not readily adjustable at inference. Recent work explored modifications to recurrent neural network architecture to approximate a sample rate independent system, enabling audio processing at a rate that differs from the original training rate. This method works well for integer oversampling and can reduce aliasing caused by nonlinear activation functions. For small fractional changes in sample rate, fractional delay filters can be used to approximate sample rate independence, but in some cases this method fails entirely. Here, we explore the use of signal resampling at the input and output of the neural network as an alternative solution. We investigate several resampling filter designs and show that a two-stage design consisting of a half-band IIR filter cascaded with a Kaiser window FIR filter can give similar or better results to the previously proposed model adjustment method with many fewer operations per sample and less than one millisecond of latency at typical audio rates. Furthermore, we investigate interpolation and decimation filters for the task of integer oversampling and show that cascaded half-band IIR and FIR designs can be used in conjunction with the model adjustment method to reduce aliasing in a range of distortion effect models.
... The resulting four-fold signals from the demodulation stage (G) are mathematically combined (H) in order to nearly suppress the unwanted frequency component of twice the modulation frequency (2ω 0 ) via phase cancelation, thus considerably reducing the amount of needed filter coefficients of the LPF stages (I). The LPF filter stages are realized as a decimating cascaded integrator comb (CIC) section [35], followed by a linear-phase, tapped-delay, multi-stage, moving average (MA) filter, in order to compensate for the non-flat, sin(x)/x-like magnitude response of the passband of the preceding CIC stages. ...
In this work, a highly sensitive, selective, and industrially compatible gas sensor prototype is presented. The sensor utilizes three distributed-feedback quantum cascade lasers (DFB-QCLs), employing wavelength modulation spectroscopy (WMS) for the detection of hydrogen sulfide (H2S), methane (CH4), methyl mercaptan (CH3SH), and carbonyl sulfide (COS) in the spectral regions of 8.0 µm, 7.5 µm, and 4.9 µm, respectively. In addition, field-programmable gate array (FPGA) hardware is used for real-time signal generation, laser driving, signal processing, and handling industrial communication protocols. To comply with on-site safety standards, the QCL sensor prototype is housed in an industrial-grade enclosure and equipped with the necessary safety features to ensure certified operation under ATEX/IECEx regulations for hazardous and explosive environments. The system integrates an automated gas sampling and conditioning module, alongside a purge and pressurization system, with intrinsic safety electronic components, thereby enabling reliable explosion prevention and malfunction protection. Detection limits of approximately 0.3 ppmv for H2S, 60 ppbv for CH3SH, and 5 ppbv for COS are demonstrated. Noise-equivalent absorption sensitivity (NEAS) levels for H2S, CH3SH, and COS were determined to be 5.93 × 10⁻⁹, 4.65 × 10⁻⁹, and 5.24 × 10⁻¹⁰ cm⁻¹ Hz−1/2. The suitability of the sensor prototype for simultaneous sulfur species monitoring is demonstrated in process streams of a hydrodesulphurization (HDS) and fluid catalytic cracking (FCC) unit at the project’s industrial partner, OMV AG.
... Then, we can replace the first-order CTSDM built around the second integrator, I nt2, by a VCO-based ADC, which is composed by a VCO acting as phase integrator, a phase quantizer, a sampler and a first difference block (See Fig. 2(c)). This replacement has been shown to be mathematically identical in [33]. In order to keep the same NTF as in Fig. 2(a), an extra feedback loop with gain 0.5 around the first-order VCO-ADC is needed, as shown in Fig. 2(c). ...
One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250
W occupying 0.095
in 130 nm CMOS.
... This is also an important property when trying to encode an analog signal into a digital pulse train. The second important component is a comb filtering stage [29] like those seen in cascaded integrator comb filters, both in classical and RSFQ applications, used for decimation and interpolation filter devices [30], [31]. This component is also seen in some pulse multiplier circuits [21]. ...
One of the most important and topical challenges of quantum circuits is their scalability. Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to single-flux-quantum-based on-chip devices that are directly connected to the quantum systems, it is possible to minimize the total system overhead, improving scalability and integration. In this article, we present a novel RSFQ device that generates multitone digital signals, based on complex pulse train sequences using a circular shift register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and read out arrays of quantum devices, such as qubits and single-photon detectors.
... от англ. Cascaded Integral-Comb Filters) [10]. CIC-фильтры обеспечивают децимацию сигнала с коэффициентом, равным степени двойки (2 ). ...
Relevance. The direct spread spectrum signals are widely used in navigation and communication systems recently. These signals prevail in modern satellite navigation systems and are used in various communication systems with code division multiplexing in particularly. In this regard, the tasks of building direct spread spectrum signals’ demodulators have the key importance. Mach importance in the construction of demodulators is the problem chip rate variability.
The purpose of the study is to propose a demodulator structure focused on solving this problem.
Methods. The research is based on computer modeling methods.
Decision. The paper proposes an approach to the construction of the direct spread spectrum signal’s demodulators based on modern methods of digital signal processing. It is shown that the main advantage of the proposed approach is the possibility of rebuilding the variable chip rate demodulators. Based on the results obtained, a scheme for the direct spread spectrum signals demodulator using resampling methods is proposed. Resampling, in turn, is implemented on the basis of polynomial interpolation using Lagrange polynomials. The structure of the resampler is proposed, similar to the structure of an interpolating filter with a finite impulse response. The presented simulation results show the effectiveness of the proposed approach.
Novelty . It seems that the currently common methods of implementing direct spread spectrum signal in terms of delay synchronization do not sufficiently meet modern requirements. The implementation of delay synchronization schemes based on resampling is practically not discussed in well-known works. At the same time, modern methods and devices of digital signal processing make it possible to ensure an effective hardware implementation of the scheme in question. In this context, the approach proposed in the paper to the construction of demodulators seems to be very relevant.
Significance. The results of the work can be used in the construction with direct spread spectrum signals’ demodulators for a wide range of communication and navigation systems. The synchronous sampling structure proposed in this paper is very promising, especially for variable chip rate demodulators.
... The v o SD bit-stream given by the Σ∆ − M needs to be down-sampled and filtered at very high rates to recover the SiPM signal in digital format. According with [40], the Cascade Integrator Comb (CIC) filter presents the best response at high frequencies or high data rate decimation process. Equation 23 describes the CIC transfer function in the Z domain, where S is the number of cascaded integrators and Comb filters, D is the delay required by the Comb filter, and R is the down-sampling factor. ...
This work describes MexSIC, a data acquisition channel designed for Silicon Photomultipliers (SiPMs), composed of a mixed-mode application specific integrated circuit (ASIC) front-end, an FPGA-based processing stage, and a user interface. The ASIC provides a 1-bit sigma-delta modulated (ΣΔ –
M
) digital equivalent of the input SiPM current, a flag indicating the start/end of the SiPM pulse, and a clock reference generated by an internal Phase Locked Loop (PLL). At the ASIC input stage, the SiPM current is converted to voltage by means of a 1.57 GHz bandwidth transimpedance amplifier (TIA), the gain of which can be switched between 21 dB and 48 dB, allowing for an input current range between 20
μ
A and 20 mA. The generated voltage signal is then fed to a Triggering Unit (TU) implemented to discriminate between desired signals and the spurious ones, and in parallel, also to a second-order ΣΔ modulator providing 6.1 Equivalent Number Of Bits (ENOB). The TU circuit sends a start/end bit flag by comparing the SiPM voltage signal with an 8-bit programmable voltage reference. The ΣΔ was selected to have a single output line instead of using a data bus with many lines, which is important in applications where the number of SiPM channels being read out is very large. The 10 MHz bandwidth ΣΔ –
M
uses an Over Sampling Ratio (OSR) of 50, and a 1 GHz sampling clock that is generated by a PLL using an off-chip 100 MHz reference. The FPGA receives the ASIC ΣΔ modulated output signal and performs a decimation process by means of a Cascade Integrator Comb (CIC) filter to complete the data recovery. The recovered signal is visualized in a Matlab programmed Graphical User Interface (GUI). The MexSIC ASIC was designed in a 180 nm CMOS standard process using Cadence
©
software, and the processing stage was implemented in a Kintex-7 FPGA.
... The first stage of the digital filter is a CIC or Hogenauer filter [12] providing a factor 2048 of decimation, resulting in an output frequency of 12.2 kHz. CIC filters are implemented using only adders, subtracters, registers, and delays. ...
An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology experiments with the primary goal of measuring the signature of inflation with the Cosmic Microwave Background Radiation. The system consists of analog superconducting electronics running at 250mK and 4K, coupled to digital room temperature backend electronics described here. The digital electronics perform the real time functionality with DSP algorithms implemented in firmware. A soft embedded processor provides all of the slow housekeeping control and communications. Each board in the system synthesizes multi-frequency combs of 8 to 32 carriers in the MHz band to bias the detectors. After the carriers have been modulated with the sky-signal by the detectors, the same boards digitize the comb directly. The carriers are mixed down to base-band and low pass filtered. The signal bandwidth of 0.050 Hz - 100 Hz places extreme requirements on stability and requires powerful filtering techniques to recover the sky-signal from the MHz carriers.
... For instance, for uplink CPRI signals, different propagation path loss, shadowing, fading channel and mobility for different users may result in significant variance in general. Block Scaling, also known as automatic gain control (AGC), is employed to lower the resolution of signal and to maintain the dynamic range simultaneously [5] [21]. ...
The future wireless network, such as Centralized Radio Access Network (C-RAN), will need to deliver data rate about 100 to 1000 times the current 4G technology. For C-RAN based network architecture, there is a pressing need for tremendous enhancement of the effective data rate of the Common Public Radio Interface (CPRI). Compression of CPRI data is one of the potential enhancements. In this paper, we introduce a vector quantization based compression algorithm for CPRI links, utilizing Lloyd algorithm. Methods to vectorize the I/Q samples and enhanced initialization of Lloyd algorithm for codebook training are investigated for improved performance. Multi-stage vector quantization and unequally protected multi-group quantization are considered to reduce codebook search complexity and codebook size. Simulation results show that our solution can achieve compression of 4 times for uplink and 4.5 times for downlink, within 2% Error Vector Magnitude (EVM) distortion. Remarkably, vector quantization codebook proves to be quite robust against data modulation mismatch, fading, signal-to-noise ratio (SNR) and Doppler spread.
... This is also an important property when trying to encode an analogue signal into a digital pulse train. The second important component is a Comb Filtering stage [27] like those seen in Cascaded-Integrator-Comb filters, both in classical and RSFQ applications, used for decimation and interpolation filter devices [28], [29]. This component is also seen in some pulse multiplier circuits [19]. ...
One of the most important and topical challenges of quantum circuits is their scalability. Rapid Single Flux Quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to SFQ-based on-chip devices that are directly connected to the quantum systems, it is possible to minimise the total system overhead, improving scalability and integration. In this work, we present a novel RSFQ device that generates multi tone digital signals, based on complex pulse train sequences using a Circular Shift Register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and readout arrays of quantum devices, such as qubits and single photon detectors.
... The sampling rate should be sufficiently high to meet this requirement, meaning the DSP system should operate with an adequate oversampling ratio (OSR). At low OSRs, the filter coefficients need to be adjusted, and if the sampling rate is too low, it could be upsampled in the frontend and downsampled at the backend of the DSP, by cascaded integrator-FDFs, i.e. by MAFs [24]. ...
Intuitive engineering is a valuable skill that empowers engineers to effectively tackle problems using straightforward methodologies and simple calculations, rather than relying solely on complex techniques and higher mathematics. Recently, a comprehensive foundation for intuitive active digital filter (ADF) design has been published in a two-part series. Part I introduced the fundamental principles of first-order ADFs, demonstrating their application in designing low-pass, high-pass, band-pass, and band-rejection filters. Part II further explored the design of higher-order low-pass filters (LPFs), serving as a guide for the design strategy of high-pass filters (HPFs). This article continues the series on ADF design by focusing on second and higher-order active HPFs. Similar to Part II, popular filter approximations, such as Bessel, Butterworth, and Chebyshev are discussed and compared to their analog Sallen-Key counterparts. Additionally, second-order active high-pass filtering of electrocardiogram (ECG) signals is demonstrated, indicating its better ability to suppress baseline drift from ECG signals.
... When k is close to one, the integrator's gain G is significantly reduced, leading to considerable deviations in filter parameters such as gain, f c , and Q from their nominal values when G >> 1. In practice, G can be augmented by increasing the sampling rate, for example, by upsampling at the frontend and downsampling at the backend of the filtering routine [18]. However, this approach should be considered as a final resort when f c is close to or higher than the MGP. ...
The recently developed intuitive approach to active digital filter (ADF) design represents a straightforward and efficient method for designing digital filters. This approach explores the similarity between digital integrators and operational amplifiers in analog filter design. By connecting digital integrators as signal followers, first-order ADFs are implemented. By inserting first-order ADFs into the feedback loop of another ADF, second-order or biquadratic ADFs (biquads) are created. Cascading multiple biquads allows the construction of higher-order filters. This paper, Part IV of the series, focuses on the design of active biquads as fundamental filtering stages in ADF design. A universal biquad architecture, capable of simultaneously generating low-pass, high-pass, band-pass, and band-tejection responses, is introduced and thoroughly examined. Special attention is given to the use of positive feedback as an approach to increase the Q-factor in bandpass biquads. Finally, the application of biquad notch filtering to suppress 50 Hz power-line interference in electrocardiogram signals is demonstrated.
... To facilitate multiple applications, the output of the ADC is passed to be an adjustable down sampler. The down sampler is based on a CIC filter architecture [27]. By having an adjustable down sampler, the ADC can support a variety of chopping frequencies and adjustable output frequencies. ...
Early prediction of seizures and timely interventions are vital for improving patients' quality of life. While seizure prediction has been shown in software-based implementations, to enable timely warnings of upcoming seizures, prediction must be done on an edge device to reduce latency. Ideally, such devices must also be low-power and track long-term drifts to minimize maintenance from the user. This work presents SPIRIT: Stochastic-gradient-descent-based Predictor with Integrated Retraining and In situ accuracy Tuning. SPIRIT is a complete system-on-a-chip (SoC) integrating an unsupervised online-learning seizure prediction classifier with eight 14.4 uW, 0.057 mm2, 90.5 dB dynamic range, Zoom Analog Frontends. SPIRIT achieves, on average, 97.5%/96.2% sensitivity/specificity respectively, predicting seizures an average of 8.4 minutes before they occur. Through its online learning algorithm, prediction accuracy improves by up to 15%, and prediction times extend by up to 7x, without any external intervention. Its classifier consumes 17.2 uW and occupies 0.14 mm2, the lowest reported for a prediction classifier by >134x in power and >5x in area. SPIRIT is also at least 5.6x more energy efficient than the state-of-the-art.
... The CIC filter (CIC1 in figure 2(b)) is a 3rd with a programmable decimation factor N CIC1 [27]. This type of filter, typically employed in telecommunication applications, has several advantages. ...
A high sensitivity Magneto-Impedance (GMI) sensor for magnetic communication systems in harsh environments is presented. In this system, the receiving coil of a conventional magnetic communication system is replaced by a high sensitivity GMI sensor and its digital electronic conditioning as well as digital signal processing. The whole architecture of the sensor is described in detail. It achieves two digital amplitude demodulations to recover, in real time, the binary sequence of the message sent by the transmitter. The demonstration and the validation of the reliable functioning of the system are illustrated through the transmission of messages using On-Off-Keying modulation method. The measured equivalent magnetic noise of the sensor was about noise 2 pT/Hz at 60 kHz, which is largely lower than the noise of other potential types of magnetic sensors such as Anisotropic Magneto-Resistive sensors for this application. This noise level suggests a potential higher communication range. When compared with an inductive coil, the developed sensor also presented an almost flat and sufficiently wide bandwidth compatible with magnetic communication. This bandwidth could potentially be extended according to the application.
... The baseline variations of the different PMTs are clearly visible. In order to reduce the sensitivity to baseline variations, the waveforms are processed by digital Finite-Impulse-Response (FIR) filters [20] which perform signal integration and baseline subtraction. ...
The Data Acquisition System (DAQ) for the LUX-ZEPLIN (LZ) dark matter detector is described. The signals from 745 PMTs, distributed across three subsystems, are sampled with 100-MHz 32-channel digitizers (DDC-32s). A basic waveform analysis is carried out on the on-board Field Programmable Gate Arrays (FPGAs) to extract information about the observed scintillation and electroluminescence signals. This information is used to determine if the digitized waveforms should be preserved for offline analysis. The system is designed around the Kintex-7 FPGA. In addition to digitizing the PMT signals and providing basic event selection in real time, the flexibility provided by the use of FPGAs allows us to monitor the performance of the detector and the DAQ in parallel to normal data acquisition. The hardware and software/firmware of this FPGA-based Architecture for Data acquisition and Realtime monitoring (FADR) are discussed and performance measurements are described.
... Due to the inherent nonlinearity of IDSC, various studies have focused on the optimal decoding scheme implemented as a general digital filter. Currently, there are some traditional linear digital filters have been applied to IDSCs, such as the linear cascade of integrator (COI 1 ,COI 2 ,COI 3 etc) and the sinc L filter [4,5,11,21]. Although the implementations of these filters are simple, there is still ample room for improvement in their performance. ...
This paper introduces a novel algorithm for optimizing the coefficients of the digital filters used in incremental delta-sigma analog-to-digital converters (IDSC). This algorithm is modified from constrained linear least squares (LS) to improve the signal-to-noise-and-distortion ratio (SNDR) of IDSC and minimize the oversampling rate (OSR) of the modulator, which enhances system speed and reduces power consumption. In the case of the same SNDR, the first-order IDSC with the proposed filter can reduce the OSR of the modulator by 50%, at least compared to the IDSC with the conventional filter. The second-order IDSC with the proposed filter can reach a higher SNDR of 106 dB with an OSR of 64. Considering the nonlinearity of the integrator, the SNDR of IDSC with the proposed filter is also 10 dB greater than that of the conventional filters and 3dB greater than that of the IDSC using the near-optimal algorithm filter. The experimental results indicate that the proposed filter possesses an excellent figure of merit of 0.028 pJ/conv.
... References (44)(45)(46)(47)(48)(49)(50)(51)(52)(53)(54)(55)(56)(57)(58)(59)(60)(61) ...
Textile sensors transform our everyday clothing into a means to track movement and bio-signals in a completely unobtrusive way. One major hindrance to the adoption of "smart" clothing is the difficulty encountered with connections and space when scaling up the number of sensors. There is a lack of research addressing a key limitation in wearable electronics: connections between rigid and textile elements are often unreliable and they require interfacing sensors in a way incompatible with textile mass production methods. We introduce a prototype garment, compact readout circuit, and algorithm to measure localized strain along multiple regions of a fibre. We employ a helical auxetic yarn sensor with tunable sensitivity along its length to selectively respond to strain signals. We demonstrate distributed sensing in clothing, monitoring arm joint angles from a single continuous fibre. Compared to optical motion capture, we achieve around 5°error in reconstructing shoulder, elbow, and wrist joint angles.
... The proposed method can be used as a time modulation method to implement jitter control on pattern data to realise the generation of digital signals carrying standard jitter sources [21,22]. Digital and the analogue filters were combined, and the step-by-step transmission of the high timing resolution of the sample points was achieved by filtering the spurious signals using the zero-order hold sampling of the DAC [23]. Improved pulse width resolution can enhance PWM. ...
... While cascade of integrator (COI) reconstruction filters are the most popular choice for higher-order I-ADC due to their simple implementation and superior performance compared to other filter structures [55], [58]- [60], they suffer from poor out-of-band suppression. To avoid folding of strong chopping artifacts, we implemented a 2 nd order cascaded integratorcomb (CIC) decimation filter [61]. While this reconstruction filter results in worse signal-to-quantization-noise ratio (SQNR) than a COI filter of the same order at the same OSR on I-ADCs, its frequency response features notches offering significant suppression at dedicated out-of-band frequencies. ...
This paper presents the system architecture for an implant concept called
NeuroBus
. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344 μm x 294 μm) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility. We introduce the architecture, the integrated building blocks, and the post-CMOS processes required to realize a
NeuroBus
, and we characterize the prototyped direct digitizing neural recorder front-end as well as polyimide-based ECoG brain interface. A rodent animal model is further used to validate the joint capability of the recording front-end and thin-film electrode array.
... The CIC filter is placed in the second stage due to its highspeed processing [16]. It removes the adjacent channels and produces a linear phase response signal. ...
This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system’s validity.
... The conventional way of implementing these interpolators and decimators is to use a series of high-order FIR filters, which has the drawback of having high hardware complexity due to the large number of multiplications. In 1981, Hogenauer [1] introduced a novel class of costeffective digital filters for decimation, known as Cascaded Integrator Comb filters (CIC). These filters operate without multipliers and do not require storage for filter coefficients. ...
This article offers a summary of the approaches used in the design of Cascaded-Integrator Comb (CIC) filters, focusing on their implementation in Field Programmable Gate Arrays (FPGAs). Because of its simplicity, computational efficiency, flexibility for high-speed data handling, and features such as anti-aliasing, interpolation, and noise reduction, CIC filters play an essential role in multi rate signal processing. This study examines current research efforts aimed at improving the performance of CIC filters, such as signal integrity, signal-to-noise ratio (SNR), passband droop, and compensation designs. This paper also portrays a comparative analysis of several parameters such as adders, multipliers, registers utilized, and also Adders per output sample (APOS) and minimum attenuation based on various papers that have similar functionalities but vary in methodologies employed, that affect the overall performance while implementing in hardware.
In the field of motivation, incentives are seen as a means of motivating people. Incentives are usually applied in the form of a scheme, such as piece-rate and fixed-rate monetary rewards. Since the field of knowledge management involves a certain measure of motivation, a number of organizations have used incentives to encourage their employees to share knowledge. Research to date concerning the role of incentives in knowledge sharing seems to contradict one another. Furthermore, when an incentive is sufficiently large, some individuals are inspired to increase their performance to reflect the incentive received (London & Oldham, 1976). Along with this negative disposition, intrinsically motivated individuals would experience a deterioration of such motivation due to the introduction of incentives, thus jeopardizing the whole knowledge sharing initiative (Deci, Koestner, & Ryan, 1999; Jordan, 1986). Some research (Bock & Kim, 2002; O’Dell & Grayson, 1998) has suggested a trigger effect that comes from implementing incentives. Empirical evidence concerning the long-term effects of incentives in the field of knowledge sharing is also lacking (Fossum, 1979; O’Dell & Grayson). This research seeks to consolidate the many different views of past research, investigating areas that are lacking. Is it possible to consolidate the different views of incentives in knowledge sharing? Are there differences between having fixed-rate, piece-rate, or no incentive schemes in knowledge sharing initiatives? Do incentives exhibit a triggering effect in motivating individuals to share their knowledge? Would the removal of incentives after the trigger period affect a knowledge sharing initiative? Will the continual increase of incentives remain effective in the long term for knowledge sharing initiatives? These research questions will be answered as the article progresses.
This study presents the design of an innovative, compact, and wearable device for continuous monitoring of phonocardiogram (PCG) and electrocardiogram (ECG) waveforms. Aimed at regular usage, this device enables users to effortlessly monitor their heart health, providing real-time data on cardiac function. By combining PCG and ECG monitoring, the device provides a comprehensive view of the heart's electrical and acoustic activity, which is essential for early detection of potential cardiac issues. Notable attributes of the device include continuous monitoring, wireless data transmission, and noise reduction technology to ensure high-quality signal acquisition. A user-friendly interface makes it accessible to a wide range of users, while built-in data analysis and archiving capabilities allow for long-term tracking and evaluation of heart health. The device can integrate with other health monitoring systems, allowing for a more holistic approach to patient care. Furthermore, this design offers significant opportunities for research and development in the field of predictive cardiac healthcare. By utilizing advanced algorithms and machine learning, the system can analyze heart sound patterns and detect abnormalities that may not be easily identified through conventional methods. Ultimately, this wearable system aims to improve early diagnosis, personalized treatment, and overall management of cardiac health.
Analog electrical elements such as mixers, filters, transfer oscillators, isolating buffers, dividers, and even transmission lines contribute technical noise and unwanted environmental coupling in time and frequency measurements. Software defined radio (SDR) techniques replace many of these analog components with digital signal processing (DSP) on rapidly sampled signals. We demonstrate that, generically, commercially available multi-channel SDRs are capable of time and frequency metrology, outperforming purpose-built devices by as much as an order-of-magnitude. For example, for signals at 10 MHz and 6 GHz, we observe SDR time deviation noise floors of about 20 fs and 1 fs, respectively, in under 10 ms of averaging. Examining the other complex signal component, we find a relative amplitude measurement instability of 3e-7 at 5 MHz. We discuss the scalability of a SDR-based system for simultaneous measurement of many clocks. SDR's frequency agility allows for comparison of oscillators at widely different frequencies. We demonstrate a novel and extreme example with optical clock frequencies differing by many terahertz: using a femtosecond-laser frequency comb and SDR, we show femtosecond-level time comparisons of ultra-stable lasers with zero measurement dead-time.
The need for a high-performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize the latest technique identified as oversampling systems. It was the most economical modulator and decimation in the communication system. It has been proven to increase the SNR and is used in many high-performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and it's VLSI implementation which was the sub-component in the oversampling technique. The design and realization of the main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half-band filters, and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted in power and area measurement on-chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308 x 0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.
In space gravitational wave detection, the CIC (Cascaded Integrator–Comb) antialiasing filter is always utilized for the down-sampling of phasemeter. However, the passband of CIC filter is not flat, which means that the attenuation is not the same at different frequencies. Therefore, in fields that require high accuracy of phase true value, such as differential wavefront sensing, the traditional down-sampling method is not applicable. In this paper, the filter of CIC-ISOP (Interpolated Second-Order Polynomials) architecture is developed for the compensation of the attenuation effect. A phasemeter is also developed for the experimental demonstration. The results show that the passband attenuation at 1 Hz reduces from 0.1076dB to 3.86×10
-4
dB, significantly reducing the droop in the passband. The noise performance of the phasemeter is also tested, which can reach the level of 2πμrad/Hz
1/2
.
A novel down-sampling filter named moving accumulative sign filter (MASF) is proposed for low-power down-sampling of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages than state-of-the-art cascaded-integrator-comb (CIC) filter, especially in the area of low-power design. The theory of MASF is proposed and introduced comprehensively, including the algorithm model, transfer function, and frequency response characteristics. The pipeline voting architecture is applied to the implementation of the MASF to improve the speed of data processing, which simplifies the circuit structure and reduce the power consumption. The MASF circuits of general application based on pipeline voting are designed for binary and ternary signals only using D flip-flop and logic gates. The area and power consumption of MASF are reduced by 86% and 88% compared with CIC filter under the same conditions on FPGA. What’s more, a hardware-friendly pooling algorithm named polar-pooling is proposed based on MASF for binary and ternary feature maps, which greatly reduces the time and space complexity of pooling. Compared with max-pooling and average-pooling, the processing time of polar-pooling is reduced by more than 75% for a
binary image. The two-stage MASF circuit for ternary signal processing is implemented at 40-nm CMOS process, compared with state-of-the-arts cascade-of-integrators filter which cascading two integrators, the normalized power consumption of proposed two-stage MASF circuit has 67% reduction and the area has 75% reduction.
Textile sensors transform our everyday clothing into a means to track movement and biosignals in a completely unobtrusive way. One major hindrance to the adoption of “smart” clothing is the difficulty encountered with connections and space when scaling up the number of sensors. There is a lack of research addressing a key limitation in wearable electronics: Connections between rigid and textile elements are often unreliable, and they require interfacing sensors in a way incompatible with textile mass production methods. We introduce a prototype garment, compact readout circuit, and algorithm to measure localized strain along multiple regions of a fiber. We use a helical auxetic yarn sensor with tunable sensitivity along its length to selectively respond to strain signals. We demonstrate distributed sensing in clothing, monitoring arm joint angles from a single continuous fiber. Compared to optical motion capture, we achieve around five degrees error in reconstructing shoulder, elbow, and wrist joint angles.
The Delta Sigma modulation technology has been around for a while, but because of technological advancements, the devices are now more widely used and feasible. The work proposes a multi-bit Delta Sigma ADC of second order having a very low power consumption. MATLAB Simulink is used to develop both the Delta Sigma ADCs of first and second order and the digital output is passed through a digital filter to recreate the original signal. According to simulation results, at 100 KHz frequency of output sampling, the Delta-Sigma modulator exhibits a Spurious Free Dynamic Range of 95.38 dB, and also it demonstrates that the designed Delta-Sigma ADC is capable of achieving an ENOB (Effective Number of Bits) of 11.83 bits and an SNR of 72.99 dB.
In this paper a general theory of multistage decimators and interpolators for sampling rate reduction and sampling rate increase is presented. A set of curves and the necessary relations for optimally designing multistage decimators is also given. It is shown that the processes of decimation and interpolation are duals and therefore the same set of design curves applies to both problems. Further, it is shown that highly efficient implementations of narrow band finite impulse response (FIR) filters can be obtained by cascading the processes of decimation and interpolation. Examples show that the efficiencies obtained are comparable to those of recursive elliptic filter designs.
Filtering is necessary in decimation (decreasing the sampling rate of) or interpolation (increasing the sampling rate of a digital signal. If the rate change is substantial, the process is more efficient when the decimation or interpolation occurs in stages rather than in one step. Half-band filters are particularly efficient for effecting octave changes in sampling rate and nine digital filters are presented, eight of them half-band filters, to be used as components of multistage interpolators and decimators. Also presented is a procedure for combining the filters to produce multistage designs that meet a very wide range of accuracy requirements (stopband attenuation to 77 dB, passband ripple as low as 0.00014). The nine filters admit changes between sampling rates above 4W, where W is the nominal bandwidth of the signal. Established design techniques may be used to obtain efficient filters for conversion between 4W Hz sampling and 2W Hz, the "baseband sampling rate." With these multistage filters, the possible interpolation and decimation ratios are all integer multiples of powers of two. To overcome this restriction we present a simple resampling technique that extends the range of designs to conversions between any two rates. The interpolation or decimation ratio need not be an integer or even rational. In fact, it can vary slightly as in a practical situation where the input signal and output signal are under the control of autonomous clocks. We demonstrate the approach by means of several design examples and compare its results with those obtained from the optimization scheme of Crochiere and Rabiner.
In this paper several issues concerning the design and implementation of multistage decimators, interpolators, and narrow-band filters are discussed. In particular, the question of designing these systems in terms of minimum storage rather than minimum computation rate is examined. It is shown that a design which uses finite impulse response (FIR) filters for each stage, and which is minimized for storage is essentially minimized in terms of computation rate as well. The problem of further improvements in designing decimators and interpolators by taking advantage of DON'T CARE frequency bands is also discussed. For the early stages in a multistage design it is shown that fairly significant reductions in filter order can be achieved in this manner. A third issue in the design process is the question of practical schemes for efficient implementation of multistage decimators and interpolators in both hardware and software. One such efficient implementation is discussed in this paper. Finally, the problem of designing multistage decimators and interpolators using elliptic infinite impulse response (IIR) filters is discussed. It is shown that multistage IIR designs can be somewhat more efficient computationally than single-stage designs; however, the storage efficiency of the multistage IIR design is worse than that of the single-stage IIR design.
In this paper a general theory of multistage decimators and interpolators for sampling rate reduction and sampling rate increase is presented. A set of curves and the necessary relations for optimally designing multistage decimators is also given. It is shown that the processes of decimation and interpolation are duals and therefore the same set of design curves applies to both problems. Further, it is shown that highly efficient implementations of narrow-band finite impulse response (FIR) filters can be obtained by cascading the processes of decimation and interpolation. Examples show that the efficiencies obtained are comparable to those of recursive elliptic filter designs.
In an earlier paper Crochiere and Rabiner [1] discuss the theory of using finite impulse response (FIR) digital filters for signal decimation, interpolation, and filtering. In this paper we expand on the ideas presented in the earlier paper on implementing narrow-band designs efficiently. It is shown how, using the techniques of decimation and interpolation, a desired narrow-band filter can be realized with a greatly reduced number of multiplications per second in the realization over standard direct form implementations. Further, it is shown that the proposed implementation can have less roundoff noise and less severe coefficient sensitivity problems than a standard direct form implementation. Several examples are presented to illustrate the applicability of this implementation to practical design problems.
A new approach to the implementation problem of digital filters is presented. This approach capitalizes on recent advances in semiconductor memory technology and is shown to offer significant reductions in cost and power consumption for the same speed of operation as that of existing realizations. Furthermore, this approach makes possible speeds of operation which cannot be achieved by existing realizations. The proposed approach yields a very flexible hardware configuration and a discussion of the various options is presented together with a comparison to existing realizations. The mean-squared error resulting from the use of finite word length is analyzed.