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# Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited

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Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.
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INVITED Cryo-CMOS Electronic Control
for Scalable Quantum Computing
Fabio Sebastiano
1
, Harald Homulle
1
, Bishnu Patra
1
, Rosario Incandela
1
, Jeroen van Dijk
1
,
Lin Song
1,2
, Masoud Babaie
1
1,3
, Edoardo Charbon
1,4,5
1
Delft University of Technology, Delft, The Netherlands,
2
Tsinghua Univ., Beijing, P.R. China,
3
U.C. Berkeley, Berkeley,
CA, U.S.A.
4
Intel Corp., Hillsboro, OR, U.S.A.,
5
EPFL, Neuchâtel, Switzerland
f.sebastiano@tudelft.nl
ABSTRACT
Quantum computers
1
could revolutionize computing in a profound
way due to the massive speedup they promise. A quantum
computer comprises a cryogenic quantum processor and a
classical electronic controller. When scaling up the cryogenic
quantum processor to at least a few thousands, and possibly
millions, of qubits required for any practical quantum algorithm,
cryogenic CMOS (cryo-CMOS) electronics is required to allow
feasible and compact interconnections between the controller and
the quantum processor. Cryo-CMOS leverages the CMOS
fabrication infrastructure while exploiting the continuous
improvement of performance and miniaturization guaranteed by
Moore’s law, in order to enable the fabrication of a cost-effective
practical quantum computer. However, designing cryo-CMOS
integrated circuits requires a new set of CMOS device models,
their embedding in design and verification tools, and the
possibility to co-simulate the cryo-CMOS/quantum-processor
architecture for full-system optimization. In this paper, we address
these challenges by focusing on their impact on the design of
complex cryo-CMOS systems.
CCS CONCEPTS
Hardware Quantum computation; Electronic design
automation; Analog and mixed-signal circuits; Application
specific integrated circuits.
KEYWORDS
Cryo-CMOS, cryogenics, quantum computation, qubit, error-
correcting loop, device models.
1 INTRODUCTION
Quantum computers hold the promise to successfully address
computational problems that are intractable by standard
computing paradigms. These problems include efficient search in
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DAC '17, June 18-22, 2017, Austin, TX, USA
© 2017 ACM. ISBN 978-1-4503-4927-7/17/06…$15.00 DOI: http://dx.doi.org/10.1145/3061639.3072948 extremely large datasets, factorization of large integers in their prime factors and simulations of quantum systems for the optimization of drug synthesis, materials and industrial chemical processes [1]. In a quantum computer, standard logic bits are replaced by quantum bits (qubits), which can be represented as a point on the surface of a three-dimensional sphere, the so-called Bloch sphere, shown in Figure 1. In this construct, standard logic ‘1’ and ‘0’ are replaced by quantum states |0 and |1, and are manipulated, so as to exploit the fundamental phenomena of quantum mechanics for computation, i.e. superposition and entanglement [2]. Qubits can exist in a superposition of both state |0 and |1 simultaneously, which results in a computing power that doubles with every additional qubit, thus resulting in a massive speedup with respect to traditional computers. For example, it has been estimated that the state of a 50-qubit system cannot be stored in the memory of the world’s most powerful computers today [3]. In addition to a quantum processor comprising several qubits, a quantum computer also requires a classical controller to manipulate and read out qubit states (Figure 2). Classical controller and quantum processor must be placed in close proximity, because of the need for physical interconnections between them. This requirement will be especially stringent when the number of qubits, and hence the wires connecting them, will grow to very large numbers. Since most quantum processors nowadays require operation at deep-cryogenic temperature well below 1 K, such as in the examples shown in Figure 2, the Figure 1. Bloch sphere representation of a qubit. 2 classical controller must also operate at cryogenic temperature. To address this issue, a cryogenic CMOS (cryo-CMOS) electronic controller has been proposed [4]-[7]. The controller must satisfy stringent requirements on noise, accuracy, and bandwidth, in order not to reduce qubit performance, and to comply with power dissipation limits imposed by the cooling technology. Meeting those demands requires effort and innovations both in the development of new system and circuit architectures and in the creation of novel design and verification strategies and tools. In regard to design tools, few topics require specific attention: the co-simulation of the electronic interface with the quantum processor for a full system optimization; the need for models of CMOS devices operating at cryogenic temperature and their embedding in commercial EDA tools to enable the design of complex circuits and systems. In this paper, we focus on those challenges and their impact on the design of complex cryo-CMOS circuits. The paper is organized as follows. The motivations and the requirements for the cryo-CMOS controller are presented in section 2. Section 3 and 4 discuss the challenges for the development of the quantum- processor/controller co-simulations and cryo-CMOS device models, respectively, while remarks on cryo-CMOS design automation occupy section 5. Conclusions are drawn in section 6. 2 THE NEED FOR CRYO-CMOS CONTROL Several physical implementations have been proposed for qubits, however solid-state alternatives are currently the most promising in terms of scalability to a large number of qubits, although no more than a dozen qubits have been demonstrated in such platforms so far [8]. Solid-state qubits come in several variants, such as electron spins in quantum dots, superconducting circuits, and nitrogen-vacancies in diamond lattices [9]-[20]. A common feature of most of those technologies is the required operation at deep-cryogenic temperatures, typically below 100 mK. This is required both to expose their quantum behavior and to increase the coherence time of their quantum state. The coherence time is usually far below a second, that is a time frame much shorter than what is required for the execution of any practical quantum algorithms. Consequently, to counteract the loss of the quantum state, quantum error-correction techniques have been developed to exploit information redundancy by encoding the quantum information on a large number of qubits, thus trading off simplicity for fidelity in execution of the quantum algorithm [21]. Thus, although a quantum computer with 50 logical qubits can already exceed the memory capabilities of today’s supercomputers and non-trivial quantum chemistry problems can be solved with the availability of just 100 logical qubits [22], thousands, or even millions, of physical qubits, i.e. the real physical devices, are required to enable practical quantum computation. The classical controller in Figure 2 must serve this large number of qubits by taking care of the execution of the quantum algorithm and, in parallel, by implementing an error-correction loop intended to maintain the fidelity of the computation beyond coherence times. Interfacing solid-state qubits usually involves the generation and acquisition of purely electrical signals, such as microwave bursts with frequencies ranging from a few GHz to tens of GHz and voltage and current pulses with a bandwidth of tens of MHz. Since existing state-of-the-art quantum processors comprise only a few qubits, most of the electronics making up the classical controller operate at room temperature and it is wired to the qubits in the cryogenic chamber. Only a few functionalities, such as low- noise amplification of read-out signals and attenuation of control signals, are implemented at cryogenic temperature in close proximity to the quantum processors. However, when scaling up the number of qubits to the large number required for any practical computation, this approach may incur a number of limitations, including the thermal load of the large number of cables, or the latency of the error-correction loop [23]. Although there is not yet a general consensus about whether those limitations are critical or may be circumvented in the near future, it is clear that wiring thousands of low-frequency and high- frequency wires from room temperature to the cryogenic quantum processor would lead to an extremely expensive, bulky, unreliable and, hence, unpractical quantum computer. As an alternative, a cryogenic controller may be employed, in order to relieve the requirements on interconnections, system size and reliability. Several technologies have demonstrated functionality at cryogenic temperature, such as junction field- effect transistors (JFET), high-electron-mobility transistors (HEMT), superconducting devices based on Josephson junctions, compound semiconductors (e.g. GaAs) and CMOS transistors [24][25]. However, by relying on the progress of the semiconductor industry, only CMOS technology can ensure low power consumption and functionality down to 30 mK [7][26], while offering the integration of billions of transistors on a single chip, as it will be required to handle the complexity of future quantum processors. Moreover, CMOS is preferred also because the design automation infrastructure is very mature for the standard industrial and military temperature ranges, i.e. down to -55 °C. Figure 3 shows a generic platform for control and read-out of a quantum processor. It comprises a frontend for (de)multiplexing, amplification, analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for the analog signals coming from and Figure 2. Quantum-classical interface. 3 feeding to all qubits. Ideally, quantum processors and electronics should operate at the same temperature, if not even on the same chip, to eliminate the need for any off-chip interconnect. However, currently available refrigeration technologies limit the available cooling power to less than ~1 mW at temperature below 100 mK [28], and it is unlikely that the full electronic controller can operate with such power budget in the near future. On the contrary, a cooling power exceeding 1 W is usually available at the 4-K stage, thus allowing the majority of the electronics to operate there. A limited amount of low-power electronics, including (de)multiplexers to reduce the number of connections to the 4-K stage, is envisioned to operate at the same temperature as the quantum processor, as shown in Figure 3. The specifications for the cryo-CMOS electronic controller are extremely challenging. To ensure the target performance in the quantum processor, electronic signals driving the qubits must be highly accurate (in terms of amplitude, timing, frequency and phase) and contribute a negligible amount of noise. As a comparison, the control of state-of-the-art quantum processors is achieved by using the most accurate (and expensive) bench-top electronic instrumentation available on the market [9]-[20]. The read-out must be very sensitive to detect the weak signals from the quantum processor [6], and to ensure a low kickback, so as to avoid altering qubit states. These specifications must be granted while keeping the latency of the error-correction loop much lower than the qubit coherence time. Moreover, while ensuring the above-mentioned functionalities and specifications, the controller must dissipate very low power. Although more than 1-W cooling power is available at 4 K, a processor with only 1000 qubits would limit the power budget to 1 mW/qubit, which is already very challenging, as shown in [6]. Thus, while targeting for a power budget of 1 mW/qubit is ambitious, but probably achievable in the short and medium term, it becomes clear that the development of advanced cryo-CMOS systems must go hand in hand with the development of more advanced and powerful refrigeration systems. In addition to the above-mentioned challenges, proper design tools and design flows are required to support the development of a complex system as the one in Figure 3. Cryo-CMOS can already exploit the design automation infrastructure already in place for standard CMOS. However, specific issues related both to the operation at cryogenic temperature and the interfacing with a quantum system must be addressed, as elaborated in the following sections. 3 CO-SIMULATING THE ELECTRONIC CONTROLLER AND THE QUANTUM PROCESSOR The tight power budget coupled with very demanding specifications calls for a careful system optimization. While electronic controllers operating at room temperature can be overdesigned to make the performance of the full quantum computer limited by the qubits by a wide margin, this cannot be allowed in a cryogenic implementation. It is then necessary to understand clearly the effect of any non-ideality of the electronic controller on the system performance. For example, in the case of spin qubits and transmons [10][17], single-qubit operations, i.e. rotations of the qubit state | in the Bloch sphere in Figure 1, can be executed by exciting the qubit with a microwave pulse with a specific carrier frequency and phase and specific pulse shape, amplitude and duration, which all together determine the axis of rotation and the angle of rotation in the coordinate system in Figure 1. The possible error sources for this example are listed in Table 1. Any error or any additional noise on the pulse parameters would cause an error in the operation that can be quantified by the fidelity of the quantum operation [27]. The fidelity, which should be as close as possible to 100%, is a measure of the reliability of the quantum operation, similar to the Bit Error Rate (BER) for classical communication systems. Knowing how much each single source of error contributes to the final fidelity enables a better optimization of the design, since, for example, providing accuracy/noise in the pulse amplitude may be more expensive in terms of power consumption than ensuring accuracy/noise in the pulse duration. Error budgeting for a minimum power consumption would then become possible. Table 1. Error sources for a microwave pulse for single- qubit operation (assuming a square pulse). Microwave frequency Accuracy Noise Microwave amplitude Accuracy Noise Microwave duration Accuracy Noise Microwave phase Accuracy Noise Figure 3. Generic electronic p latform for the control and read-out of quantum processors. 20-100mK 1-4K 300K ADC ADC DAC DAC MUX DEMUX Quantum Processor T Sensors Bias / References TDC Digital control (ASIC/ FPGA) OPTICAL GUIDE APD 4 For this purpose, we have developed a MATLAB simulation tool that receives as input a description of the required electrical signals and simulates the quantum system with those excitations by numerically solving the Schrödinger equation (Figure 4). As a result, the fidelity of the operation is computed. Since the simulation is computationally intensive, we are currently only able to simulate two spin qubits. However, since this allows the simulation of single- and two-qubit operations and qubit read-out (which are sufficient building blocks for most quantum computer implementations), it is sufficient, together with a theoretical model, to derive an accurate error budget for the general electronic platform of Figure 3. Moreover, the MATLAB model of the quantum processor can be used for verification of the developed cryo-CMOS circuit during the design phase (or during experimental validation before connection to the quantum processor): the simulated (or measured) output waveforms could be fed to the qubit simulator while the electrical signals generated for the read-out can be passed to the circuit simulator. This represents the first step towards a fully integrated environment for the design and verification of the controller/quantum-processor system, although several challenges are already in sight. First, it is well known that quantum systems cannot be efficiently simulated with traditional computers, and it is unclear how the simulations can be extended to a larger number of qubits that can better represent a real scenario. Furthermore, it would be convenient to embed the qubit simulation in commercial EDA design/verification flows and tools. Finally, it will be necessary to fully or partially integrate the physical simulation of qubit into the full design/validation stack of the quantum system [29], which includes the infrastructure for the quantum microcode execution and for the quantum compiler on top of the above- discussed physical layer. 4 CRYO-CMOS DEVICE MODELING Accurate device models are required to reliably design and simulate complex cryo-CMOS circuits. At deep-cryogenic temperature, many physical parameters that determine transistor behavior, such as carrier mobility, show a strong deviation from room temperature. This results, for example, in a larger drain current and higher threshold voltage at 4 K. In addition, several non-idealities that are specific to the cryogenic operation appear, such as the a so-called ‘kink’, i.e. a sudden increase in drain current at high drain-source voltage, and hysteresis in the drain current when sweeping the drain-source voltage upwards or downwards. Although the physics of cryo-CMOS is generally understood [30] and a few nanometer technologies have been cryogenically characterized (65 nm at 78 K [31], 32 nm at 6 K [32], 14 nm at 77 K [33]), there is not yet a general consensus on a standard cryogenic model for modern technologies, since prior models were limited to mature technologies (feature size 160 nm) and moderate cryogenic temperatures (>20 K) [34]-[38]. Characterization and modelling of nanometer CMOS technologies is specifically relevant for implementing low-power circuits for the platform in Figure 3, where handling of large-bandwidth high- frequency signals is required. As a step in that direction, we have characterized a large number of active and passive components in standard 160-nm and 40-nm CMOS technologies [6][7][39]. As an illustration, Figure 5 and Figure 6 shows the output characteristics of NMOS transistors in both technologies. Despite a non-negligible shift of the transistor parameters, such as threshold voltage and current gain, Figure 4: Process for the co-simulation of the electronic controller and the quantum processor. Figure 5: I-V characteristics of a 2320 nm/160 nm NMOS fabricated in 160-nm CMOS: measurements at 300 K (dotted lines) and 4 K (solid lines); SPICE-compatible model (dashed lines). Figure 6. I-V characteristics of a 1200 nm/40 nm NMOS in 40- nm CMOS: measurements at 300 K (dotted lines) and 4 K (solid lines); SPICE-compatible model (dashed lines). Vd s [ V ] 00.511.51.8 Id[ A ] 10-3 0 0.5 1 1.5 2 2.5 Vgs=0.68V Vgs=1.05V Vgs=1.43V Vgs=1.8V Vds [ V ] 0 0.2 0.4 0.6 0.8 1 1.1 Id[ A ] 10-4 0 1 2 3 4 5 6 7 Vgs=0.54V Vgs=0.65V Vgs=0.88V Vgs=1.1V 5 those characteristics are not dissimilar to the ones of a standard NMOS transistor, thus leading us to believe that standard SPICE models may be applicable also at cryogenic temperature. However, although it seems that a SPICE-compatible model for the DC behavior of cryo-CMOS devices may be feasible, much work must still be devoted to develop a full cryo-CMOS device model with the same reliability and accuracy of the models available for commercial technologies at room temperature, thus allowing the design of the complex RF, analog, mixed-signal and digital circuits of Figure 3. The challenges to be addressed include the modelling and characterization of dynamic and RF behavior, of noise at low and high frequency, both for active devices and passives. Moreover, some preliminary investigations have suggested that transistor mismatch at 4 K is largely uncorrelated to that at 300 K and that standard design techniques to mitigate the effect of mismatch may need to be modified [40]. The large impact of mismatch on the performance and, hence, the design of analog and mixed-signal circuits asks for further investigations, and both additional experimental data and theoretical analysis will be required before the correct cryogenic mismatch model can be included in design tools. Finally, self-heating may give a non-negligible effect, since even a temperature raise of only a few degrees represents a relatively large increase in absolute temperature that can result in a large variation of the electrical properties of the devices. Because of this high sensitivity, it may be necessary to model the self-heating for each individual device. This would require strong efforts in properly updating the EDA tools, since self-heating of single devices or circuit sub-blocks can be highly dependent both on their physical placement on the die and their surroundings (including metal interconnections), not to mention the effect of thermal transients. At the moment, those issues are left largely unexplored for cryo-CMOS to the best of the author’s knowledge. 5 DESIGN AUTOMATION FOR CRYOGENIC DESIGNS Although the characteristic of CMOS transistors show a very wide alteration at cryogenic temperature, it has been shown that even complex commercial components not designed or specified outside the commercial temperature range, such as FPGAs, can reliably operate at cryogenic temperature [41]-[43]. Extensive characterization showed not only that all major components of a standard Xilinx Artix 7 FPGA, including look-up tables (LUT), phase-locked loops (PLL) and IOs, operate correctly down to 4 K but also that their logic speed is very stable over temperature [43]. An ADC based on a time-to-digital converter (TDC) has also been implemented in the same FPGA platform and its continuous operation from 300 K down to 15 K has been demonstrated, although specific care had to be taken in designing the firmware to minimize the temperature sensitivity, and calibration was extensively used to compensate for temperature effects [42]. Apart from showing the functionality of standard CMOS components at cryogenic temperature, FPGAs can also have a practical application for the implementation of the system in Figure 3, which at least in the first instance will not be necessarily limited to application-specific integrated circuits (ASIC). FPGAs could be beneficial thanks to their reconfigurability, which could prevent expensive and time-consuming cool-down-warm-up cycles. In addition, FPGA design tools leverage a mature synthesis and place-and-route technology, with advanced verification tools that could be used to emulate the operation of the circuit at cryogenic temperatures. For the design and verification of the cryogenic FPGA, standard tools for firmware design were employed. The characterization of a standard FPGA library was an important step in creating the firmware, thus enabling correct operation at deep- cryogenic temperature. Similar efforts are needed in ASIC digital libraries, where transistor models are part of this characterization and could enable fast library certification. Ultimately, logic gate farms will be required to verify simulations and to validate the proposed models. In this context, the process of digital library characterization is not unlike a conventional one, with the difference that it requires care in measuring the circuits at various temperatures with a well-controlled measurement setup and particular attention to self-heating. The library characterization will also yield non-functional library elements, depending on temperature, thus requiring that synthesis and place-and-route tools be temperature-driven and/or temperature-aware. A less trivial task would be the design of digital circuits that exploit the specific features of cryo-CMOS. The main challenge of operating large CMOS circuits and systems at cryogenic temperatures is power dissipation. In order to minimize power dissipation, the supply voltage could be reduced even down to a few tens of millivolt by exploiting the relaxed requirement on noise margins due to the low thermal-noise level at cryogenic temperature. Operation in sub-threshold regime can also be heavily exploited thanks to the improved subthreshold slope at low temperature and to the resulting large on/off-current ratio (I on /I off ) ratio. Furthermore, the expected extremely low leakage current in cryo-CMOS may lead to power-efficient use of existing dynamic logic, or even bring in the possibility of new dynamic logic families. This can pose problems in the synthesis and verification of logic circuits, prompting the EDA industry to rethink models and perhaps even simulators, so as to achieve the necessary accuracy in the simulation of these regimes. Finally, the operating temperature can be exploited as a new design parameter. Since the cooling power in a cryogenic refrigerator is larger at higher temperature, higher computational power could be placed at a higher temperature. However, particular care should then be devoted to the interconnections that, apart from becoming unpractical, could also occupy a relevant fraction of the cooling power budget due to their thermal conduction. The full digital back-end of a quantum computer would then spread over several temperature stages, eventually with a lower inter-stage data communication rate for circuits at lower temperatures. Although conceptually interesting, such approach would require an ad-hoc EDA infrastructure covering several multidisciplinary domains, including device modelling and library characterization over a very wide temperature range, 6 thermal modelling, interconnect optimization and novel synthesis tools. 6 CONCLUSIONS The design of cryo-CMOS controllers for quantum computers presents several challenges for the design automation industry. First steps have already been taken, especially for device modelling and simulation/optimization of the quantum/classical interface. However, we are still far from the EDA infrastructure that will enable the design of the classical controller satisfying both the demanding electrical specifications and its very tight power budget. With the growing academic and industrial interest in the field of quantum computation, we foresee that several of the presented challenges will be soon picked up by the research community. This would result in an accelerating virtuous cycle including the design of cryo-CMOS circuits and systems with ever increasing complexity on one hand and more performant EDA tools on the other hand, thus facilitating the fabrication of practical quantum computers. ACKNOWLEDGMENTS The authors are grateful to Intel Corp. for funding the project. REFERENCES [1] A. Montanaro Quantum Algorithms: An Overview. npj Quantum Information 2, (Jan. 2016), 15023. [2] R. P. Feynman. Simulating physics with computers, International journal of theoretical physics 21, 6 (1982), 467–488. [3] K. M. Svore and M. Troyer. The Quantum Future of Computation, Computer 49, 9 (2016), 21-30. [4] J. M. Hornibrook et a l. Cryogenic Control Architecture for Large-Scale Quantum Compu ting. Phys. Rev. Appl. 3 (2015), 024010. [5] H.Homulle, S.Visser, B.Patra, G.Ferrari, E.Prati, C.G. Almudever, K. Bertels, F. Sebastiano, and E. Charbon. CryoCMOS Hardware Technology - A Classical Infrastructure for a Scalable Quantum Computer,” 2016 ACM International Conference on computing frontiers (2016). [6] E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, R.B. Staszewski, H.A.R. Homulle, B. Patra, J.P.G. van Dijk, R.M. Incandela, L. Song, and B. Valizadehpasha. Cryo-CMOS Circuits and Systems for Scalable Quantum Computing. Proc. 2017 International Solid-State Circuits Conference (2017). [7] E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, R.M. Incandela. Cryo-CMOS for quantum computing. Proc . 2016 IEEE International Electron Devices Meeting (IEDM) (2016). [8] L. Vandersypen. Quantum Computing-The Next Challenge in Circuit and System Design. Proc. 2017 International Solid-State Circuit Conference, (2017), 24-29. [9] F. R. Braakman, P. Barthelemy, C. Reichl, W. Wegscheider, and L. M. K. Vandersypen. Long-distance coherent coupling in a quantum dot array. Nat. Nanotechnol. 8 (2013), 432-437. [10] E. Kawakami, P. Scarlino, D. R. Ward, F. R. Braakman, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, and L. M. K. Vandersypen. Electrical control of a long-lived spin q ubit in a Si/SiGe quantum dot. Nat. Nanotechnol. 9 (2014), 666. [11] D. Kim et al. Quantum control and process tomography of a semiconductor quantum dot hybrid qubit. Nature 511 (2014), 70-4. [12] J. I. Colless, A. C. Mahoney, J. M. Hornibrook, A. C. Doherty, H. Lu, A. C. Gossard, and D. J. Reilly. Dispersive readout of a few-electron double quantum dot with fast RF gate sensors. Phys. Rev. Lett. 110 (2013), 046805. [13] R. Kalra, A. Laucht, C. D. Hill, and A. More llo. Robust two-qubit gates for donors in silicon controlled by hyperfine interactions. Phys. Rev. X. 4 (2014), 021044. [14] J. T. Muhonen e t al. Sto ring qua ntum informat ion for 3 0 seco nds in a nanoelectronic device. Nat. Nanotechnol. 9 (2014), 986. [15] J. T. Muhonen et al. Quantifying the quantum gate fidelity of single-atom spin qubits in silicon by randomized benchmarking. J. Phys. Condens. Matter 27 (2015), 154205. [16] L. DiCarlo et al. Demonstration of two-qubit algorithms with a superconducting quantum processor. Nature 460 (2009), 240. [17] D. Risté, S. Poletto, M.-Z. Huang, A. Bruno, V. Vesterinen, O.-P. Saira, and L. DiCarlo. Detecting bit-flip errors in a logical qubit using stabilize r measurements. Nat. Commun. 6 (2015), 6983. [18] R. Barends et al. Superconducting quantum circuits at the surface code threshold for fault tolerance. Nature 508 (2014), 500. [19] E. Jeffrey et al. Fast accurate state measurement with superconducting qubits. Phys. Rev. Lett. 112 (2014), 190504. [20] J. M. Chow, J. M. Gambetta, E. Magesan, D. W. Abraham, A. W. Cross, B. R. Johnson, N. A. Masluk, C. A. Ryan, J. A. Smolin, S. J. Srinivasan, and M. Steffen. Implementing a strand of a scalable fault-tolerant quantum computing fabric . Nat. Commun. 5 (2014), 4015. [21] A. Fowler, M. Mariantoni, J. Martinis, and A. Cleland. Surface codes: Towards practical large-scale quantum computation. Phys. Rev. A 86 (2012), 032324. [22] D. Wecker, B. Bauer, B. K. Clark, Bryan K. and M. B. Hastings, and M. Troyer. Gate-count estimates for performing quantum chemistry on small quantum compu ters. Phys. Rev. A, 90, 2 (2014), 022305. [23] D.J. Reilly. Engineering the quantum-classical interface of solid-state qubits. npj Quantum Information 1 (Oct. 2015), 15011. [24] J.D. Cressler and H.A. Mantooth, Eds. Extreme environment electronics. Boca Raton, Florida: CRC Press., 2013. [25] R. Kirschman. Survey of Low-Temperature Electronics. Workshop on Low- Temp. Electronics – WOLTE11 (2014). [26] S.R. Ekanayake, T.Lehmann, A.S. Dzurak, R.G. Clark and A. Brawley. Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout. IEEE Tran. Electron Devices 57, 2 (Feb. 2010), 539-547. [27] M. A. Nielsen and I. L. Chuang. Quantum Computation and Quantum Information. Cambridge university press, 2010. [28] Blue Fors Cr yogenic s. XLD Series. Retrie ved Marc h 17th, 2017 from http://www.bluefors.com/newsite/index.php/xld-seriest [29] X.Fu, L.Riesebos, L.Lao, C.G.Almudever, F.Sebastiano, R.Versluis, E.Charbon, and K.Bertels. A Heterogeneous Quantum Computer Architecture. 2016 ACM International Conference on computing frontiers (May 2016). [30] E. Simoen and C. Claeys. Impact of CMOS processing steps on the drain current kink of NMOSFETs at liquid helium temperature. IEEE Trans. Electron Devices, 48, 6 (Jun. 2001), 1207–1215. [31] A. Siligaris et al. High-Frequency and Noise Performances of 65-nm MOSFET at Liquid Nitrogen Temperature. IEEE Transactions on Electron Devices 53, 8 (Aug. 2006), 1902-1908. [32] A. H. Coskun and J. C. Bardin. Cryogenic small-signal and noise performance of 32nm SOI CMOS. 2014 IEEE MTT-S International Microwave Symposium, 2014. [33] M. Shin, M. Shi, M. Mouis, A. Cros, E. Josse, G. T. Kim and G. Ghibaudo. Low temperature characterization of 14nm FDSOI CMOS devices. 2014 11th International Workshop on Low Temperature Electronics (WOLTE), (2014). [34] H. Zhao, and X. Liu. Modeling of a standard 0.35 μm CMOS technology operating from 77K to 300K. Cryogenics 59 (2014), pp. 49-59. [35] P. Martin, A. S. Royet, F. Guellec, and G. Ghibaudo. MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process. Solid-State Electronics 62 (Feb. 2011), 115-122. [36] A. Akturk, M. Holloway, S. Potbhare, D. Gundlach, B. Li, N. Goldsman, M. Peckerar, and K. P. Cheung. Compact and Distributed Modeling of Cryogenic Bulk MOSFET Op eration. IEEE Trans. Electron Devices 57, 6 (June 2010), 1334-1342. [37] G.S. Fonseca, L.B. de Sá, and A.C. Mesquita. Extraction of static parameters to extend the EKV model to cryogenic temperatures. Proc. SPIE (May 2016), 98192B-98192B. [38] Z. Zhu, A. Kathuria, S.G. Krishna, M. Mojarradi, B. Jalali-Farahani, H. Barnaby, W. Wu, and G. Gildenblat. Design applications of compact MOSFET model for extended temperature range (60-400K). Electronics Letters 47, 2 (Jan. 2011), 141-142. [39] L. Song, H. Homulle, E. Charbon, and F. Sebastiano. Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS. Proc. 2016 IEEE Sensors (2016). [40] K. Das, T. Lehmann. Effect of deep cryogenic temperature on silicon-on- insulator CMOS mismatch: A circuit designer’s perspective. Cryogenics 62 (2014), 84–93. [41] I.D.Conway Lamb, J.I. Colless, J.M. Hornibrook, S.J. Pauka, S.J.Waddy, M.K.Frechtling, and D.J. Reilly. A FPGA-based instru mentation platform for use at deep cryogenic temperatures. Rev. Sci. Instrum. 87 (2016), 014701. [42] H. Homulle, S. Visser and E. Charbon. A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. IEEE Tran. Circuits and Systems I: Regular Papers 63, 11 (Nov.2016), 1854-1865. [43] H. Homulle, S. Visser, B. Patra, G. Ferrari, E. Prati, F. Sebastiano, and E. Charbon. A Reconfigurable Cryogenic Platform for the Classical Control of Scalable Quantum Computers. arXiv:1602.05786 ... Furthermore, hardware decoders would be preferred to support the scalability of quantum computers. Promising candidates for large-scale quantum computers comprise large arrays of cryogenic solid-state qubits controlled by local electronics also operating at cryogenic temperatures to ensure compactness and reliability by avoiding long interconnects between several temperature stages [20][21][22][23][24][25][26][27][28]. Thus, the QEC decoder must also run at cryogenic temperature and an integrated hardware implementation is favorable to minimize the area occupation (for compactness) and the power dissipation (to comply with the limited cooling budget of cryogenic refrigerators). ... ... FIG.21. The optimal distance to obtain the lowest logical error rate for a certain physical error rate. ... Preprint Full-text available Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements$(\approx 440\ \mathrm{ns})$of current solid-state qubit technologies for both ASIC designs$(<30\ \mathrm{ns})$and FPGA implementations$(<90\ \mathrm{ns})$. These results designates NN-decoders as fitting candidates for an integrated hardware implementation in future large-scale quantum computers. ... This operating temperature is dictated by both the implementation requirements of qubits (for ion traps, superconducting, spin etc.,) as well as reliability in terms of fidelity. A feasible solution for building a scalable quantum computer with reasonable number of interconnects is to place the control electronics and memory circuits closer to the qubits at around 4K rather than at room temperature [8] which will require digital, analog and RF circuits to operate at low temperatures. CMOS is one of the more reliable Rakshith technologies that can provide an integrable solution with a higher number of qubits and operate at cryogenic temperature. ... Article Full-text available Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in cryogenic operation of digital logic. In this paper, we analyze digital standard cells in 28nm High-K Metal Gate (HKMG) CMOS foundry Process Design Kit (PDK). We have developed BSIM4 models of cryogenic CMOS and calibrated with experimental measurements. Since, low temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this paper, we present inverter static and dynamic characteristics and multiple Ring Oscillator(RO) structures. The simulation study shows that we can achieve 28%(FO4-RO) – 59%(NAND3-RO) higher performance under iso-VDD scenario and up to 90% improvement in the Energy Delay Product (EDP) under iso-overdrive scenario at 6K compared to room temperature. Thesis Compact models describing the operation of MOS devices at cryogenic temperatures are crucial for the designing of reliable and optimized circuits. Nowadays, process-design kits lack models for all devices at deep cryogenic temperatures, whether it is a MOSFET, a qubit, or a passive device. The task of building compact models for cryogenic operation needs to be tackled urgently, mainly because today’s circuit simulations fail to function as expected down to cryogenic temperatures. Consequently, excessive simulations are needed to be done to account for the changes in different parameters.There are two approaches to deal with this task, the first one is to take existing standard compact models, which are originally built for room temperature operation and try to adapt them to cryogenic temperature operation through empirical formulas. It should be noted that for this approach the circuit performance is not guaranteed, and they are designed with a non-negligible degree of uncertainty. The second approach, which is a research approach and the one we choose in the frame of this thesis, is to build fully-physics based compact models that are dedicated for cryogenic device operation. Compared to the first approach, this approach should be less risky and the output design-wise is much more appropriate and precise.Current standard compact models can scale down to liquid Nitrogen temperature 77K, but at liquid Helium temperature 4.2K and below some discontinuities start appearing in the moderate inversion region. Moreover, neither of the FDSOI cryogenic operation published works demonstrate in an extensive manner the transistor electrostatics characteristics that is to say the electrostatic surface potentials for both interfaces, and the C – V curves. Likewise, the Fermi-Dirac statistics need to be considered in the transport part in the drain current derivation and not only in the electrostatics part. Furthermore, most of the published works maintain the RT mobility laws and adapt them to cryogenic behavior by modifying/adding fitting parameters or considering a constant mobility in the linear regime, but none considers introducing a proper mobility law dedicated for MOSFETs operating at cryogenic temperatures.Besides, Numerical simulations are an important step that must precede the development of an analytical model and that will serve as a solid ground for the validation of its results/approximations. No numerical simulation has been held in such conditions, whether the simulation of the electrostatics at equilibrium, or electronic transport out of equilibrium. The use of such simulations is very important and necessary for the development of compact models. In the frame of this work, Poisson-Schrodinger simulations of the FDSOI structure at cryogenic temperatures and accounting for Fermi-Dirac statistics were held to exploit and understand the device’s electrostatics primarily, and then the simulations were held with the introduction of a quasi-Fermi level term to analyze the transport aspect of the device.The scope of this thesis therefore, is to exploit the device’s physics of FDSOI transistors down to deep cryogenic temperatures and to develop an appropriate core compact model. Such work would be the foundation into a compact model that is suitable for spice simulations. Article Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least$\pm$20% of process parameter variations as demonstrated with extensive simulations. Article Full-text available Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements$(\approx 440\ \text{ns})$of current solid-state qubit technologies for both application-specific integrated circuit designs$(< \!30\ \text{ns})$and field-programmable gate array implementations$(<\! 90\ \text{ns})\$ . These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
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