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Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

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... Furthermore, Chase decoding can be implemented efficiently in a parallel manner, and the decoder has no iterations. In order to further reduce the decoding latency while still retaining a similar performance gain, a simple but effective two-stage hybrid decoding algorithm [70] is adopted here for decoding RS codes. ...
... The signal dependent offset model is appropriate in many scenarios. For example, the binary input user data is stored as the two resistance states of a spin-torque transfer magnetic random access memory (STT-MRAM) cell [70]. A signal dependent offset model is reasonable when process variation causes an asymmetric distribution of both the low and high resistance states. ...
... • It would be challenging to investigate the information-theoretic channel capacity of noisy channels with gain and/or offset mismatch. Small-scale research has emerged evaluating the capacity of channels with physical effects like voltage leakage, such as a multi-level flash memory with input-dependent additive Gaussian noise [10], a binary asymmetric channel cascaded with a Gaussian mixture channel [70]. ...
... STT-MRAM devices are used in the embedded memory applications [10] for automotive industry [4] and the Internet [1,8], which do not require the use of powerful computing systems. There are also studies on the use of these technologies in nonvolatile operating computer memory, along with flash-memory technologies [7]. ...
... This is due to thermal fluctuations of the energy values of thermal fluctuations comparable with the values of the magnetization reversal energy. In [4], it is foretold that three types of errors may occur in STT-MRAM: 1) errors caused by higher values of current than technological standards; 2) errors caused by lower values of the recording current than technological standards; 3) errors caused by random magnetization. ...
... The final form of the equation based on the macro-spin model that uses the amplitude value of the spin current, derived from the quantum-mechanical model of the electron flow, can be written as follows: (4) where I s is the spin current. ...
Article
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The article analyzes the physical processes that occur in spin-valve structures during recording process which occurs in high-speed magnetic memory devices. Considered are devices using magnetization of the ferromagnetic layer through transmitting magnetic moment by polarized spin (STT-MRAM). Basic equations are derived to model the information recording process in the model of symmetric binary channel. Because the error probability arises from the magnetization process, a model of the magnetization process is formed, which is derived from the Landau-Lifshitz-Gilbert equations under the assumption of a single-domain magnet. The choice of a single-domain model is due to the nanometer size of the flat magnetic layer. The developed method of modeling the recording process determines the dependence of such characteristics as the bit error probability and the rate of recording on two important technological characteristics of the recording process: the value of the current and its duration. The end result and the aim of the simulation is to determine the optimal values of the current and its duration at which the speed of the recording process is the highest for a given level of error probability. The numerical values of the transmission rate and error probability were obtained for a wide range of current values (10–1500 μA) and recording time of one bit (1–70 ns), and generally correctly describe the process of information transmission. The calculated data were compared with the technical characteristics of existing industrial devices and devices which are the object of the scientific research. The resulting model can be used to simulate devices using different values of recording currents: STT-MRAM series chips using low current values (500-100 μA), devices in the stage of technological design and using medium current values (100–500 μA) and devices that are the object of experimental scientific research and use high currents (500–1000 μA). The model can also be applied to simulate devices with different data rates, which have different requirements for both transmission speed and bit error probability. In this way, the model can be applied to both high-speed memory devices in computer systems and signal sensors, which are connected to sensor networks or connected to the IoT.
... Driven by the characteristics of these errors, the work in [5] proposed a cascaded channel model for STT-MRAM, where the write error and the read disturb error are modeled by a combined binary asymmetric channel (BAC). Considering reading along the write-0 direction, the crossover probabilities of the BAC are given by ...
... Following the parameters adopted in [2], in this work, we consider a 45nm×90nm in plane MTJ under a PTM 45nm technology node, with µ 0 = 1 kΩ, µ 1 = 2 kΩ, and σ 0 /µ 0 = σ 1 /µ 1 . In all our simulations, we take a write error rate of P 1 = 2×10 −4 , and vary σ 0 /µ 0 to account for the influence of different quality of the fabrication process on the read decision error [5]. We propose a quantized STT-MRAM channel as shown by Fig. 1, which is derived based on the cascaded channel model [5]. ...
... In all our simulations, we take a write error rate of P 1 = 2×10 −4 , and vary σ 0 /µ 0 to account for the influence of different quality of the fabrication process on the read decision error [5]. We propose a quantized STT-MRAM channel as shown by Fig. 1, which is derived based on the cascaded channel model [5]. This quantized channel consists of a BAC and a binary-input DMC (BI-DMC). ...
Preprint
Channel output quantization plays a vital role in high-speed emerging memories such as the spin-torque transfer magnetic random access memory (STT-MRAM), where high-precision analog-to-digital converters (ADCs) are not applicable. In this paper, we investigate the design of the 1-bit quantizer which is highly suitable for practical applications. We first propose a quantized channel model for STT-MRAM. We then analyze various information theoretic bounds for the quantized channel, including the channel capacity, cutoff rate, and the Polyanskiy-Poor-Verd\'{u} (PPV) finite-length performance bound. By using these channel measurements as criteria, we design and optimize the 1-bit quantizer numerically for the STT-MRAM channel. Simulation results show that the proposed quantizers significantly outperform the conventional minimum mean-squared error (MMSE) based Lloyd-Max quantizer, and can approach the performance of the 1-bit quantizer optimized by error rate simulations.
... The LDPC codes have the same problem, namely, the long decoding latency [5]. A hybrid decoding algorithm, combining the extended Hamming code with Chase decoding, is proposed to balance the error correcting capability and decoding latency [6]. In this paper, we make a simple modification to the original hybrid algorithm for efficient hardware implementation. ...
... A cascade channel is proposed to model the STT-MRAM cell [6]. The cascade channel is built by concatenating a combined binary asymmetric channel (BAC) and a Gaussian mixture channel (GMC), as shown in Fig. 1. ...
... A two-stage hybrid decoding algorithm is proposed to enhance the error correction capability of the HDD for STT-MRAM [6]. It first runs the hard-decision decoding. ...
... Key advantages of STT-MRAM include high endurances, fast read/write speed, and low switching energy [2]. However, due to process variation and thermal fluctuation, both the write errors and read errors occur, leading to a detrimental effect on the reliability of data stored in the memory cells [3]. Moreover, due to the memory process imperfection, there also exists a diversity of the raw bit error rate (BER) among different dies of STT-MRAM. ...
... Based on the major characteristics and cell failure mechanism of STT-MRAM, a cascaded channel model for STT-MRAM is proposed by [3] and used in our work. The cascaded channel model adopts a binary asymmetric channel (BAC) to describe the combined write error and the read disturb error of STT-MRAM. ...
... At the receiver side, a sign adjuster is adopted that performs the operation of v i = u i * (1 − 2 * t i ), with u i being the log-likelihood ratio (LLR) of the channel output signal y i , v i being the input of the LDPC decoder. Here, u i is provided by an LLR generator, such as a soft-output channel detector [3]. As can be seen, the sign adjuster undoes the effect of the mod-2 adder. ...
Article
Thanks to its superior features of non-volatility, fast read/write speed, high endurance, and low power consumption, spin-torque transfer magnetic random access memory (STT-MRAM) has become a promising candidate for the next generation non-volatile memories (NVMs) and storage class memories (SCMs). However, it has been found that the write errors and read errors caused by thermal fluctuation and process variation severely degrade the reliability of STT-MRAM. Moreover, process imperfection also causes a diversity of the raw bit error rate (BER) among different dies of STT-MRAM. In this paper, we propose the design of novel rate-compatible protograph low-density parity-check (RCP-LDPC) codes to correct memory cell errors and mitigate the raw BER diversity of STT-MRAM. In particular, to deal with the asymmetric property of the STT-MRAM channel, we first apply an independent and identically distributed (i.i.d.) channel adapter to symmetrize the STT-MRAM channel. We then present a modified protograph extrinsic information transfer (P-EXIT) algorithm for the symmetrized STT-MRAM channel. We further propose a combined guideline, including the modified P-EXIT algorithm, the asymptotic weight enumerator (AWE) analysis, as well as the actual error rate performance, for designing protograph LDPC codes with short information word lengths for STT-MRAM. By further applying a code extension approach, we design novel RCP-LDPC codes that can work with a single encoder/decoder. Simulation results show that our proposed RCP-LDPC codes outperform the well-known rate-compatible AR4JA protograph codes as well as the fixed-rate quasi-cyclic (QC) LDPC codes in terms of both the error rate performance and the convergence speed over the STT-MRAM channel.
... We simply find r = 0.733. The next table shows δ w versus w using (14). ...
... A (71, 64) regular Hamming code is used for Everspins 16 MB MRAM, where straightforward hard decision detection is used [13]. Cai and Immink [14] propose a (72, 64) extended Hamming code with a two-stage hybrid decoding algorithm that incorporates hard decision detection for the first-stage plus a Chase II decoder [11] for the second stage of the decoding routine. ...
... Exhaustive optimal detection of long Hamming codes, such as the extended (72, 64) is an impracticality as it requires the distance comparison of 2 64 valid codewords. Sub-optimal detection can be accomplished with, for example, the wellknown Chase algorithm [11], [14]. The Chase algorithm selects T of the least reliable bits by selecting the symbols, r i , having least absolute channel value with respect to the decision level. ...
Article
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We consider the transmission and storage of encoded strings of symbols over a noisy channel, where dynamic threshold detection is proposed for achieving resilience against unknown scaling and offset of the received signal. We derive simple rules for dynamically estimating the unknown scale (gain) and offset. The estimates of the actual gain and offset so obtained are used to adjust the threshold levels or to re-scale the received signal within its regular range. Then, the re-scaled signal, brought into its standard range, can be forwarded to the final detection/decoding system, where optimum use can be made of the distance properties of the code by applying, for example, the Chase algorithm. A worked example of a spin-torque transfer magnetic random access memory (STT-MRAM) with an application to an extended (72, 64) Hamming code is described, where the retrieved signal is perturbed by additive Gaussian noise and unknown gain or offset.
... An STT-MRAM cell has two resistance states, a low resistance state R 0 which represents an input information bit of "0", and a high resistance state R 1 which denotes an information bit of "1". The reliability of the data stored in the memory cell is largely affected by the process variation caused by the fabrication imperfection, which leads to widened distributions of the low and high resistances of the memory cell and their overlapping, and hence the channel detection errors [16], [17]. Moreover, the resistance distributions of the STT-MRAM cell are also affected by the working temperature. ...
Preprint
The memory physics induced unknown offset of the channel is a critical and difficult issue to be tackled for many non-volatile memories (NVMs). In this paper, we first propose novel neural network (NN) detectors by using the multilayer perceptron (MLP) network and the recurrent neural network (RNN), which can effectively tackle the unknown offset of the channel. However, compared with the conventional threshold detector, the NN detectors will incur a significant delay of the read latency and more power consumption. Therefore, we further propose a novel dynamic threshold detector (DTD), whose detection threshold can be derived based on the outputs of the proposed NN detectors. In this way, the NN-based detection only needs to be invoked when the error correction code (ECC) decoder fails, or periodically when the system is in the idle state. Thereafter, the threshold detector will still be adopted by using the adjusted detection threshold derived base on the outputs of the NN detector, until a further adjustment of the detection threshold is needed. Simulation results demonstrate that the proposed DTD based on the RNN detection can achieve the error performance of the optimum detector, without the prior knowledge of the channel.
... An STT-MRAM cell has two resistance states, a low resistance state R 0 which represents an input information bit of "0", and a high resistance state R 1 which denotes an information bit of "1". The reliability of the data stored in the memory cell is largely affected by the process variation caused by the fabrication imperfection, which leads to widened distributions of the low and high resistances of the memory cell and their overlapping, and hence the channel detection errors [16], [17]. Moreover, the resistance distributions of the STT-MRAM cell are also affected by the working temperature. ...
... With the proposed technique, both reliability and access performance of STT-MRAM can be improved dramatically. A novel cascaded channel model for fast error rate simulation was proposed in [117]. Based on this model, the authors proposed a two-stage hybrid decoding scheme extended from the Hamming code to improve STT-MRAM access reliability. ...
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Memories occupy most of the silicon area in nowa-days' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript so far for various MRAM technologies. The last part of this article gives some perspectives on this hot topic.
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As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. In this paper, we reveal an important fact that has been neglected in STT-RAM designs for long: the write operation of a STT-RAM cell is asymmetric based on the switching direction of the MTJ (magnetic tunneling junction) device: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite switching. Some special design concerns, e.g., the write-pattern-dependent write reliability, are raised by this observation. We systematically analyze the root reasons to form the asymmetric switching of the MTJ and study their impacts on STT-RAM write operations. These factors include the thermal-induced statistical MTJ magnetization process, asymmetric biasing conditions of NMOS transistors, and both NMOS and MTJ device variations. We also explore the design space of different design methodologies on capturing the switching asymmetry of different STT-RAM cell structures. Our experiment results proved the importance of full statistical design method in STT-RAM designs for design pessimism minimization.
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Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Green's Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16 nm predictive technology.
Article
There are numerous emerging nonvolatile memory technologies, which have been proposed as being capable of replacing hard disk drives (HDDs). In this paper, the prospects for these alternative technologies to displace HDDs in 2020 are analyzed. In order to compare technologies, projections were made of storage density and performance in year 2020 for both hard disks and the alternative technologies, assuming the alternative technologies could solve their remaining problems and assuming that hard drives would continue to advance areal density at a pace of about 40% per year, which would result in a two-disk 2.5-in disk drive that stores approximately 40 Terabytes and costs about $40. A major conclusion of the study is that to compete with hard drives on a cost per terabyte basis will be challenging for any solid state technology, because the ITRS lithography roadmap limits the density that most alternative technologies can achieve. Those technologies with the best opportunity have a small cell size and the capability of storing multiple bits per cell. Phase change random access memory (PCRAM) and spin transfer torque random access memory (STTRAM) appear to meet these criteria. PCRAMs are being marketed by at least one supplier and therefore appear to be closer to practical realization. On the other hand, STTRAMs would appear to have a performance edge assuming they, too, can be brought to market with multiple bits per cell. Although there are technologies that are not limited by the lithography roadmap and thus have greater areal density potential, they tend to be further from practical realization.
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The logic complexity and computational complexity of decoders for BCH codes are investigated, and bounds on complexity are obtained. These are compared with earlier. results of Savage for arbitrary block codes and for some special decoding rules. It is found that decoders for the class of BCH codes are of much lower complexity.
Article
This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
Conference Paper
The rapidly increased demands for memory in electronic industry and the significant technical scaling challenges of all conventional memory technologies motivated the researches on the next generation memory technology. As one promising candidate, spintransfer torque random access memory (STT-RAM) features fast access time, high density, non-volatility, and good CMOS process compatibility. However, like all other nano-scale devices, the performance and reliability of STT-RAM cells are severely affected by process variations, intrinsic device operating uncertainties and environmental fluctuations. In this work, we systematically analyze the impacts of CMOS and MTJ process variations, MTJ switching uncertainties induced by thermal fluctuations and working temperature on the performance and reliability of STT-RAM cells. A combined circuit and magnetic simulation platform is also established to quantitatively analyze the persistent and non-persistent error rates during the STT-RAM cell operations. Finally, an optimization flow and its effectiveness are depicted by using some STT-RAM cell designs as case study.
Conference Paper
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In conventional design practice, the nMOS transistor within each memory cell is sized to be large enough to carry a current larger than the worst-case MTJ write current threshold, leading to an increasing storage density penalty as the technology scales down. To mitigate such variability-induced storage density penalty, this paper presents a smaller-than-worst-case transistor sizing approach with the underlying theme of jointly considering memory cell transistor sizing and defect tolerance. Its effectiveness is demonstrated using 256Mb STT MRAM design at 45nm node as a test vehicle. Results show that, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design practice.
Article
Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient design paradigm from circuit and/or architecture perspective-to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting design requirements for read stability, writability and cell area. It can be used at an early stage of the design cycle for yield enhancement.
Article
This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
Conference Paper
A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time. The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM. This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm. The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure. The 4kbit spin-RAM was fabricated on a 4 level metal, 0.18 mum CMOS process. In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated. It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory
Conference Paper
A 256-Mb DRAM (dynamic random-access memory) fabricated using 0.25-μm CMOS technology is described. The DRAM has 16-b I/Os, 30-ns access time, and 35-mA operating current for 60-ns cycle time. Key circuits include a partial cell array activation scheme in a multidivided array structure with a dual word-line format for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O (input/output) width and to reduce current, and a time-sharing refresh to maintain a conventional refresh period without increasing power-line voltage bounce
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In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an order of magnitude. We concentrate on extended Bose-Chaudhuri-Hocquengem codes as the constituent row and column codes because of their already low implementation complexity. For these component codes, we observe that the weight and reliability factors can be fixed, and that there is no need for normalization. Furthermore, as opposed to previous efficient decoders, the newly proposed decoder naturally scales with a test-pattern parameter p that can change as a function of iteration number, i.e., the efficient Chase algorithm presented here uses conventionally ordered test patterns, and the syndromes, even parities, and extrinsic metrics are obtained with a minimum number of operations.
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In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.
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The general problem of estimating the a posteriori probabilities of the states and transitions of a Markov source observed through a discrete memoryless channel is considered. The decoding of linear block and convolutional codes to minimize symbol error probability is shown to be a special case of this problem. An optimal decoding algorithm is derived.
Article
A class of decoding algorithms that utilizes channel measurement information, in addition to the conventional use of the algebraic properties of the code, is presented. The maximum number of errors that can, with high probability, be corrected is equal to one less than d , the minimum Hamming distance of the code. This two-fold increase over the error-correcting capability of a conventional binary decoder is achieved by using channel measurement (soft-decision) information to provide a measure of the relative reliability of each of the received binary digits. An upper bound on these decoding algorithms is derived, which is proportional to the probability of an error for d th order diversity, an expression that has been evaluated for a wide range of communication channels and modulation techniques. With the aid of a lower bound on these algorithms, which is also a lower bound on a correlation (maximum-likelihood) decoder, we show for both the Gaussian and Rayleigh fading channels, that as the signal-to-noise ratio (SNR) increases, the asymptotic behavior of these decoding algorithms cannot be improved. Computer simulations indicate that even for !ow SNR the performance of a correlation decoder can be approached by relatively simple decoding procedures. In addition, we study the effect on the performance of these decoding algorithms when a threshold is used to simplify the decoding process.
Article
We study two families of error-correcting codes defined in terms of very sparse matrices. “MN” (MacKay-Neal (1995)) codes are recently invented, and “Gallager codes” were first investigated in 1962, but appear to have been largely forgotten, in spite of their excellent properties. The decoding of both codes can be tackled with a practical sum-product algorithm. We prove that these codes are “very good”, in that sequences of codes exist which, when optimally decoded, achieve information rates up to the Shannon limit. This result holds not only for the binary-symmetric channel but also for any channel with symmetric stationary ergodic noise. We give experimental results for binary-symmetric channels and Gaussian channels demonstrating that practical performance substantially better than that of standard convolutional and concatenated codes can be achieved; indeed, the performance of Gallager codes is almost as close to the Shannon limit as that of turbo codes
Area, power, and latency considerations of STT-MRAM to substitute for main memory
  • Y Jin
  • M Shihab
  • M Jung
Y. Jin, M. Shihab, and M. Jung, "Area, power, and latency considerations of STT-MRAM to substitute for main memory," in Memory Forum Tech. Dig., Minneapolis, MN, USA, Jun. 2014, pp. 1-4.
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
  • X Bi
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  • W Wu
X. Bi, Z. Sun, H. Li, and W. Wu, "Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches," in IEEE/ACM Int. Conf. Comput.-Aided Design Tech. Dig., Nov. 2012, pp. 88-94.
Channel capacity and softdecision decoding of LDPC codes for spin-torque transfer magnetic random access memory (STT-MRAM)
  • K Cai
  • Z Qin
  • B Chen
K. Cai, Z. Qin, and B. Chen, "Channel capacity and softdecision decoding of LDPC codes for spin-torque transfer magnetic random access memory (STT-MRAM)," J. Commun., vol. 8, no. 4, pp. 225-232, Apr. 2013.
A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM
  • M Hosomi
Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell
  • J.-H Kim