Single event effects in high density CMOs SRAMs
NTT Electrical Communications Laboratories 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-01 JapanIEEE Transactions on Nuclear Science (Impact Factor: 1.28). 01/1987; 33(6):1632 - 1636. DOI: 10.1109/TNS.1986.4334654
Source: IEEE Xplore
The effects of epi-substrate and a cell power supply layout on heavy-ion induced latch-up for 64K SRAMs are examined by heavy-ion exposure tests using a cyclotron. It is shown that epi-substrate alone is not sufficient to prevent latch-up. A cell power supply layout technique, that is, power is supplied through the well for MOSFETs in the well, combined with epi-substrate is very effective in preventing latch-up for high density CMOS/BULK memories. Soft error cross sections and threshold LETs for various CMOS SRAMs are determined by heavy-ion exposure tests. The threshold LET for conventional 64K SRAMs decreases to about one-fifth that of 1K SRAMs.
Conference Paper: Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K[Show abstract] [Hide abstract]
ABSTRACT: The processing and design geometric scaling effects on the soft-error tolerance levels of the 16K 2-µm technology and the 256K 1-µm technology CMOS SRAMs are separated by fabricating the 16K 2-µm design with the 1-µm process. Although the 1-µm twin-tub process is inherently more tolerant than the p-well process to soft errors, the densely packed 1-µm memory cells become very soft because of the dominant effect of the channel width reduction. An advanced device-plus-circuit simulator was used to calculate the differential contribution from each of the vertical and lateral dimensional changes involved in the technology transition. Good agreement between the simulations and the experimental data is reached by properly correcting the 2D model to account for the phenomenal saturation effect involving very heavy ions.
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ABSTRACT: We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandia's 2Â¿m-technology 16K SRAMs are fabricated with a radiation-hardened 1-Â¿m CMOS process. An advanced 2D transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the 2-Â¿m process to the 1-Â¿m process. Error cross-section data, performed at the Berkeley cyclotron, on the first such device lot indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with the high-LET events is described and physical mechanisms responsible for the saturation are discussed.
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ABSTRACT: Data have been obtained with krypton and xenon ions for the latchup threshold vs. temperature of four different versions of a Harris CMOS/epi 16K static RAM. These special versions of the HM6516 RAM have 12-micron, 9-micron, 7-micron and 5-micron epi thicknesses, as grown. The test data showed a marked improvement in latchup resistance with decreasing epi thickness and with decreasing temperature over the range of 250 C (operating chip ambient) to 1000 C. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
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