The multiple valued logic (MVL) multiplier plays an important role in today's
arithmetic models, signal processing, FIR filters, big data processing and many
other applications. Owing to technological advances, several researchers have
been trying and preparing the development of the multipliers that set one of the
final technical parameters: high speed, low power consumption, the regularity of
layout, thus and so less area. Integrated Circuit Based Simulation Cadence software used to implement a multiplier. The simulation results have shown that the
development is more effective than the binary multiplier and the circuit will reach
a high speed, become smaller in size and have a minimum number of transistors.
The principles of Multiple-Valued Logic were then shown in this paper for design
of multiple valued octal logic multipliers. The most important factor is the implementation of MVL circuits which is superior to the binary valued circuits. When
decreased wire complexity compared to binary circuits, using a single wire to
transmit rather than several currents or voltages, it resulted with more information
per cable, improved computing capability, and more cost-effective circuits. The
Current-mode multiplier is designed to be based on radix 8. The multiplier is an electrical circuit that is used by computer devices like a
processor to multiply two numbers. In total, multiplication is a simple arithmetic
operation with 8.72 per cent of all instructions (Asadi, 07). Multiplication is also
a complicated process of delay. Typical loop multiplication is between 2 and 8
cycles (Santoro, 89). As a result, it is to be said that having high-speed multipliers
is crucial to the performance of the processors. Different methods can be used to
apply a multiplier; one of these techniques is MVL. Multiple valued or manyvalued logic is a discrete p-valued system. Multiple valued logic consists of discrete p-valued systems in which p>2 is used, non-binary valued systems (Dubrova, 99). The number of discrete logic levels in the MVL is not limited to two.
This is different from binary, with only two levels that are logic level 0 and logic
level 1; however, discrete variables with an infinite number of values can be
called MVL (Miller, 07). MVL has many useful applications and has been used
for the design of digital devices which use more than two discrete signal stages,
such as multiple-valued memories, multiple-valued arithmetic structures, fieldprogrammable gate arrays, etc. The key purpose of this work is therefore the development of the MVL multiplier.
Previously, Hanyu and Kameyama had developed a 200 MHz 54x54-bit multiplier using multiple-value current-mode MOS circuits (Hanyu, 95). The efficiency of the multiplier is calculated to be approximately 1.4 times higher than
that of the corresponding binary configuration under normalized energy dissipation. The special architecture of the current quaternary multiplier is indicated in
(Chu, 95). Without bias generation circuitry, the device comprises 49 MOS transistors and simulates worst-case delay with 0.2m CMOS technology, producing
output currents of around 10ms. Shimabukuro and Zukeran proposed Modulo 7
multipliers with a barrel shifter and a sign inverter consisting of 60 transistors.
Simulation findings for 0.8m CMOS and 5V power supply technologies indicate
a delay time of 4.32ns (Shimabukuro, 98). It has been stated from previous works
that the quaternary number was the most used one, but in MVL, the higher radix
would best reflect as many numbers as feasible.
Digital arithmetic operations are of considerable significance in the creation
of digital processors and application-specific devices. The arithmetic process in
digital equipment is a significant component of circuits. Amongst arithmetic circuits, adders are mostly used as basic building blocks, e.g., processor cores of DSP. According to the logic level of 'and' 1, binary adders are simple to implement, however, they have their redundant disadvantages in terms of circuit complexity and chip size, which eventually increases the delay in the propagation of
the circuits (Leela, 15). A much smaller chip area, the full-adder circuit displays
faster, more complex behavior than its binary alternatives. The drawbacks of current mode multi-valued logic circuits are higher static dissipation and lower noise
limits for high radix (Temel, 04).
A high-speed redundant binary architecture is developed by a fast parallel
CMOS multiplier. This design allows (one) to transform a pair of partial products
in normal binary form to a specific redundant binary number without any additional circuit. Makino et al. have enhanced the redundant binary adder circuit in
such a way that redundant binary partial items are added and the converter circuit
which converts the last redundant binary number to the corresponding binary
number is also optimized. The defined features of the converter circuit are carried
out with multiplexer circuits primarily. A 54x54-bit multiplier is fully compatible
with this architecture (Makino, 96). The width of the transmission gates can be
expanded to speed up all modifications. Trade-offs in field, speed, and power
must be determined in the scope of each specific application (Current, 95).
Kawahito et al. have shown that in some examples, MVL circuits have an
inherent advantage, like Wallace trees. The advantages to include with current
mode circuits are very noticeable. (Kawahito, 87). Clarke and Nudd suggested
different methods for constructing block libraries for general logic and arithmetic.
These techniques will enable the design of any circuit at basin level in typical
MVL mode (Clarke, 94). Sheng et al. suggests a new approach for ternary logic
circuits, using carbon nanotube FETs. Ternary logic can be a viable solution to
the traditional approach to binary logic design, since, in contemporary digital architecture, there are reduced overhead circuits such as interconnect and chip area
that promote stability and cost-effectiveness. With regard to the power delay in
the fully implemented design, the use of the suggested ternary gates combined
with binary gates solutions has been reduced by more than 90% (Lin, 09).
The efficiency of 3D graphics and signal processing systems relies heavily on
the performance of multiplications, which means that these techniques must
tackle highly multiplication-intensive operations. A great deal of work has also
been performed on sophisticated multiplication algorithms and patterns (Booth,
51), (Dadda, 65), (Elguibaly, 00), (Fadavi, 93), (Itoh, 01), (Kang, 04), (Kang, 93),
(Nagamatsu, 89), (Oklobdzija, 96), (Santoro, 89), (Stelling, 98), (Wallace, 64),
(Weinberger, 81), (Yeh, 00). There are three main steps of each multiplication.