sor, pattern generator, and timing generator (TG)]; in the last
The remaining sections are organized as follows. Section II 75
discusses the basic issues associated with signal integrity re- 76
volving around dc–dc converters. Furthermore, it introduces 77
an analytical model for jitter that is amenable to a frequency- 78
domain-measurement approach. A methodology for measuring 79
the jitter due to radiated EMI is then proposed in Section III, 80
followed by experimental results in Section IV. Finally, con- 81
clusions are drawn in Section V.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 20061
Measuring the Timing Jitter of ATE
in the Frequency Domain
Luca Schiano, Student Member, IEEE, Mariam Momenzadeh, Student Member, IEEE,
Fengming Zhang, Young Jun Lee, Student Member, IEEE, Thomas Kane, Member, IEEE,
Solomon Max, Life Senior Member, IEEE, Philip Perkins, Member, IEEE,
Yong-Bin Kim, Senior Member, IEEE, Fabrizio Lombardi, Senior Member, IEEE,
and Fred Jackie Meyer, Member, IEEE
Abstract—The objective of this paper is to provide a framework
by which jitter, in the output signals of a test-head board in an
automatic test equipment (ATE), can be measured. In this paper,
jitter phenomena caused by radiated electromagnetic interference
(EMI) noise are considered. EMI noise is mainly present in the test
head of an ATE as result of the activity of the dc–dc converters.
An analysis has been pursued to establish the areas of the
test-head board that are most sensitive to EMI noise. The most
sensitive part of the test-head board has been found to occur
in the loop filter of the phase-locked loop (PLL) that is used
to obtain a high-frequency clock for the timing generator (TG).
Different H-fields are then externally applied to the loop filter to
verify the behavior of the output signal in terms of rms jitter.
A frequency-domain methodology has been employed for the
rms-jitter measurements. The rms-jitter variation for the radiated
EMI magnitude and frequency has been characterized. Also, the
orientation of the external H-field source has been investigated
with respect to the target board and its effects on the measured
rms jitter. For measuring the jitter, an interface circuitry has been
designed on an adapter board to circumvent ground noise and
connectivity problems arising from the test-head environment.
Index Terms—Automatic test equipment, electromagnetic-
interference (EMI)-induced jitter, frequency domain, jitter char-
acterization, jitter measurement, test-head board.
tectures have undergone radical changes in operation and de-
sign . Past ATE architectures were based on shared resources
[i.e., all channels share components such as the test proces-
O MEET the challenge of designing and testing modern
integrated circuits, automatic-test-equipment (ATE) archi-
Manuscript received June 15, 2004; revised September 13, 2005. This work
was supported by LTX Corporation, Westwood, MA, and by the International
Test Conference Endowment at Northeastern University.
L. Schiano, M. Momenzadeh, F. Zhang, Y. J. Lee, Y.-B. Kim, and
F. Lombardi are with the Electrical and Computer Engineering Department,
Northeastern University, Boston, MA 02115 USA (e-mail: lschiano@ece.
neu.edu; firstname.lastname@example.org; email@example.com; firstname.lastname@example.org;
T. Kane, S. Max, and P. Perkins are with LTX Corporation, Westwood, MA
02090 USA (e-mail: email@example.com; firstname.lastname@example.org).
F. J. Meyer is with the Electrical and Computer Engineering Department,
Wichita State University, Wichita, KS 67260 USA (e-mail: fred.meyer@
Digital Object Identifier 10.1109/TIM.2006.861531
decades, so-called per-pin architectures have been developed 39
to provide flexibility in allocating to each channel its own TG. 40
In this type of architecture, all components (except for the test 41
processor) are integrated on a single board. Recently, ATEs 42
have been designed based on a per-pin test-processor architec- 43
ture, in which nearly all system components are integrated onto 44
a single chip.
This evolution has provided excellent test flexibility and 46
compactness, and has lowered per-chip costs. However, the new 47
generation of ATEs must provide high-frequency functionality 48
for testing high-performance devices-under-test (DUTs) with 49
no compromise on timing. Furthermore, the output-signal in- 50
tegrity of these ATE systems has become critical, because the 51
clock speed of the DUT is often in the gigahertz region. As 52
ATEs provide the necessary instrumentation for the generation 53
of tests and signals to the DUT at a high operating frequency, 54
jitter has emerged as a critical parameter . Also, a number 55
of chips may be simultaneously tested on an ATE, and testing 56
involves many pins on the same chip, so skew must be within 57
tolerable limits among signals (for different pins of the same 58
DUT) and DUTs (in the same or different boards). In multisite 59
testing, for example, the quality and repeatability of timing 60
require a very low jitter for reliable test results. To guarantee 61
quality, an evaluation of the timing jitter must be performed. 62
If the jitter is excessive, then corrective steps must be taken to 63
Among many signal-integrity problems, jitter due to radi- 65
ated electromagnetic interference (EMI) from switching power 66
supplies has raised concerns that are addressed in this paper. 67
The goal of this paper is to provide, through experimental 68
modeling, the framework by which jitter due to radiated EMI 69
can be predicted. A measurement methodology and a quali- 70
tative analysis (based on experimental results) are described. 71
While in , a time-domain-based technique was proposed 72
to measure the timing jitter. In this paper, frequency-domain- 73
based measurements are employed.
0018-9456/$20.00 © 2006 IEEE
supply module, a chiller system, a reference clock generator,
and multiple test-head boards, such as the one whose block
diagram is shown in Fig. 1.
A test-head board consists of memories, test-pattern gen-
erators, TGs, pin electronics, and programmable parametric-
measurement-function units. The memories store the test
vectors and the measured data collected from the DUT. The pat-
tern and TGs provide patterns and timing signals, respectively.
The pin-electronics circuitry merges the timing, pattern, and
format information to drive the DUT pin and compare the DUT
outputs with the expected data. The programmable parametric-
measurement unit acquires the dc-output parameters from the
The test-head board is made of circuits which require several
supply-voltage levels. DC–DC converters are usually utilized to
generate supply voltages. The use of dc–dc-converter technol-
ogy has several advantages .
compensating for a fault).
2IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 1.Block diagram of a test-head board in an ATE.
II. SIGNAL-INTEGRITY PROBLEM AND
This section introduces jitter problems due to radiated EMI
noise in the test-head board of an ATE and outlines a model for
the proposed analysis.
A. Test-Head Board and Signal-Integrity Problem
The ATE system under consideration consists of a power-
1) Converters are small enough to be mounted on the test- 107
head printed circuit board (PCB).
2) Converters can generate virtually any desired voltage 109
level, independent of the input level.
3) They are usually cheaper, smaller, and much more effi- 111
cient than linear power-supply modules.
However, dc–dc converters may cause EMI in the test- 113
head board due to switching and large current transients . 114
Therefore, the jitter of the test signal may be increased. At 115
current ATE operating frequencies, the timing margin of a 116
test measurement has significantly narrowed; moreover, it may 117
become worse due to the increasing clock speed by which 118
the ATE must operate for testing the DUT. The presence of 119
timing jitter can thus have a catastrophic impact on the test 120
outcome, as a good DUT could be diagnosed as faulty (due to 121
the jitter invalidating the timing measurement), or a bad device 122
may be accepted (if the jitter moves the timing in a direction 123
B. Phase-Noise Model
signal from its desired (ideal) position. An extensive treatment 127
of jitter can be found in  and .
In this paper, the phase-noise model has been adopted to 129
characterize the jitter . For the jitter in an ATE, this model 130
allows one to estimate the time-domain properties from the 131
AUTHOR PLEASE ANSWER ALL QUERIES
AQ1 = Please provide additional information in Ref. .
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Notes: 1) Please provide photo for author T. Kane.
2) Please provide IEEE membership history for authors L. Schiano, M. Momenzadeh, Y. L. Lee,
T. Kane, and P. Perkins.
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