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Design & Optimization of FinFET Based Schmitt Trigger Using Leakage Reduction Techniques
Abstract
In this proposed work we are applying valuable power gating schemes to FinFET based Schmitt trigger to enhance its performance by reducing the leakage current in standby mode (off-state mode). The power gating schemes like Sleep Transistor approach and Multi-Threshold CMOS (MTCMOS) have been analysed and simulated which shows the tremendous reduction in the leakage current thus increasing the stability of the design. In this paper, different consecutive designs of PULL-UP and PULL-DOWN networks of NMOS and PMOS are applied to FinFET based Schmitt trigger one after another. Due to this treatment of PULL-UP and PULL-DOWN network controlled voltage supply is obtained and the current driving capability of the design is increased, hence less Gate leakage current is formed. This provides the motivation to explore the design of low leakage FinFET based Schmitt trigger. Simulation is performed on the cadence virtuoso tool in 45nm technology and simulation results revealed that there is a significant reduction in leakage current for this proposed design. Leakage current offers by Sleep transistor approach and MTCMOS are 2.733 pA and 2.907 pA at 0.7 volt power supply.
... Multi Threshold CMOS or we can use the term MTCMOS in short is an effective power gating technique for sinking the sub-threshold leakages current [30]. Power gating techniques such as MTCMOS becomes more significant for lower voltage operation in FinFET because of good device topographies of FinFET based Schmitt trigger when we operate it in lower voltage supply [31]. The schematic of the FinFET based Schmitt trigger circuit using MTCMOS technique is shown in Fig. 7. ...
In the present-day VLSI system, low power design plays a noteworthy role. As we know that, a circuit with higher power consumption can ruin the performance of the system because in the modern world most of the systems are portable. Subsequently, they are functioned by the batteries. Therefore, it is desirable to have a system which operates at lower supply voltages along with maintaining the performance of the system. This low power system can be attained by abating the leakages of the devices up-to an enormous magnitude. In the contemporary VLSI system, a major role is being contributed by the Schmitt trigger circuit. Schmitt trigger is fundamentally a comparator. It is implemented by using a positive feedback. The Schmitt trigger circuit is used in various devices such as buffer, sub-threshold SRAM, sensors and PWM circuit. It is also used in analog to digital converter. The most significant property of the Schmitt trigger is that they provide hysteresis in their voltage transfer curve. Consequently, they provide better noise immunity as compared to their counterparts. Therefore it becomes quite important to enhance the performance of the Schmitt trigger circuit. The power dissipation of the device can be minimized by minimizing the sub-threshold current. The Schmitt trigger circuit is very imperative in producing a clean pulse from the input signal comprising of noise. There are various applications of Schmitt trigger circuit such as in scheming the oscillator circuit, analog to digital converter, function generator, signal conditioning and numerous applications. Thus, it becomes noteworthy to boost its performance by plummeting the leakages and power consumption of the Schmitt trigger circuit. We have realized the Schmitt trigger circuit by the use of FinFET. Therefore, we have got some optimum output in the parameters such as hysteresis width, power consumption and total noise of the Schmitt trigger circuit, but the leakages have been augmented. Thereafter, we have implemented several techniques on the Schmitt trigger circuit to shrink the leakage current, leakage power and other parameters further. We have applied Self Controllable Voltage Level, Adaptive voltage level and MTCMOS technique on the Schmitt trigger circuit using FinFET to further augment the presentation. All the circuits have been simulated in the virtuoso tool of the cadence in 45 nm VLSI domain. We have applied 0.7 V of the supply voltage to perform the simulation and got some tremendous outcome.
In this paper, we designed Schmitt trigger using CMOS low power design technique at 45nm technology. With the advancement of technology, different parameters have been calculated and analyzed to determine the performance of the circuit. With the change in technology, the aspect ratio of transistor sizing, variation in parameters also takes place. Different techniques are applied for the reduction in power consumption at the trade off with delay and area. In this paper we use novel FinFET technique to decrease the leakage power in the circuit. Schmitt trigger is a positive feedback amplifier that converts any continuous time varying signal to pulse wave. It forms the comparator of modern analog to digital convertor circuits, and it provides good noise immunity, thus it is used in communication. Parameters like slew rate, propagation delay, energy delay product etc of the circuit are calculated in both CMOS and FinFET technique and compared. Leakage power obtained using FinFET is 12.08PW which is very less to that of bulk CMOS. Designing is done with variable voltage supply and the performance of the circuit is observed at different points. The circuit is simulated in Cadence virtuoso tool version 6.1 output of all is compared.
Low-Power High-Speed Flip Flops (LPHSFF) are proposed in this paper. They are based on CMOS multi-threshold voltage techniques. High threshold voltage MOSFET transistors are applied on the non-critical paths of flip-flops in order to suppress the stand-by leakage-current, while low threshold voltage MOSFET transistors are applied on the cross-coupled critical path which in fact is the speed bottle neck of the flip-flip. This happened in order to increase the speed of operation of the circuit and to reduce the power dissipation. The proposed technique is usable in all types of flip-flops. Simulation results show the validity of the proposed technique to save power dissipation and to increase the speed of operation of the circuits. Using SPICE parameters of 0.25 um multi-threshold voltage CMOS technology, simulation results for 2.1 V supply voltage shown that 30% of power dissipation is reduced as the speed of operation is increased by 55%. Different applications are used to demonstrate the validity of the proposed technique. K e y w o r d s:
Summary form only given. We investigate scaling challenges and
outline device design requirements needed to support high
performance-low power planar CMOS transistor structures with physical
gate lengths (L<sub>GATE</sub>) below 50 nm. This work uses a
combination of simulation results, experimental data and critical
analysis of published data. A realistic assessment of gate oxide
thickness scaling and maximum tolerable oxide leakage is provided. We
conclude that the commonly accepted upper limit of 1 A/cm<sup>2</sup>
for gate leakage is overly pessimistic and that leakage values of up to
100 A/cm<sup>2</sup> are deemed acceptable for future logic technology
generations. Unique channel mobility and junction edge leakage
degradation mechanisms, which become prominent at 50 nm L<sub>GATE</sub>
dimensions, are highlighted using quantitative analysis. Source-drain
extension (SDE) profile design requirements to simultaneously minimize
short channel effects (SCE) and achieve low parasitic resistance for
sub-50 nm L<sub>GATE</sub> transistors are described for the first time
This paper proposes a new device and circuit scheme that
drastically suppresses the stand-by leakage current for the deep sub-0.1
μm era while maintaining the circuit speed. Applying boosted gate
voltage on the low leakage switches with higher V<sub>th</sub> and
thicker T<sub>ox</sub>, extremely low stand-by power for battery type
application is achieved, while degradation of circuit performance and an
increase of area overhead are sufficiently suppressed. The combination
with a negative gate voltage scheme and the application of the boosted
voltage scheme to SRAMs are also discussed
In low power design, it is difficult to suppress leakage current. In memory, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parameter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. As supply voltage is lowered, leakage power reduces. This paper models the DRV of SRAM module, and analyzes the SRAM cell stability when V-DD approaches DRV. DRV of the 4 KB SRAM module in a 0.13 mm technology ranges between 60 and 390 mv.
The CMOS device is used to achieve better performance in terms of speed, power dissipation, size, reliability and hysteresis. Schmitt trigger minimized power consumption and improving compatibility with low voltage power supplies and analog component the most effective solution is to
reduce the power consumption. This paper presented the performance comparison of 6T conventional, and 4T Schmitt trigger is used in such a way that by adjusting its threshold voltage, the signal can be made to increase early, thereby reducing the signal delay also due to less switching time,
power dissipation is less, circuit is simulated in cadence in both 180 nm and 45 nm technology, a simulation result show that 4T Schmitt trigger 12.3% delay reduction and 24% power reduction.
This paper enumerates low power, high speed design of Flip-Flops having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) Flip-Flop. As transistors used have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flops are analyzed at 90nm, 70nm and 50nm technologies. As the technology is scaled down, the leakage power increases, which is reduced by using MTCMOS technique. The designed Flip-Flops and Latches are compared in terms of power consumption, propagation delays and power dissipation product using DSCH and Microwind tools. Keywords CMOS, figure of merit, leakage current, power, delay, TSPC flip-flop.
This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells. Index Terms—Read static noise margin (RSNM), SRAM, standby power, variability.
The time has passed when traditional MOSFET scaling techniques were adequate to meet the needs of microprocessor products, but that has not meant the end of Moore's Law nor the end of improvements in microprocessor performance and power. In the new era of device scaling, innovations in materials and device structure are just as important as dimensional scaling. The past trend of using smaller transistors to build larger microprocessor cores operating at higher frequency and consuming more power is also at an end. The new era of microprocessor scaling is a system-on-a-chip approach that combines a diverse set of components using adaptive circuits, integrated sensors, sophisticated power-management techniques, and increased parallelism to build products that are many-core, multi-core, and multi-function. Although many promising technologies and device options are in the research pipeline, we need to recognize that we are doing system integration, and the future challenge we face is learning how to integrate an ever wider range of heterogeneous elements.
A simple logical threshold voltage control circuit is proposed. It can be implemented using normal conventional CMOS inverters. The proposed circuit is able to control a logical threshold voltage of a gate linearly and continuously over a range of a power supply voltage. Applications to the Schmitt trigger circuit with controllable hysteresis and a window comparator are shown to demonstrate practical usages of the proposed circuit.
The paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power with the higher engineering cost. The newer approach includes dynamic adaptive control of VDo and VTH at a block level. The paper also touches on low-power applications Trend of Power Consumption The power consumption of processors has been increasing for these 20 years as shown in Fig.1. It can be shown that the increase in power density comes directly from the scaling law and thus inevitable [1,2].
Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Turning Silicon on its edge
- E J Nowak
- I Aller
- T Ludwig
- Keunwoo Kim
- Rv Joshi
- Ching-Te Chuang
- R Bernstein
- Puri