Structural Optimization of SUTBDG Devices for Low-Power Applications

ArticleinIEEE Transactions on Electron Devices 52(3):360 - 366 · April 2005with5 Reads
Impact Factor: 2.47 · DOI: 10.1109/TED.2005.843869 · Source: IEEE Xplore


    In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-κ gate dielectrics raise the off-state current (I<sub>OFF</sub>) due to the fringing field-induced barrier lowering effect. Suppressing the I<sub>OFF</sub> increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I<sub>OFF</sub>, devices with less abrupt S/D-channel junctions suffer a drive current (I<sub>ON</sub>) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I<sub>ON</sub>. The I<sub>ON</sub> of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.