Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. This calculation is indispensable for reproducing the measured gate current-gate voltage characteristics in the device simulation. As a result, it is concluded that the scaling of the gate width cannot suppress the gate leak, even if the specification of the threshold voltage is relaxed in order to shrink the gate width. It is also found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.
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"The positive charge stored by DBs is, in this way, dependent on the electric field that determines E T − E F inside the SiON film, which has a notable influence on the gate current through the SiON film, as discussed in Section IV. It is noteworthy that the precise calculation of E F is indispensable for estimating the amount of the positive charge, which is described in detail in  and . In addition, E F has a significant influence on the estimation of the incomplete depletion layer  and the weak accumulation layer  at the interface with the gate polysilicon. "
[Show abstract][Hide abstract] ABSTRACT: Although the tunnel mass is indispensable to predict the gate leakage current of electron devices, it has been regarded as an adjustable parameter to fit the calculated leakage current with the measured ones. This appears useful because it enables calculation of the tunnel current while ignoring some details in advanced device modeling, even though it has veiled the intuitive nature of the modeling. More concretely, the adjustable tunnel mass pushes us to ignore the related issues that should carefully be considered. In this paper, we extract the tunnel masses for electrons and holes from an individual experiment and find that they are 0.85 m <sub>0</sub>, where m <sub>0</sub> is the rest electron mass, irrespective of the molecular compound ratio between Si<sub>3</sub>N<sub>4</sub> and SiO<sub>2</sub> and the film thickness. This suggests a convincing model for charge trapping in [(SiO<sub>2</sub>)<sub>1-x</sub>(Si<sub>3</sub>N<sub>4</sub>)<sub>x</sub>]<sub>1-y</sub>Si<sub>y</sub> including interfacial transition layers. It is also found that the leakage mechanism is the direct tunneling enhanced by the trapped positive charge.
Full-text · Article · Jun 2010 · IEEE Transactions on Electron Devices
"However , as the oxide thickness is continuously reduced, the oxide thickness under poly-silicon gate is no longer regarded as the same as previous papers . The direct tunneling leakage near the source–drain extension (SDE) and shallow trench isolation (STI) has become increasingly serious problem     . In this work, the gate current is treated as the sum of three components: the center channel leakage current, the STI-affected leakage current, and the SDE-affected leakage current. "
[Show abstract][Hide abstract] ABSTRACT: Gate dielectric leakage current becomes a serious concern as the gate oxide thickness of metal–oxide–semiconductor field-effect-transistors is less than 3nm. This thin oxide can conduct significant leakage current by various tunneling mechanisms and degrade circuit performance. A mathematical method of modeling the gate leakage current IG is presented in this work. Both the shallow trench isolation effect and the source–drain extension effect on IG are included. With suitably chosen transistor dimensions, the parameter extraction can be performed using the devices’ mask drawn size, and the troublesome effective device length and width are not necessary in this model. The extracted parameters and their temperature dependence were used to predict IG of devices with other different dimensions.
Full-text · Article · Feb 2008 · Solid-State Electronics
"However, the calculation of the band-gap narrowing in a degenerate semiconductor (e.g., n + gate polysilicon) is a complicated problem because the incomplete ionization of dopants and the band-gap narrowing are mutually affected –. The bandgap narrowing is based on the scattering theory, whereas the ionization problem is a bound state problem. "
[Show abstract][Hide abstract] ABSTRACT: A nanometer-scale variation of grain boundary locations in gate polysilicon is investigated in detail based on the assumption that the arrangement of grain boundaries obeys Poisson distribution. The statistics of grain boundaries described here reveals a relation between nanoscopic location and the arrangement of grain boundaries, which implies fluctuation in transistor characteristics of 45-nm and beyond MOSFETs
Full-text · Article · Feb 2007 · IEEE Transactions on Electron Devices