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MOSFET Scaling Limits Determined by Subthreshold Conduction
Abstract
The formulation and solution of the equations governing transistor
subthreshold behavior in explicit analytical form provide quantitative
predictions for minimum feature length as well as immediate information
on the relative importance of all major transistor fabrication
parameters. Such a formulation and a solution for subthreshold
conduction are presented. The importance of gate oxide thickness,
channel impurity concentration, source-drain junction depth, and applied
potentials are examined. The results suggest that successful advanced
process development programs must devise methods for ultrashallow
(<100 Å) source-drain junction formation and ultrathin (<50
Å) gate insulators. With vanishingly small (<50 Å)
junction depth, a 30 Å gate oxide dielectric and a channel
acceptor concentration of 2×10<sup>18</sup> per cubic centimeter,
one can achieve acceptably low subthreshold conduction at effective
channel lengths down to 0.06 μm at an operating temperature of 300 K
... A few V T rolloff models proposed to date include junction depth dependency but are not accurate for intermediate and shallow junction devices [47][60]. Pimbley [59] used the variational approach to find V T rolloff. Nguyen [60] considered cylindrical junctions and the equations are too complex to provide clear physical insight. ...
... Only one of (4) or (5) is needed for evaluating λ. Ratnakumar [54], Pimbley [59] and Liu [55] assume the bottom boundary condition to be (4), whereas Frank [62] uses (5). This work clarifies which of the two boundary conditions needs to be used to accurately model V T rolloff. ...
The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications. Ph.D. Committee Chair: Meindl, James; Committee Member: Allen, Phillip; Committee Member: Cressler, John; Committee Member: Davis, Jeffrey; Committee Member: Hess, Dennis
... Particularly, the analytical conduction expression in the subthreshold region is of great interest for the low-power application and high performance. In bulk MOSFETs [6] and conventional SOI MOSFETs [7]- [10], the subthreshold behavior has been discussed extensively, and various scaling theories have been proposed. ...
In this paper, the scaling theory of fin field-effect transistors (FinFETs) has been established by a 3D analytical solution and numerical simulation of Poisson's equation in the channel region. Considering the impact of ionized dopant in channel and source/drain on the potential distribution, respectively, the 3D Poisson's equation is analytically solved through the superposition method. Based on the analysis of the minimum channel potential, which is approximated from the evanescent mode, a useful and simple subthreshold-swing (S) model is proposed for design consideration. According to the derived scaling length, a FinFETs structure is superior in controlling short-channel effects (SCEs). A ratio of channel length to scaling length larger than three is required for optimization. Meanwhile, it is noticed that the gate material with relative dielectric constant of about ten could sufficiently suppress SCEs
... Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics the transition metal dichalcogenide MoTe 2 can be reversibly switched with electric-field-induced strain between the 1T′-MoTe 2 (semimetallic) phase to a semiconducting MoTe 2 phase in a field-effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors 3,4 . Using strain, we achieve large nonvolatile changes in channel conductivity (G on /G off ≈ 10 7 versus G on /G off ≈ 0.04 in the control device) at room temperature. ...
The primary mechanism of operation of almost all transistors today relies on the electric-field effect in a semiconducting channel to tune its conductivity from the conducting ‘on’ state to a non-conducting ‘off’ state. As transistors continue to scale down to increase computational performance, physical limitations from nanoscale field-effect operation begin to cause undesirable current leakage, which is detrimental to the continued advancement of computing1,2. Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics the transition metal dichalcogenide MoTe2 can be reversibly switched with electric-field-induced strain between the 1T′-MoTe2 (semimetallic) phase to a semiconducting MoTe2 phase in a field-effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors3,4. Using strain, we achieve large non-volatile changes in channel conductivity (Gon/Goff ≈ 10⁷ versus Gon/Goff ≈ 0.04 in the control device) at room temperature. Ferroelectric devices offer the potential to reach sub-nanosecond non-volatile strain switching at the attojoule/bit level5–7, with immediate applications in ultrafast low-power non-volatile logic and memory⁸ while also transforming the landscape of computational architectures because conventional power, speed and volatility considerations for microelectronics may no longer exist.
... This adds additional cost to the final product that offsets the density advantage of a finer lithographic process. In the case of MOSFETs, additional masking steps are necessary to modify the transistor's geometry and to alter the doping profile of the source and drain [Pimbley 1989][ Tanaka 1993]. Bipolar transistors require additional masking steps to make polysilicon contacts to the base and emitter and to reduce device capacitance with insulating sidewalls [Warnock 1995] [Nakamura 1995]. ...
A computer program models the electrical and thermal activity and the crystallization dynamics of small geometry, high crystallization speed, pseudobinary alloy chalcogenide switches. The results are compared with data taken on existing devices to verify the model. The model is then used to optimize the properties of switching devices and explore the limits of their capabilities which are compared with competing switching and memory technologies. 2 ACKNOWLEDGMENTS
... In 1989, Pimbley and Meindl concluded that MOST channel length can be reduced to 60nm, when using a very thin gate oxide thickness, very shallow drain junction depth, and high-channel doping levels. [10]. In 1991, Antoniadis and Chung, concluded that the minimum usable channel length was about 80nm, using the same arguments [11]. ...
... The first two criteria are based on subthreshold swing requirements of 70 mV/dec and 100 mV/dec, which correspond to excellent and moderate transistor turn-off characteristics, respectively. The third criterion mandates that threshold voltage rolloff from its long-channel value be less than 100 mV as an acceptable amount of short-channel effects [21]. The final criterion is that the "local" threshold voltage rolloff (i.e., the change of threshold voltage from its nominal value) should be less than 7% of the supply voltage when the channel length is 30% off its nominal value, which is similar to the criterion set forth in [22]. ...
Physics-based compact short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region. These models accurately characterize the subthreshold and near-threshold regions of operation by appropriately including essential phenomena such as volume inversion and the dominance of mobile charges over fixed charges under threshold conditions. Explicit, analytical expressions are derived for a scale length, which results from an evanescent-mode analysis. These equations readily quantify the impact of silicon film thickness and gate oxide thickness on the minimum channel length and device characteristics and can be used as an efficient guideline for device designs. These newly developed models are exploited to make a comprehensive projection on the scaling limits of undoped double-gate MOSFETs. On the individual device level, model predictions indicate that the minimum channel length can be scaled beyond 10 nm for a turn-off behavior of S=100 mV/dec for a silicon film thickness below 5 nm and an electrical equivalent oxide thickness below 1 nm.
... In addition, the subthreshold hump at the negative body bias worsens the functionality of the analog circuit, such as current mismatch in cascode current mirrors [8]. The off-state leakage and device mismatching caused by the subthreshold hump are also limitations of the device scale-down and analog circuit design using small geometry MOSFET [9,10]. ...
In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.
Using the static transfer curves derived from analytical drain
current and threshold voltage models for short-channel MOSFETs, MESFETs
and MODFETs, the FET scaling limits in CMOS and E/D MOSFET (NMOS),
MESFET, and MODFET DCFL digital circuits are determined as 0.025 μm,
0.05 μm, 0.075 μm, and 0.075 μm (respectively) from noise
margin considerations. The corresponding delay times of ring oscillators
using these minimum length devices are shown to be 6.37 ps, 5.07 ps.
2.44 ps and 2.61 ps, respectively
This paper presents a digital hardware implementation of a novel wavelet-based event detector suitable for the next generation of cardiac pacemakers. Significant power savings are achieved by introducing a second operation mode that shuts down 2/3 of the hardware for long time periods when the pacemaker patient is not exposed to noise, while not degrading performance. Due to a 0.13-μm CMOS technology and the low clock frequency of 1 kHz, leakage power becomes the dominating power source. By introducing sleep transistors in the power-supply rails, leakage power of the hardware being shut off is reduced by 97%. Power estimation on RTL-level shows that the overall power consumption is reduced by 67% with a dual operation mode. Under these conditions, the detector is expected to operate in the sub-μW region. Detection performance is evaluated by means of databases containing electrograms to which five types of exogenic and endogenic interferences are added. The results show that reliable detection is obtained at moderate and low signal to noise-ratios (SNRs). Average detection performance in terms of detected events and false alarms for 25-dB SNR is P<sub>D</sub>=0.98 and P<sub>FA</sub>=0.014, respectively.
An analytic threshold voltage model, which can account for the short channel effect and the fringing field effect of sub-100 nm high-k gate dielectric MOSFETs, has been developed. The model considers the two-dimensional (2D) effect both in silicon bulk and in gate dielectric layer. The results of the model are consistent with 2D numerical simulation results.
The aim of the present work is to investigate numerically the self-heating effect (SHE) in MOSFET transistors based on high-k material taking into account the deformation of the gate under the SHE. The SHE inside the MOSFET transistor is calculated using the electrothermal model based on heat transfer equation coupled with semiconductor equations. The electrothermal model have been solved in 2D-dimension using the finite element method. The high-k dielectric HfO 2 have been used as gate oxide. Several gate shapes have been used to analyze their impact on SHE. It is observed that the reduction of equivalent oxide thickness (EOT) reduces the SHE in the MOSFET transistor based in high-k dielectric material. the temperature peak increases quadratically with drain voltage for all MOSFET structures. A decrease in self-heating effect is achieved using the square gate shape.
This brief investigates the influence of source and drain junction depth on the short-channel effect (SCE) in highly scaled MOSFETs. The established scale length model represents SCE in terms of an exponential function of gate insulator thickness and gate depletion-layer width, but this model fails to account for any influence of source and drain junction depth on SCE. It is shown using two-dimensional finite-element device simulation that the influence of source and drain junction depth on SCE can be represented by an addition of a pre-exponential term to the established scale-length model. For source and drain junction depths that are deeper than the MOSFET's gate depletion-layer width, SCE is shown with this pre-exponential term to be insensitive to junction depth. Conversely, for source and drain junction depths that are shallower than the MOSFET's gate depletion-layer width, SCE is shown to improve linearly with decreasing junction depth.
The authors suggest that beyond 2003, further opportunities for
GSI will be governed by a hierarchy of theoretical and practical limits
whose levels can be codified as: (1) fundamental, (2) material, (3)
device, (4) circuit, and (5) system. Theoretical limits are elucidated
by plotting the average power dissipation during a binary switching
transition of a logic gate P versus the corresponding gate delay time t
<sub>d</sub> and the reciprocal length squared of an interconnect versus
the response time of the interconnect circuit. Using both the hierarchy
of theoretical limits and the history of practical limits as guides, a
one-billion-transistor chip is again projected by the year 2000 and the
possibility of a one-trillion-transistor chip by the year 2020 is
suggested
As the effective channel length of conventional MOSFET's
approaches the sub-0.1 μm regime, further downscaling of integrated
circuits may require new transistor structures. In this paper we propose
a new tunneling field-effect transistor. According to its new operating
principle, the tunneling current between two terminals is strongly
modulated by the bias applied to the third terminal. Different from the
planar structure of MOSFET's, the three terminals of this transistor are
vertically stacked up. This new tunneling transistor is free of the
short-channel effects, and its lateral dimension can in principle be
scaled down to nanometers. The design of new transistor structure,
calculated results and scaling properties are discussed
Three-dimensional device-physics-based analytical models are
developed for subthreshold conduction in uniformly doped small geometry
(i.e., simultaneously short channel and narrow width) bulk MOSFETs, for
various isolation schemes. Inverse-narrow width effects, where the
threshold voltage decreases with decreasing channel width, are predicted
by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs,
conventional narrow width effects, where the threshold voltage increases
due to decreasing channel width, are predicted. The narrow width effects
are found to be comparable to the short channel effects in the absence
of significant applied drain biases. However, for larger drain biases,
the short channel effects outweigh the narrow width effects due to the
weaker potential perturbation at the device width edges compared to the
drain end. Unlike the threshold voltage, the subthreshold swing of the
device is found to increase with reduced device dimensions regardless of
the isolation scheme since both conventional and inverse narrow width
effects result in weaker control of the surface potential by the gate
Short-channel effects in GaAs MESFETs are investigated. MESFETs
were fabricated with gate lengths in the range of 40 to 300 nm with GaAs
and AlGaAs buffer layers. The MESFETs were characterized by DC
transconductance, output conductance, and subthreshold measurements.
This work focuses on overcoming the short-channel effect of large output
conductance by the inclusion of an AlGaAs buffer layer, and identifying
the benefit the AlGaAs buffer affords for reducing subthreshold current,
including the effect of drain-induced barrier lowering. The design
yielded 300-nm gate-length MESFETs with excellent suppression of the
major short-channel effects
Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal-oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, self-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore's law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap.
The authors discuss some of the effects quantum mechanics has on
the performance of nanometer-scale devices. At low temperature, the
confinement and the coherence of the electronic motion on the scale of
the electron wavelength give rise to gross deviations from classical
charge transport that describes the resistance found in large
conventional devices. The authors examine three examples of the quantum
mechanical nature of the resistance of a split-gate MODFET, that are not
accounted for in conventional classical models of a FET, and yet may
influence device speed, noise performance and device isolation. The
authors consider the temperature and electric field ranges where quantum
mechanical effects are manifested in the charge transport, and speculate
about the conditions in which parasitic quantum mechanical effects might
be found in a conventional device
We use a fully quantum-mechanical model to study the inversion
layer mobility in a silicon MOS structure. The importance of depletion
charge and surface-roughness scattering on the effective electron
mobility is examined. The magnitude of the mobility is found to be
considerably reduced by both depletion charge and interface-roughness
scattering. The appropriate weighting coefficients a and b for the
inversion and depletion charge densities in the definition of the
effective electric field, which eliminate the doping dependence of the
effective electron mobility, are also calculated. These are found to
differ from the commonly used values of 0.5 and 1. In addition, the
weighting coefficient for the depletion charge density is found to be
significantly influenced by the actual shape of the doping profile and
can be either >1 or <1
Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2003. Directed by James D. Meindl. Includes bibliographical references (leaves 228-238).
An analytical model is developed to describe the drain-current characteristics of small-geometry (i.e. sub-0.15 μm) bulk MOSFET's including both non-local transport and 3D channel charge control. The model is used to investigate effects of velocity overshoot and subthreshold degradation on the performance and scaling of bulk Si MOSFET's
Using the variational method, the two dimensional Poisson Equation
is solved in the MOSFET device region including the gate oxide region,
depletion region and buried oxide region (for SOI device). An analytical
expression for the potential distribution together with a new natural
gate length scale for MOSFET is derived. The 2-D effects in front gate
dielectric, back gate dielectric and silicon film can all be taken into
account in this derivation. The validity of electrical equivalent oxide
thickness approximation is also investigated using this model.
Comparison of the short channel effect for uniform channel doping bulk
MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double
gated MOSFET is conducted using our model. The results are verified by
2D numerical simulation using the 2D device simulator MEDICI
In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.
In this letter, we report a new approach to treat the 2-D nonlinear Poisson's equation in the context of MOS devices and discuss its application in the modeling of tunneling field-effect transistors (T-FET). It is revealed that the narrowing of tunneling barrier in T-FET has different mechanisms before and after inversion layer is formed. Closed-form equation is obtained to describe the barrier narrowing in the presence of inversion layer.
In this paper, a threshold voltage model for high-k gate-dielectric metal–oxide-semiconductor field-effect transistors (MOSFETs) is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.
Using As+2 ion implantation and rapid thermal anneal, 40-nm n+-p junctions are realized. The junction formed with p- substrate shows very low leakage current (< 0.5 nA/cm2) up to 2-V reverse bias. The introduction of a heavily doped (1018 cm-3 level) p region generates a significantly higher leakage current due to the onset of band-to-band tunneling. Using varied geometry devices with a given area, the major tunneling current is shown to be confined in the perimeter of the device, and a method to suppress this leakage is suggested.
This paper presents the influence of polysilicon depletion effect (PDE) on the potential drop across polysilicon gate. The effect of the gate doping and oxide thickness variations on the PDE has been investigated using MINIMOS 6.1 respectively. These parameter variations have been shown to be the factors that contribute to the polysilicon-gate depletion effect that lead to the increase of the potential drop and degradation in device performance. Besides that, polysilicon depletion effect can be improved by reducing the oxide thickness (tox) and gate doping concentration (Np).
Accurate threshold voltage (V-T) modeling of bulk-MOSFETs is important for device optimization and circuit simulation. Existing VT models cannot model the impact of source/drain junction depth on V-T rolloff. A new model is proposed that can accurately model bulk-MOSFET VT including the source/drain junction depth. The model also provides a scale-length that can be used to rapidly predict the minimum channel-length for a given set of technology parameters. (c) 2007 Elsevier Ltd. All rights reserved.
We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.
The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-20nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020, resulting in significant changes in both the information processing technology as well as the device manufacturing technology. The most promising devices now a days are DG-MOSFET and FDSOI-MOSFET. In this paper downscaling design and simulation of NMOS transistor with 18nm gate length considered. A hafnium oxide (HfO2) is used as the high k material instead of SiO2 with Al metal gate. The LDDG (Lightly Doped Double Gate) MOSFET and FDSOI NMOS transistor and electrical characteristics is simulated using GENIUS simulator. A simulation results optimal values of threshold voltage (Vth), Leakage currents and ION/IOFF ratio. The ION/IOFF of DG-MOSFET is 3.4 times greater than the FDSOI.
New boundary conditions and a 2D potential distribution along the channel of a high-k gate-dielectric MOSFET, including both the gate dielectric material region and the depletion region, are given. Based on this distribution, a 2D threshold-voltage model with the fringing-field and short-channel effects is developed for a high-k gate-dielectric MOSFET. The model agrees well with experimental data and a quasi 2D model, and is even more accurate than the quasi 2D model at higher drain voltages. Factors affecting the threshold behavior of the high-k gate-dielectric MOSFET are discussed in detail.
Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.
The primary mechanism of operation of almost all transistors today relies on electric-field effect in a semiconducting channel to tune its conductivity from the conducting 'on'-state to a non-conducting 'off'-state. As transistors continue to scale down to increase computational performance, physical limitations from nanoscale field-effect operation begin to cause undesirable current leakage that is detrimental to the continued advancement of computing. Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics (FEs) the transition metal dichalcogenide (TMDC) MoTe$_2$ can be reversibly switched with electric-field induced strain between the 1T'-MoTe$_2$ (semimetallic) phase to a semiconducting MoTe$_2$ phase in a field effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors (FETs). Using strain, we achieve large non-volatile changes in channel conductivity (G$_{on}$/G$_{off}$~10$^7$ vs. G$_{on}$/G$_{off}$~0.04 in the control device) at room temperature. Ferroelectric devices offer the potential to reach sub-ns nonvolatile strain switching at the attojoule/bit level, having immediate applications in ultra-fast low-power non-volatile logic and memory while also transforming the landscape of computational architectures since conventional power, speed, and volatility considerations for microelectronics may no longer exist.
Analytical device-physics-based models for subthreshold drain
current in short channel SOI MOSFETs facilitate accurate and efficient
circuit simulation. These models also enable prediction of device
scaling limits determined by subthreshold conduction and comparison of
these limits with bulk MOSFETs for the same threshold and supply
voltages
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.
The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swing S needed to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects.
In this survey we do not intend to mention all types of numerical procedures but to look only on some special methods, which were used frequently in recent years or which deserved perhaps to be used more than hitherto.
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Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.
Time dependent dielectric breakdown (TDDB) data for 100Ã
of thermally grown SiO2 has been analyzed using an Eyring model based on thermodynamic free energy considerations. The model describes well the following features of the data: (1) an apparent activation energy which is a function of the stressing electric field and (2) a field acceleration parameter that is a function of temperature. Quantitatively, the model suggests the proper field dependence for the activation energy and the observed temperature dependence of the field acceleration in the 100Ã
oxide material. The apparent activation energy is found to decrease from > leV at low field stressing (Eb(50%) - Es > 5 MV/cm) to <0.3eV at higher fields Eb(50%)- Es < 3 MV/cm). Also, the field acceleration was found to be approximately 6 decades/MV/cm at room temperature but reduces to 2 decades/MV/cm at 150C.
This paper describes a method to improve the electromigration capacity of Al‐Cu or Al thin‐film interconnection metallurgy by incorporating a layer of intermetallic compounds of Al and transition metals. The improvement in lifetime can be 100 times greater than comparable Al‐Cu structures tested under the same conditions. Certain structural properties of the intermetallic compounds have been related qualitatively to the failure mode and electromigration lifetime. Results are discussed in an attempt to clarify the mechanisms by which an ordered phase (compound layer) can improve electromigration lifetime. Life‐test data obtained from the thin‐film metallurgy with Al–transition‐metal compound structures indicate that improvements can be achieved by one or a combination of the following factors: (a) blocking void propagation through the film, (b) reducing the rate of mass transport by electromigration, and (c) eliminating divergent damage sites by increasing the degree of preferred grain orientation. In many cases, the thickness of the intermetallic layer can be adjusted to yield a significant improvement in lifetime with only a small increase in stripe resistance.
N-type poly Si has no serious influence on thin oxides down to about 30 Ã
. For a boron-doped poly-Si gate, however, current increase characterized by negative gate bias is found. For an Mo gate, gate oxide surface layer of about 20 Ã
next to the gate are deteriorated. By minimizing boron diffusion from a boron-doped poly-Si and Mo penetration during Mo gate formation, both gates will be of practical use for thin gate oxide down to near 30 Ã
.
A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.
An analytical solution for the potential distribution of the two-dimensional Poisson's equation with the Dirichlet boundary conditions has been obtained for the MOSFET device by using Green's function method and a new transformation technique, in which the effects of source and drain junction curvature and depth are properly considered. Based on the calculated potential distribution, the subthreshold current considering the drain-induced barrier lowering effects has been computed by a simple current equation that considers only the diffusion component with an effective length determined by the potential distribution at the SiO 2 -Si interface. From the calculated subthreshold current, the threshold voltage of the MOSFET's is determined. It has been verified that the dependences of the calculated threshold voltage and subthreshold current on device channel length, drain, and substrate biases are in good agreement with those computed by whole two-dimensional numerical analysis and experimental data.
Series resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. Material properties associated with the interconnect metal, the semiconductor, and the interface separating the two regions thus assume greater importance. An analytical formulation of the resistance in terms of these material properties is thus quite desirable. We formulate and solve a two-dimensional model of current flow by the method of matched asymptotic expansions. The major utility of this solution is provided by higher order corrections to the standard transmission line model of current flow in the ohmic contact region. We find that present methods for the extraction of material properties from experimental measurements with a transmission line model analysis would be enhanced by the inclusion of higher order terms we present here.
Parasitic resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. The majority of this resistance arises from the contact resistance of the metal-semiconductor interface and the resistance of the semiconductor source and drain regions. The most popular method for deriving current flow in this region is the transmission line model. Though this model has proven quite useful, the severe restriction of one-dimensional current flow will introduce errors in some situations. We formulate and solve a more sophisticated dual-level transmission line model in which we incorporate to first order the two-dimensional nature of the current flow. We discuss this model in terms of an enhancement to the transmission line model and present a detailed comparison of the two models. We find that the dual-level transmission line model produces significant (12 percent) corrections to the transmission line model with source resistivity and thickness and specific contact resistivity typical of 1-µm design rule technologies.
Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.
An analytic MOST model has been developed to calculate accurately threshold voltage at submicrometer dimensions and to predict the scaling limits of digital CMOS circuits. Salient results show that for 2-V power-supply voltages, channel lengths as small as 0.14 µm for static E/E CMOS, 0.26 µm for static E/D CMOS, 0.29 µm for dynamic transmission-gate CMOS, and 0.45 µm for static E/D NMOS circuits are possible. At submicrometer dimensions, CMOS offers as much as a 3:1 scaling advantage in minimum channel length which translates to a 5:1 improvement in gate delay when compared to NMOS. Thus CMOS is projected as the dominant ULSI technology, not only due to its well known large operating margins, low static-power dissipation and design flexibility but also due to markedly superior speed.
In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.
A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.
In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10<sup>14</sup>-1 × 10<sup>16</sup>cm<sup>-3</sup>for punchthrough and 2 × 10<sup>15</sup>-5 × 10<sup>16</sup>cm<sup>-3</sup>for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.
The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swing S needed to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects. For uniformly doped structures it is shown that curves of given S can be constructed on an oxide thickness versus doping level plot, making estimates of S for any choice of these parameters particularly simple. A separate family of curves is needed for each value of source-to-substrate bias V S . Source-to-substrate reverse bias greatly reduces S in devices with large S values, but cannot reduce S to its theoretical minimum value, S_{min} = (kT/q) ln 10, at reasonable values of V S . It is found that the effect of nonuniform doping is determined mainly by the dose and centroid of the depleted portion of the excess surface doping, provided buried channels do not occur and provided the implant is not primarily located in the inversion layer itself. Higher doses and deeper implants increase S . The maximum value of S for a given implant dose and source-to-substrate reverse bias occurs for that range of implantation which places the implant near the depletion edge. Consequently, the use of implants in small MOSFET's to control threshold punchthrough and parasitic capacitances will cause turnoff degradation.
Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.
A general model of hot-electron effects is briefly reviewed; the model includes device degradation and the simple and close correlations among the different effects. The symptoms and the time dependence of device degradation are then presented, and a few controversial issues, such as interface states versus electron trapping and hot electrons versus hot holes, are discussed. A physical model of device degradation is then proposed to explain the symptoms and the dynamics. A simple physical model of device degradation is then proposed to explain the symptoms and the dynamics. A simple physical model that relates E//m , the maximum channel electric field, to all the device parameters and the bias voltages is presented. On the bass of this model, a very simple means of characterizing I//s //u //b , which serves as a monitor for all the hot electron effects, is introduced. Finally, the prospect of suppressing E//m and the impact of LDD structures are briefly discussed in the light of the E//m model.
A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.
An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.
This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 μ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.
A 46 ns 256K CMOS RAM
- M Isobe
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Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis VLSI limitations from drain-induced bamer low-ering Analysis and Solution of Partial Differential Equations
- T Toyabe
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Small-geometry MOS transistors: Physics and mod-eling of surface-and buried-channel MOSFETs
- T N Nguyen
T. N. Nguyen, " Small-geometry MOS transistors: Physics and mod-eling of surface-and buried-channel MOSFETs, " Ph.D. dissertation,
Short-channel MOST thresh-old voltage model Performance limits of CMOS ULSI A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped sub-strates
- K N Ratnakumar
- J D Meindli
- J R Pfiester
- J D Shott
- J D Meindl
- J D Kendall
- A R Boothroyd
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Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET A fully scaled submicrometer NMOS technol-ogy using direct-write E-beam lithography
- J R Brewsi
- M R Wordeman
- A M Schweighart
- R H Dennard
- G Sai-Halasz
- W W Molzen
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