Article

MOSFET Scaling Limits Determined by Subthreshold Conduction

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Abstract

The formulation and solution of the equations governing transistor subthreshold behavior in explicit analytical form provide quantitative predictions for minimum feature length as well as immediate information on the relative importance of all major transistor fabrication parameters. Such a formulation and a solution for subthreshold conduction are presented. The importance of gate oxide thickness, channel impurity concentration, source-drain junction depth, and applied potentials are examined. The results suggest that successful advanced process development programs must devise methods for ultrashallow (<100 Å) source-drain junction formation and ultrathin (<50 Å) gate insulators. With vanishingly small (<50 Å) junction depth, a 30 Å gate oxide dielectric and a channel acceptor concentration of 2×10<sup>18</sup> per cubic centimeter, one can achieve acceptably low subthreshold conduction at effective channel lengths down to 0.06 μm at an operating temperature of 300 K

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... A few V T rolloff models proposed to date include junction depth dependency but are not accurate for intermediate and shallow junction devices [47][60]. Pimbley [59] used the variational approach to find V T rolloff. Nguyen [60] considered cylindrical junctions and the equations are too complex to provide clear physical insight. ...
... Only one of (4) or (5) is needed for evaluating λ. Ratnakumar [54], Pimbley [59] and Liu [55] assume the bottom boundary condition to be (4), whereas Frank [62] uses (5). This work clarifies which of the two boundary conditions needs to be used to accurately model V T rolloff. ...
Article
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... Particularly, the analytical conduction expression in the subthreshold region is of great interest for the low-power application and high performance. In bulk MOSFETs [6] and conventional SOI MOSFETs [7]- [10], the subthreshold behavior has been discussed extensively, and various scaling theories have been proposed. ...
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... This adds additional cost to the final product that offsets the density advantage of a finer lithographic process. In the case of MOSFETs, additional masking steps are necessary to modify the transistor's geometry and to alter the doping profile of the source and drain [Pimbley 1989][ Tanaka 1993]. Bipolar transistors require additional masking steps to make polysilicon contacts to the base and emitter and to reduce device capacitance with insulating sidewalls [Warnock 1995] [Nakamura 1995]. ...
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... In 1989, Pimbley and Meindl concluded that MOST channel length can be reduced to 60nm, when using a very thin gate oxide thickness, very shallow drain junction depth, and high-channel doping levels. [10]. In 1991, Antoniadis and Chung, concluded that the minimum usable channel length was about 80nm, using the same arguments [11]. ...
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First Page of the Article
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Series resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. Material properties associated with the interconnect metal, the semiconductor, and the interface separating the two regions thus assume greater importance. An analytical formulation of the resistance in terms of these material properties is thus quite desirable. We formulate and solve a two-dimensional model of current flow by the method of matched asymptotic expansions. The major utility of this solution is provided by higher order corrections to the standard transmission line model of current flow in the ohmic contact region. We find that present methods for the extraction of material properties from experimental measurements with a transmission line model analysis would be enhanced by the inclusion of higher order terms we present here.
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Parasitic resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. The majority of this resistance arises from the contact resistance of the metal-semiconductor interface and the resistance of the semiconductor source and drain regions. The most popular method for deriving current flow in this region is the transmission line model. Though this model has proven quite useful, the severe restriction of one-dimensional current flow will introduce errors in some situations. We formulate and solve a more sophisticated dual-level transmission line model in which we incorporate to first order the two-dimensional nature of the current flow. We discuss this model in terms of an enhancement to the transmission line model and present a detailed comparison of the two models. We find that the dual-level transmission line model produces significant (12 percent) corrections to the transmission line model with source resistivity and thickness and specific contact resistivity typical of 1-µm design rule technologies.
Article
Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.
Article
An analytic MOST model has been developed to calculate accurately threshold voltage at submicrometer dimensions and to predict the scaling limits of digital CMOS circuits. Salient results show that for 2-V power-supply voltages, channel lengths as small as 0.14 µm for static E/E CMOS, 0.26 µm for static E/D CMOS, 0.29 µm for dynamic transmission-gate CMOS, and 0.45 µm for static E/D NMOS circuits are possible. At submicrometer dimensions, CMOS offers as much as a 3:1 scaling advantage in minimum channel length which translates to a 5:1 improvement in gate delay when compared to NMOS. Thus CMOS is projected as the dominant ULSI technology, not only due to its well known large operating margins, low static-power dissipation and design flexibility but also due to markedly superior speed.
Article
In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.
Article
A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.
Article
In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10<sup>14</sup>-1 × 10<sup>16</sup>cm<sup>-3</sup>for punchthrough and 2 × 10<sup>15</sup>-5 × 10<sup>16</sup>cm<sup>-3</sup>for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.
Article
The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swing S needed to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects. For uniformly doped structures it is shown that curves of given S can be constructed on an oxide thickness versus doping level plot, making estimates of S for any choice of these parameters particularly simple. A separate family of curves is needed for each value of source-to-substrate bias V S . Source-to-substrate reverse bias greatly reduces S in devices with large S values, but cannot reduce S to its theoretical minimum value, S_{min} = (kT/q) ln 10, at reasonable values of V S . It is found that the effect of nonuniform doping is determined mainly by the dose and centroid of the depleted portion of the excess surface doping, provided buried channels do not occur and provided the implant is not primarily located in the inversion layer itself. Higher doses and deeper implants increase S . The maximum value of S for a given implant dose and source-to-substrate reverse bias occurs for that range of implantation which places the implant near the depletion edge. Consequently, the use of implants in small MOSFET's to control threshold punchthrough and parasitic capacitances will cause turnoff degradation.
Article
Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.
Article
A general model of hot-electron effects is briefly reviewed; the model includes device degradation and the simple and close correlations among the different effects. The symptoms and the time dependence of device degradation are then presented, and a few controversial issues, such as interface states versus electron trapping and hot electrons versus hot holes, are discussed. A physical model of device degradation is then proposed to explain the symptoms and the dynamics. A simple physical model of device degradation is then proposed to explain the symptoms and the dynamics. A simple physical model that relates E//m , the maximum channel electric field, to all the device parameters and the bias voltages is presented. On the bass of this model, a very simple means of characterizing I//s //u //b , which serves as a monitor for all the hot electron effects, is introduced. Finally, the prospect of suppressing E//m and the impact of LDD structures are briefly discussed in the light of the E//m model.
Article
A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.
Article
An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.
Article
This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 μ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.
A 46 ns 256K CMOS RAM
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Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis VLSI limitations from drain-induced bamer low-ering Analysis and Solution of Partial Differential Equations
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Small-geometry MOS transistors: Physics and mod-eling of surface-and buried-channel MOSFETs
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Short-channel MOST thresh-old voltage model Performance limits of CMOS ULSI A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped sub-strates
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Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET A fully scaled submicrometer NMOS technol-ogy using direct-write E-beam lithography
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