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Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells



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Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
Insights of Performance Enhancement Techniques on
FinFET-based SRAM Cells
Girish H.
Research Scholar,
J C BOSE Centre for
Research & Development,
Dept. of ECE, Cambridge
Institute of Technology,
K.R.Puram, Bangalore, India
Shashikumar D. R., PhD
Professor and HOD,
Dept. of Computer science Engg.
Cambridge Institute of Technology,
K.R.Puram, Bangalore, India
With the advancement in the energy efficient storage system,
FinFET has already gained a pace in the area of computational
memory management. However, after reviewing the research
work focusing on FinFET based SRAM cells till date, we
found that amount of research work towards enhancement of
the design principle has not been much in number. Hence, we
study some of the recently introduced research contribution
towards enhancing the design performance of FinFET based
SRAM cells and found that majority of the technique have both
advantages and limitations too. We also highlights the
significant research gap from the existing studies in order to
assist the readers aware of the practicality of the research
progress in this regards.
FinFET, SRAM, Leakage Power, Energy Efficiency, CMOS,
With the modernization of the VLSI and need of superior grade
storage system, FinFET SRAM has been evolved as a boon to
offer 10nm size of transistor design [1]. The prime reason of
this revolutionary technology is due to three dimensional
design of the gate controls which is lowering its controlling
dependencies from conventional drain and source terminal
[2][3]. In conventional transistor design, inclusion of new
components calls for short channel effect, which is completely
mitigated by present design principle of FinFET [4]. Not only
this, FinFET also addresses the problem of variation of
arbitrary dopant as there is no channel doping mechanism in it.
This phenomenon causes higher resistance from any form of
potential errors or any other fluctuation caused from to process
itself [5]. Along with this there are also less number of energy
points as well as less number of points for product of delay and
energy in FinFET circuits causing lowering of levels of supply
voltage in comparison to planer CMOS design. Therefore,
better stability in the voltage is achieved using FinFET. At the
same time, the area of storage system like SRAM suffers from
high allocation of cache memory in the chip area as well as it
also suffers from maximum energy consumption of the chip
power [6]. SRAM is used to perform three significant
operation in a storage management i.e. standby, read, and write
operation. SRAM is found better than DRAM with respect to
volatility, speed, cost, density, reliability etc. The prime trade-
offs in the design principle of the SRAM are i) speed vs
leakage current, ii) read vs write stability, and iii) area vs yield.
It is required that an SRAM cell should work faster and should
dissipate less leakage power, which unfortunately is still an
open end problem. The minimum voltage that a memory cell
can use for performing reading operation is called as read
voltage. Whereas the write voltage is just the opposite of it i.e.
maximum voltage to perform write operation. Hence for better
stability during read and write operation, it is required that read
and write voltage should be kept minimum and driving strength
of AC transistor should be make weaker and stronger during
read and write operation respectively [7].
Another problem with existing SRAM is that it has shifted into
the large scaled technologies in node design that consider
smaller size with minimized level of voltage. This causes
narrowing of the difference between the cut-off voltage and the
supply voltage. Sometimes, the level of the voltage becomes
highly unstable especially in the cache design in CPU where
the system design calls for inclusion of transistors with higher
reduced size in order to maintain large storage points. It is
believed that voltage scaling causes bottlenecks in memory
system and in order to address this problem, it is preferred to
jointly study FinFET with SRAM. This integrated design
principle offers a potential energy efficient feature in storage
access design. We have also observed that there are lesser
extent of studies that has focused on features of cache
memories of SRAM cells. The prime difference between the
conventional planar CMOS and FinFET is actually the fin,
which is responsible for furnishing the channel for propagating
the current in the switched on stage of the device. The gate
surrounds the vertical fins on all the three sides in order to
accomplish a superior control system over the channel. This
control system automatically minimizes the short channel
effect. The other significant attributes of FinFET are width of
fin, height of fin, thickness, length of fin, and underlap of gate
(i.e. distance between drain (or source) terminal to strip of
gate). The incorporation of gate underlap assists in addressing
the effect of current from source-to-drain, which further
increase the robustness of FinFET devices to short channel
effect. This paper reviews some of the techniques introduce
most recently to enhance the design principles of FinFET based
SRAM cells and discusses the research gap from the most
recent literatures. Section II discusses about the essential of
SRAM as well as FinFET design principle followed by
discussion of existing techniques in Section III with respect to
advantages and limitations of each techniques discussed in this
section. Section IV briefs about the research gap after
reviewing the existing system followed by Summary of the
paper in Section V.
As known RAM or Random Access Memory is one of the
essential storage form in any forms of computing device. RAM
is again classified into Static RAM (SRAM) and Dynamic
RAM (DRAM). SRAM uses 6 transistors of cell structure to
store a bit of data. It is characterized by beneficial factors e.g.
Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
faster access, less power utilization although it is quite
expensive to design [8]. Normally, flip-flop circuit is used for
developing SRAM cells and is found to usually used with Field
Effect Transistor (FET or unipolar transistor) [9]. The prime
purpose of FET is to channelize the transmission from source
to drain. There are three types of terminals in FET i.e. source,
drain, and gate, which can be seen on any cross section of
MOSFET as shown below:
n + n +X
Oxide Gate
Figure 1. MOSFET Cross Section
As SRAM is majorly implemented with FinFET, so it is
essential to brief about evolution and operations of FinFET that
has evolved during 1990 by DARPA. A novel structure for a
unique transistor was presented by Dr. Chenming Hu in order
to minimize leakage current. The research towards FinFET was
then taken over by group of researchers in Berkley who
recommended use of MOSFET of thin body to minimize
leakage. Fig.2 shows the original structure of FinFET.
Source Drain
Buried Oxide
(a) Ultra-Thin Body
Source Drain
(b) Double Gate
Figure 2 Evolution of FinFET from MOSFET
The evolved structure assists in minimizing the leakage current
by changing the orientation of the original double gate
structure (Fig.2(b)). This phenomenon allows auto aligning of
the gate electrodes by conventional lithography methods which
is almost equivalent to planar structure of FET (Fig.3(a))
Source Drain
(a) Planer-double Gate FET
(b) FET with 90% rotation
Fin height
Fin width=Tsi
(c) FinFET
Figure 3 Evolution of FinFET
The FinFET design at present time is highly three dimensional
and offers all possible way to minimize the leakage of power
from its body during the off state of FinFET device. It was also
believed that scalability of the FinFET can be maintained by
scaling the channel thickness.
2.1 Aim of FinFET
The general aim of adoption of FinFET is to mainly ensure the
reduction of leakage current to maximum degree although the
processing cost of its three dimensional structure can slightly
go up to 5% as compared to planer structure. The FinFET
ensure 37% increment in speed along with 90% of
minimization of leakage current.
Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
(a) Conventional Planar Transistor
Silicon Substrate
(b) 3D Tri-Gate Transistor (FinFET)
Figure 4 Difference between Conventional Planar and 3D
Usage of FinFET allows the transistor designer to operate it
quite faster using equivalent quantity of power. Another aim of
FinFET is to offer superior processing of Integrated Circuits.
The generalized aim of FinFET are stated as following:
To offer highly minimal power consumption in higher
level of integration.
Due to usage of lower cut-off voltage, FinFET is
dependent on only lower operating voltage.
FinFET offers a size upto 20nm as maximum.
90% reduction in static leakage power.
The operating speed of FinFET is 30% faster compared to
other types.
2.2 Tool of FinFET
At present there are various tools which offers digital designing
of FinFET with better accuracy e.g. RC (Resistance
Capacitance) Extraction Tools [10], SPICE Simulation Tools
[11], TCAD Tools [12], and Physical verification tools [13].
The RC (Resistance Capacitance) Extraction Tools is basically
used for investigating the effect of parasitic effects in the form
of resistance and capacitance. One of such product is StarRC
from Synopsys [10]. SPICE is one of the most frequently used
simulation tool in research by various names e.g. HSpice,
FineSim Spice, CustomSim Spice, FastSPICE etc. It possess an
extensive library of transistors and circuitry design. TCAD
tools are basically used for optimization purpose and is used to
study multiple effects by simulation. Physical verification tools
are basically used for validating the industrial design of
FinFET using a ruleset. Such rule sets are used for
authenticating the effectiveness of logic correctness and design
rule checks.
2.3 Performance Parameters
At present, it is found that existing research work towards
FinFET SRAM uses three performance parameters e.g.
Leakage power drainage, Static Noise Margin, and Propagation
Delay. From majority of the study the leakage power
consumption is found within a range of 27-70oC for standard 6
transistors configuration. The static noise margin can be
defined as exact amount of voltage of DC noise in order to
perform flipping operation of respective states of SRAM cells
of specific configurations. The last parameter called as
propagation delay is mainly associated with reading operation
of FinFET and is represented as time that is needed to voltage
difference of specific value (200mV) between BL and BLB.
The next section discusses about the existing techniques where
various design principles for enhancing FinFET SRAM has
been discussed.
This section discusses about the most recently presented
technique for improving the design aspect of FinFET SRAM
operation in research area. The conceptual discussion of FinFET
SRAM has bulk of research papers and there are some survey
papers [14] that has already covered up the discussion of
techniques till 2013. However, none of the existing review
papers has discussed the comparative analysis of existing
techniques with respect to beneficial features and limiting
features of existing techniques. Hence, this section of the paper
will discuss the existing techniques for enhancing the design of
FinFET SRAM published between 2013-2016.
The design aspects of the SRAM could be significantly improve
by focusing on the nanometer area which could be populated
with various alternative devices of Field Effect Transistors i.e.
FET. The recent review performed by Parimaladevi et al. [15]
have discussed about the performance factor of the SRAM and
has theoretically discussed multiple solutions. The study assists
to understand two facts i.e. i) there are better scope of FET in
SRAM for design improvement and ii) the design of FET itself
can be hybridized to attain better objectives. Similar review was
also carried out by Bhattacharya and Jha [16]. Discussion on
design challenges on FinFET was carried out by Burnett et al.
[17]. The most recent study of Zhang et al. [18] [19] have
emphasized on low powered applications with FinFET
technologies of 7/8 nm. The prototype designed by the author
was used to gauge the SRAM with 6 transistors. The study
outcome was evaluated with respect to current and voltage.
Study towards significance of FinFET on the design
improvement was also recently carried out by Lee [20]. The
authors presents elaborated discussion towards bulk FinFET and
compared its performance over with another type of the FinFET
i.e. SOI FinFET. The evaluation was carried out over 14 nm of
node and was tested with respect to current-voltage
charecteristics. The study has also investigated about the trends
of heat dissipation from the 14nm node to find the temperature
reduction capability of 325 K. Study in similar direction was
also carried out by Song et al. [21] most recent in 2016. The
author have introduced the similar design principle with 10nM
of node with FinFET on SRAM with 128 Mb capacity.
Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
Ansari et al. [22] have presented an elaborated study of design
improvement of SRAM cells with 7 transistors. The author has
considered a simulation-based study with HSPICE using
multiple number of transistor (20, 16, 14, 10, 7 nm). The
outcome of the presented simulation study was found to possess
better write speed as well as enhanced stability. The mean static
power was also found to be reduced by approximately 57% with
existing design of 5T SRAM. A trend of using multiple
numbers of transistors involvement was investigated by various
researchers. The work carried out by Dani et al. [23] have
discussed the charecteristics of 6T SRAM design using FinFET
with respect to standby mode, read / write mode, etc. The
simulation study outcome was evaluated with respect to power
and delay mainly for both read / write operation. Similar trend
of study on 6T SRAM was also carried out by Gupta and Roy
[24]. Same year (i.e. 2015), Kushwah and Akashe [25] have
presented a technique of enhancing the stability of noise margin
using SRAM cells with 6 transistors. The study outcome shows
better feasibility of stability enhancement during read operation
and minimizing the voltage reduction and leakage current.
Hence, it can be seen that there are many researchers who
choose to implement in SRAM cells with 6 transistors.
However, usage of 6 transistors cannot be used to accomplish
near-cut-off voltage which is quite important for devices with
restricted energy. This problem was addressed by Park et al.
[26] where a unique buffer for reading operation was introduced
with near cut-off voltage. The outcome shows better write
capability with stabilized device operation. Similar direction of
the study using SRAM cells with 6 transistors and 22 nm
FinFET device was also investigated by Manju and Kumar [27].
The author have considers access time variation between read
and write operation in order to maximize it.
Farkhani et al. [28] have presented a new SRAM design with
cell size of 65nm for incorporating new methods in read / write
operations. The technique uses non-positive voltage for
enhancing the write characteristics of SRAM cells. The
complete design evaluation was done for SRAM cells with 10
transistors. The simulation outcome of the study was found to
possess 82% enhancement to write operation in contrast to
conventional SRAM cells with 8 transistor.
Figure 5. Design of 6T SRAM by Dani et al. [L7]
BLB M10 M12
Figure 6 Design of 6T SRAM by Kushwah [L10]
Shafaei et al. [29] have presented a unique technique to
improving performance of FinFET devices. The authors have
built a 6T and 8T SRAM cells with 7nm of FinFET device. The
overall study objective was to attain the energy efficient cache
memory on FinFET device. Zeinali et al. [30] have presented a
study using SRAM cells of 9 transistors with 14 nm FinFET
device. The study outcome shows minimization of leakage
power by 20% and enhancement of memory access time by
30%. Pal et al. [31] have introduced a double dielectric for
enhancing the electrostatic integrity of FinFET in SRAM. Ghai
et al. [32] have presented a study that compares the multiple
significant parameters for FinFET with respect to analog design.
Kerber et al. [33] have developed a double gated FinFET to
checks its influence due to strained effects of silicon on static
memory. The study outcome shows enhancement in read / write
stability in comparison to unstrained FinFET. Villacorta et al.
[34] have focused on reliability of SRAM using statistical
approach. The summary of above discussion is tabulated below:
Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
Table 1 Summary of Techniques for Design Enhancement of FinFET SRAM
Parimaladevi et al. [15]
Theoretical study of SRAM
Simple description of FET
Doesn‟t specifically highlight
the best solution.
Zhang et al. [18][19]
SRAM with 6T, FinFET
Saving of 20% of cell area
Study lacks benchmarking
Lee [20]
14nm, Bulk & SOI FinFET
325K of temperature reduction
-No Benchmarking
Song et al. [21]
10nm, FinFET SRAM, 128 bit
Better power gain
-No Benchmarking
Ansari et al. [22]
Highly stable, 57% of reduced
power consumption
-No Design optimization
Dani et al. [23] Gupta
and Roy [24], Kushwah
and Akashe [25]
-8.9% of improvement of static
noise margin in 16nm cell
-better delay and energy
-less extensive analysis of
outcomes to prove system
stability on dynamic load.
Park et al. [26], Manju
and Kumar [27]
Buffer with read operation, 6T
SRAM, 22 nm FinFET
Better write ability, stabilized
-Computational Complexity is
not evaluated.
Farkhani et al. [28]
-82% improvement of existing
write operation.
-Supply voltage reduced to 24%.
-33% minimization of leakage
-Less Effective benchmarking
Shafaei et al. [29]
6T, 8T SRAM with 7nm FinFET,
cross layer
-memory efficient memory
-No variability analysis
-outcome validation not done.
Zeinali et al. [30]
9T SRAM, 14 nm FinFET
-30% improvement of existing
read operation.
-20% minimization of leakage
-Less Effective benchmarking
Pal et al. [31]
Double dielectric, 22nn FinFET
-reduction of 56% and 17% of
read & write access time
-Computational Complexity is
not evaluated.
Ghai et al. [32]
Comparison of FinFET parameters
-outcomes applicable in analog
circuit design
-Computational Complexity is
not evaluated.
-No Benchmarking
Kerber et al. [33]
Investigation on Strained Effect on
10-20% enhancement of read-
write stability.
-Computational Complexity is
not evaluated.
-No Benchmarking
Villacorta et al. [34]
Hardening of SRAM FinFET
Enhance critical charge
-Less Effective benchmarking
This section discusses about the research gap of the existing
techniques to improvise the design aspects of SRAM cells and
FinFET technologies.
Less Extent of Novelty: We have observed that studies
pertaining to improve the SRAM cell performance is done
majorly either by changing the number of transistors or by
using various size of FinFET device, which becomes an
impediment towards any future scope of optimization.
Less number of computational Modelling: Majority of the
existing mechanism chooses to use either experimental
approach or by using hardware-based simulation
environment for SRAM and FinFET. Experimental
approaches give highly reliable outcomes but none of the
studies done till date have actually checked for
computational complexity, which makes the approach less
applicable in real-time and big-scale commercial usage.
Hardware-based approach uses a specific simulation
environment which narrows down the scope of
computational capability in this.
Less Studies toward Optimization: There is a need to
develop a computational optimization model in order to
enhance the design performance of SRAM FinFET as
well as to address the problems of fault tolerance too.
There is a need of mathematical optimization principle
supported by probability theory for giving better edge to
the upgradation of design principles of SRAM based
FinFET. There is also a need to focus on the variability
Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
factor which has received less attention till date in this
field except for few number of studies.
Lack of Benchmarked Research Work: Till date, there are
approximately 378 research papers (297 conference and
79 journals) dedicated for SRAM FinFET till date, which
is extremely less in number of research work. Even in this
less extent of work, the existing studies have witness
various differentials in terms of approaches. We have
observed that majority of the outcome of the studies are
not found to be benchmarked with some standards which
makes it quite hard to make out the best approaches or
technique till date.
The topic or problems related to FinFET SRAM is not new as
there are approximately 738 Journals focusing on the problems
related to SRAM published during the year 2010-2016 in IEEE
Xplore and there are approximately 378 Journals focusing on
the problems related to FinFET published during the year
2010-2016 in IEEE Xplore. There are many problems in this
topic, but it is required to choose such a problem, where we
don‟t have much research work. Hence, some unique problem,
which are found to be less addressed in IEEE transaction
papers are: i) Ignorance towards Fault Tolerance: It is
discussed on many papers that gate tunneling and threshold
current during read/write process are highly influenced by
static leakage current in FinFET SRAM. Usage of
computational model of optimization is also less found in
literatures. ii) Vague implication of optimization: Majority of
the existing literatures just perform minor improvement of
performance parameters and claimed it as optimization.
Whereas in real-sense, none of the paper related to FinFET
SRAM is found actually implement optimization modelling.
However, there are few papers e.g. Wang [35], Lu [36], and
Kashfi [37]. A closer look into all the IEEE papers on FinFET
SRAM will show that their approach is like fine-tuning the
technology in order to ensure better customization of transistor
charecteristics. However, none of the techniques implemented
till date in this can be never considered to be sufficient enough
as a transistor will always need to design requirements with
respect to system, circuits, and corresponding application. It
was because; enough computational modelling is missing from
literatures. Moreover, now we have more problems (but
specific) to address i.e. fault tolerance, energy efficiency, and
high level optimization, for which we do not have any
transaction papers to claim so in FinFET SRAM published
between 2010-2016. Therefore, our future direction of the
work will be to develop a computational model for high level
of design optimization of FinFET SRAM. Following are the
objectives to be fulfilled i.e. i) To develop a simple and cost
effective fault-tolerant model that can significantly optimize
stochastically the design performance of FinFET SRAM, ii) To
apply a predictive approach for further optimizing design state
of FinFET SRAM for enhanced throughput, and iii) To further
perform high-level optimization for better stability and energy
effectiveness (dynamic).
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Communications on Applied Electronics (CAE) ISSN : 2394-4714
Foundation of Computer Science FCS, New York, USA
Volume 5 No.6, July 2016
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Girish H
He received his B.E in ECE from Kuvempu University,
Karnataka, India and M Tech from Visveswaraya
Technological University (VTU), Belgaum, India. He is
pursuing PhD in VTU. His area of interest is VLSI. He is
currently working as Associate Professor in Department of
Electronics and Communication, Cambridge Institute of
technology, Bangalore-36, India.
Dr. Shashikumar D R
He received his B.E in ECE from Mysore University (MU),
Karnataka, India & M.E from Bangalore University (BU),
Karnataka, India. He received his PhD degree from Fakir
Mohan (FM) University, Balasore, Orissa. His area of
interest is VLSI, image Processing. He is currently working as
Professor and Head of the Department of Computer Science
Engineering, Cambridge Institute of technology, Bangalore-
36, India. He has published more than 20 International
journals and 20 National journals. Currently, he is guiding 6
PhD scholars.
... Girish and Shashikumar [31] to reduce the computational complexity of an algorithm related to conventional method and performance upgradation of system found in the current times. Girish and Shashikumar [32] focused on FinFET based SRAM cell until today. Mounica [34] have demonstrated the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process methods. ...
... As the proposed system mainly targets for stability control using optimization principle over new design principle of FinFET SRAM; therefore, it is assessed with respect to different forms of performance parameters that are discussed as below. Figure 2 highlights that proposed system offer better retention of the energy in a test 1400 simulation rounds and this is much better than exising approach of Kang et al. [22] and Ebrahimi et al. [32]. The prime reason behind this is approach of Kang et al. [22] includes too many parameters for minimizing Vth; however; it couldn't balance with energy saving. ...
... The prime reason behind this is approach of Kang et al. [22] includes too many parameters for minimizing Vth; however; it couldn't balance with energy saving. Similarly, the approach of Embrahimi et al. [32] includes too much iterative-based approach where complete focus was towards constructing and obtaining data for failure metric. This process consumes maximum energy as well as it also result to higher degree of instability ( Figure 3). ...
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The conventional design principle of the finFET offers various constraints that act as an impediment towards improving ther performance of finFET SRAM. After reviewing existing approaches, it has been found that there are not enough work found to be emphasizing on cost-effective optimization by addressing the stability problems in finFET design.Therefore, the proposed system introduces a novel optimization mechanism considering some essential design attributes e.g. area, thickness of fin, and number of components. The contribution of the proposed technique is to determine the better form of thickness of fin and its related aspect that can act as a solution to minimize various other asscoiated problems in finFET SRAM. Implemented using soft-computational approach, the proposed system exhibits that it offers better energy retention, lower delay, and potential capability to offer higher throughput irrespective of presence of uncertain amount of noise within the component.
... Therefore we get better stability in the voltage due to FINFET. At the same time, memory storage system like SRAM suffers due to high occupancy of cache memory in the chip area as well as it also suffers from maximum energy consumption of the chip power [6]. ...
... Whenever the memory element is to be used for read or write operation, the access transistors must be switched ON. There is a requirement that SRAM cell should provide wider noise margin and high speed but it is a major problem because if we require high speed then the leakage power increases [6]. ...
... This provides us with narrow difference between the cut-off voltage and the supply voltage. Sometimes this narrow difference becomes highly unstable especially when design requires increases in number of transistors with reduced size in order to maintain large storage points [6]. Device design for an SRAM is governed by the stability, power consumption, and access time of an SRAM cell. ...
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CMOS devices are facing many problems because the gate starts losing control over the channel. These problems includes increase in leakage currents, increase of on current, increase in manufacturing cost, large variations in parameters, less reliability and yield, short channel effects etc Since conventional CMOS is used to design SRAM, but it is also facing the problem of high power dissipation and increase in leakage current which affects its performance badly. Memories are required to have short access time, less power dissipation and low leakage current thus FINFET based SRAM cells are recommended over CMOS based SRAM cells. Reducing the leakage aspects of the SRAM cells has been very essential to enhance the stability of the cell. Therefore many low power techniques are used to reduce the power dissipation and leakage currents. These include Multithreshold CMOS (MTCMOS), variable threshold CMOS (VTCMOS), Stacking technique, power gating, Self controllable voltage level (SVL) technique etc. In this paper we propose use of MTCMOS technique to design a FINFET SRAM cell and compare it with FINFET SRAM cell in terms of dynamic power dissipation. All the simulation are done on symica using 14nm technology and predictive technology model (PTM).
... Conventional MOSFET[19]. ...
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Extensive Literature Survey on CMOS, FinFET, CNTFET and TFET based SRAM cells
... The sector norm, as shown in Figure B, which is an SRAM set, for its fast detecting differential and exceptionally tiny region, was seven Transistor (7T) cells (6). Conversely, the full scale of provide electrical energy has affect the efficiency of reading and writing in SRAMs and thus made it complicated for Classical 7T-cell to be achieved [12]. The memory cell is large enough for a powerful inversion machine to function correctly. ...
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Because of the system variations of tiny functional size, enhanced adjustment functions in bits are becoming more and more vital, as technology nodes proceed to scale, primary memory encounter increased energy with output and time impacts such as crosstalk, challenges in consumption and reliability. We suggest a sustainable strategy to error correction in deeply-scale memories in order to tackle increasing failure rates owing to issues. SRAM is frequently used for high-speed memory apps like cache. The SRAM memory layout (SRAM) main parameter is power consumption. SRAM cells are power starving and bad in traditional models. The low-power cell designs for power consumption, delay write and the power retard product has been analyzed in this paper. The most recent upgrade VLSI, primarily in the volatile memory form of the SRAM set built into the PMOS & NMOS series and which is to be included in the cache segment on the CPU and in microcontrollers that are electronically energy-related, and now we have improved the SRAM Array challenges. Keywords: SRAM 6T & 7T CELL, SRAM array 16x16, power and delay of read & write section.
... The existing system on SRAM is presented in (Girish and Shashikumar [9]) is presented and identified certain set of problems of cost optimization that was addressed in most recent implementation (Girish and Shashikumar [10]). This section discusses approaches towards enhancing performance of FinFET/SRAM. ...
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The evolutions in the modern memory units are comeup with FinFET/SRAM which can be utilized over high scaled computing units and in other devices. Some of the recent systems were surveyed through which it is known that existing systems lags with improving the performance and optimization of FinFET/SRAM design. Thus, the paper introduces an optimized model based on Search Optimization mechanism that uses Predictive Approach to optimize the design structure of FinFET/SRAM (PAOD). Using this can achieve significant fault tolerance under dynamic cumpting devices and applications. The model uses mathematical methodology which helps to attain less computational time and significant output even at more simulation iteration. This POAD is cost effective as it provides better convergence of FinFET/SRAM design than recursive design.
... The existing system on SRAM is presented in (Girish and Shashikumar [9]) is presented and identified certain set of problems of cost optimization that was addressed in most recent implementation (Girish and Shashikumar [10]). This section discusses approaches towards enhancing performance of FinFET/SRAM. ...
Full-text available
The evolutions in the modern memory units are comeup with FinFET/SRAM which can be utilized over high scaled computing units and in other devices. Some of the recent systems were surveyed through which it is known that existing systems lags with improving the performance and optimization of FinFET/SRAM design. Thus, the paper introduces an optimized model based on Search Optimization mechanism that uses Predictive Approach to optimize the design structure of FinFET/SRAM (PAOD). Using this can achieve significant fault tolerance under dynamic cumpting devices and applications. The model uses mathematical methodology which helps to attain less computational time and significant output even at more simulation iteration. This POAD is cost effective as it provides better convergence of FinFET/SRAM design than recursive design. Copyright © 2019 Institute of Advanced Engineering and Science. All rights reserved.
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FinFET/SRAM has been contributing to the new evolution of modern-day memory units that are used over broader scale of computing units and other sophisticated devices. A review analysis is performed over existing system to find that existing approaches are more inclined towards improvement in performance parameters and very less towards design optimization. Hence, a novel approach is introduced and is named as Search Optimization based Predictive Approach (SOPA) for optimizing the design structure of FinFET/SRAM so that it can ensure highest degree of fault tolerance when used in broader scale of dynamic applications and modern computing devices. In this, analytical methodology used where the proposed computational model is found to offer reduced computational time and more yield in increasing simulation iteration. The study contributes to progressive convergence of elite design of FinFET/SRAM rather than recursive design and hence cost effective.
Conference Paper
In the area of computational memory management, energy efficiency and proper utilization of memory cell area is being constantly investigated. However, record of research manuscript in this regards are quite less compared to other related research topic in computer science. We reviewed existing techniques of upgrading the performance of FinFET-based SRAM and found that adoption of computational modeling for optimization is quite a few to find. Hence, we model the problem of leakage power minimization as linear optimization problem and develop a technique that ensures better fault tolerance operation of FinFET-based SRAM using enhanced particle swarm optimization. We minimize the computational complexity of the algorithm compared to conventional evolutionary technique and other performance upgrading system found in recent times. Our algorithm has better control over convergence rate, energy dissipation, and capability to ensure fault tolerance.
Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.
This book reviews a range of quantum phenomena in novel nanoscale transistors called FinFETs, including quantized conductance of 1D transport, single electron effect, tunneling transport, etc. The goal is to create a fundamental bridge between quantum FinFET and nanotechnology to stimulate readers' interest in developing new types of semiconductor technology. Although the rapid development of micro-nano fabrication is driving the MOSFET downscaling trend that is evolving from planar channel to nonplanar FinFET, silicon-based CMOS technology is expected to face fundamental limits in the near future. Therefore, new types of nanoscale devices are being investigated aggressively to take advantage of the quantum effect in carrier transport. The quantum confinement effect of FinFET at room temperatures was reported following the breakthrough to sub-10nm scale technology in silicon nanowires. With chapters written by leading scientists throughout the world, Toward Quantum FinFET provides a comprehensive introduction to the field as well as a platform for knowledge sharing and dissemination of the latest advances. As a roadmap to guide further research in an area of increasing importance for the future development of materials science, nanofabrication technology, and nano-electronic devices, the book can be recommended for Physics, Electrical Engineering, and Materials Science departments, and as a reference on micro-nano electronic science and device design. • Offers comprehensive coverage of novel nanoscale transistors with quantum confinement effect • Provides the keys to understanding the emerging area of the quantum FinFET • Written by leading experts in each research area • Describes a key enabling technology for research and development of nanofabrication and nanoelectronic devices
This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reader with a deep understanding of the major random variation sources, and the characterization of each random variation source. Furthermore, the book presents various CMOS device designs to surmount the random variation in future CMOS technology, emphasizing the applications to SRAM.
The read-write ability of SRAM cells is one of the major concern in nanometer regime. This paper analyzes the stability and performance of asymmetric FinFET based different schematic of 6T SRAM cells. The proposed structure exploits asymmetrical behavior of current to improve read-write stability of SRAM. By exploiting the asymmetricity in proposed structure, contradiction between read and write noise margin (RNM and WNM) is relaxed. The overall improvements in static, read and write noise margins for proposed asymmetric FinFET based independent gate SRAM (IGSRAM) are 28%, 71%, and 31% respectively.
In contrast to conventional 2-D MOSFETs, FinFETs are able to be scaled down to 20 nm and beyond, and have superior performance. There are two types of FinFETs:SOI FinFETs and bulk FinFETs. Bulk FinFETs are built on bulk-Si wafers, which have less defect density and are cheaper than SOI wafers, while also having better heat transfer rate to the substrate compared to SOI FinFETs. In 2011, Intel announced the world’s first 3-D transistors in the mass production of a 22 nm microprocessor (code-named Ivy Bridge). The 3-D transistors adopted by Intel are actually bulk FinFETs. In this chapter, we provide the design guidelines for bulk FinFETs at the 14 nm node, and compare bulk and SOI FinFETs in terms of scalability, parasitic capacitance, and heat dissipation. Decrease of the drain current by parasitic resistance in the source (S) and drain (D) regions is also addressed. Drain current fluctuation by single charge trap is studied in terms of the trap depth, trap position, and percolation path. In the design of 14 nm bulk FinFETs, a punch-through stopper at a position just under the S/D junction depth is required to suppress unwanted cross-talk between S and D. The peak concentration of the stopper needs to be 2–3 × 1018 cm−3. The S/D junction depth should be equal or slightly smaller than the height of fin body, defined from the surface of the isolation oxide region to the top of the fin body. Considering the short channel effect and drain current drivability, the reasonable doping concentration of uniformly doped fin body is 2–3 × 1017 cm−3. To keep the drain-induced barrier below 100 mV/V when the length between the S and D junctions is the same as the gate length (14 nm), the width of the fin body should be ~9 nm. Under the same doping concentration and geometry, both 14 nm SOI and bulk FinFETs have nearly the same I–V characteristics, which mean nearly the same scalability. Since thin fin bodies protruding from the substrate are easily depleted, the junction capacitance of the S/D to fin body can be reduced to similar or even lower values than that of SOI FinFETs. To achieve a similar heat transfer rate to the substrate as bulk FinFETs, the buried oxide in SOI FinFETs should be thinned down to 20 nm or beyond, which could cause unwanted increase in the parasitic capacitance. The contact area between the metal electrode and the S/D region should be as wide as possible to reduce the S/D parasitic resistance.
The benefits of a super-steep retrograde (SSR) fin doping profile, which can be achieved using the oxygen insertion technology, are quantified via 3-D technology computer-aided design simulations for the 7/8-nm bulk-Si FinFET technology targeting low-power applications. A calibrated compact model is then used to estimate the six-transistor static RAM cell performance and yield. The SSR FinFET technology is projected to provide for up to 100 mV reduction in minimum cell supply voltage, to facilitate voltage scaling to below 0.50 V.
Design technology to address the new and vast problem of heterogeneous embedded systems design while remaining compatible with standard "More Moore" flows, i.e. capable of simultaneously handling both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today and will be for several years to come. While the micro-electronics industry, over the years and with its spectacular and unique evolution, has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction levels, the emergence of device heterogeneity requires new approaches enabling the satisfactory design of physically heterogeneous embedded systems for the widespread deployment of such systems. Heterogeneous Embedded Systems, compiled largely from a set of contributions from participants of past editions of the Winter School on Heterogeneous Embedded Systems Design Technology (FETCH), proposes a necessarily broad and holistic overview of design techniques used to tackle the various facets of heterogeneity in terms of technology and opportunities at the physical level, signal representations and different abstraction levels, architectures and components based on hardware and software, in all the main phases of design (modeling, validation with multiple models of computation, synthesis and optimization). It concentrates on the specific issues at the interfaces, and is divided into two main parts. The first part examines mainly theoretical issues and focuses on the modeling, validation and design techniques themselves. The second part illustrates the use of these methods in various design contexts at the forefront of new technology and architectural developments. © 2012 Springer Science+Business Media B.V. All rights reserved.
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via connections now and remote links later.
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.