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Non-volatile D-latch for sequential logic circuits using memristors
Abstract
This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.
... The advancement of CMOS-compatible ReRAMs has promoted the development of NVMs, which incorporates ReRAMs into CMOS circuits, such as latches, flip-flops, and SRAMs, to provide the NV property. There are many ReRAM-based NVMs, such as Non-Volatile D-Latch (NVDL) [12], Radiation-hardened hybrid RRAM-based Non-volatile Latch (RHRNL) [13], Low Store Energy and Robust Non-Volatile Flip-Flop (LSER-NVFF) [14], Non-Volatile 8T2R SRAM (NV8T2R SRAM) [15], and Non-Volatile 7T1R SRAM (NV7T1R SRAM) [16]. However, to the best of our knowledge, there are few latch structures composed of a CMOS logic part along with few ReRAMs to simultaneously provide radiation-hardening and NV capability. ...
In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.
... Pure memristive-designs for D and T flip-flops that have been reported earlier utilized IMPLY logic [6,7]. Hybrid designs for the flip-flops are reported in [16][17][18] that need both CMOS and memristor for design purpose. But the hybrid designs thus provided are not compatible with crossbar-based pure memristive-memories [2,3]. ...
‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates
the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of
performance and energy-efficiency. ‘Memristors’ are considered as potential devices for building such memories,
as they are highly dense, non-volatile scalable devices with faster switching times and lower energy dissipation
and are also compatible with the existing CMOS-technology. Additionally, memristors fit in crossbar structure and
can perform logic-computations, when different voltages are applied across them. Previously, various synthesis
works have been reported for logic realization using memristors. But logic blocks, implemented using synthesis
tools, are not always completely optimized. In this context, we present the alternative memristive-designs for the
two most commonly used digital units—Delay (D) and Toggle (T) flip-flops. The proposed designs are based on
Memristor Aided loGIC (MAGIC) design style and are specific to crossbar-based pure memristive-memories. A
relevant simulation methodology is presented for simulating the proposed MAGIC-designs of D and T flip-flops in
Cadence Virtuoso. Comparison with the existing designs of D, T flip-flops (using IMPLY) revealed that both the
proposed D, T flip-flops are more performance-efficient (by 28.571%, 20% respectively) and more energy-efficient
(by 83.873%, 82.905% respectively) than their corresponding IMPLY-peers. Also, the proposed D, T flip-flops are
found to use reduced crossbar areas (by 46.667%, 45% respectively) relative to their counterparts generated using
a recent synthesis technique, which makes the designs suitable for massive parallel executions inside memristive-memories
of any size.
... To overcome the volatility of CMOS-based D-latch and to improve power consumption, a non-volatile memristive D-latch (NVDL) was proposed and published [213]. The NVDL also benefits against CMOS sequential logic circuits with the addition of non-volatile memory storage. ...
This dissertation reports the research work that was conducted to propose a non-volatile architecture for FPGA using resistive switching devices. This is achieved by designing a Configurable Memristive Logic Block (CMLB). The CMLB comprises of memristive logic cells (MLC) interconnected to each other using memristive switch matrices. In the MLC, novel memristive D flip-flop (MDFF), 6-bit non-volatile look-up table (NVLUT), and CMOS-based multiplexers are used. Other than the MDFF, a non-volatile D-latch (NVDL) was also designed. The MDFF and the NVDL are proposed to replace CMOS-based D flip-flops and D-latches to improve energy consumption. The CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the MDFF provides switching speed of 1.08 times faster; the NVLUT reduces power consumption by 6.25nW and improves device area by 128 transistors; while the memristive logic cells reduce overall device area by 60.416μm2. The NVLUT is constructed using novel 2TG1M memory cells, which has the fastest switching times of 12.14ns, compared to other similar memristive memory cells. This is due to the usage of transmission gates which improves voltage transfer from input to the memristor. The novel 2TG1M memory cell also has lower energy consumption than the CMOS-based 6T SRAM cell. The memristive-based switch matrices that interconnects the MLCs together comprises of novel 7T1M SRAM cells, which has the lowest energy-delay-area-product value of 1.61 among other memristive SRAM cells. Two memristive logic gates (MLG) were also designed (OR and AND), that introduces non-volatility into conventional logic gates. All the above circuits and design simulations were performed on an enhanced SPICE memristor model, which was improved from a previously published memristor model. The previously published memristor model was fault to not be in good agreement with memristor theory and the physical model of memristors. Therefore, the enhanced SPICE memristor model provides a memristor model which is in good agreement with the memristor theory and the physical model of memristors, which is used throughout this research work.
... The complementary inverter will then output V DD and logic information is restored in the slave. A memristive D-latch was presented in [28] that consists of 13 transistors and 2 memristors. The average output delay of the MDFF is 0.195 ns while the output delay of the memristive D-latch is 0.15 ns, giving an average of 0.173 ns of path delay for memristive sequential circuits, between memristive D-latch and D flip-flop. ...
This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25nW, and the memristive logic cells reduce device area by 60.416μm². In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.
With the rapid emergence of silicon scaling limitations and ongoing challenges such as the Von Neumann bottleneck, the need for alternative computing paradigms is increasingly essential. One of the most promising solutions is in-memory computation, enabled by memristive technology. In this work, we propose a Hybrid CMOS-Memristor (HCM) non-volatile D latch that capitalizes on the unique resistive switching properties of memristors to achieve enhanced digital circuit performance with fewer components. Functional correctness is validated through PVT analysis and Monte Carlo simulations, ensuring robust functionality across various operating conditions. The results demonstrate that the proposed design outperform other memristor based latches, offering faster switching times, reduced delay and area, and a wider threshold voltage range. Additionally, the design is extended to implement a D Flip-Flop (DFF) and a Pseudo-Random Number Generator (PRNG). These features make the proposed designs particularly suitable for unstable power environments, where reliability and efficiency are critical. Overall, the advancements presented in this work contribute to the development of efficient and scalable digital circuits, demonstrating significant potential for real-world applications.
In this study, the D-type latch devices with Ceramic Flat Package (CFP) and Shrink Small-Outline Package (SSOP) were tested and analyzed by experimental means. The effects of manufacturing technics on the pin structure, wire bond, chip layout design, die attach and temperature-affected electrical performance were subsequently investigated. Results show that manufacturing technics with CFP package possesses thicker special pin coatings, thicker different wire bond, stable and effective die attach compared with SSOP package. Meanwhile, the bare dies of two devices exhibit same layout structure design but different longitudinal dimensions. The temperature-affected electrical performances including voltage, current and propagation delay time reveal that the temperature sensitive parameters of CFP latch (variation about 1%) display 12 times better stability than that of SSOP latch (distinct variation about 12%) from −55 °C to 125 °C. Meanwhile, the SSOP latch displays 41.8% better switching speed and working frequency than CFP latch with similar other electrical parameters at room temperature.
In this paper, an improved memristor SPICE model of [1] is presented by incorporating dynamic ground feature. Thus the proposed model enables the memristor to admit bidirectional current flow regardless of the manner it is connected to its voltage source and behaves similar to the electrical characteristics of the physical memristor. The simulation results of the proposed memristor model shows that they are in close agreement with experimental results.
This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore, it addresses the prevalent problems associated with nano crossbars, such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns, while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition, the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations.
We present resistive switching model for TaOx memristors, which demonstrates that the radius of a tantalum rich conducting filament is the state variable controlling resistance. The model tracks the flux of individual oxygen ions and permits the derivation and solving of dynamical and static state equations. Model predictions for ON/OFF switching were tested experimentally with TaOx devices and shown to be in close quantitative agreement, including the experimentally observed transition from linear to non-linear conduction between RON and ROFF. This work presents a quantitative model of state variable dynamics in TaOx memristors, with direct comparison to high-speed resistive switching data.
This study examined the effects of electrical forming methods on the bipolar resistance switching (BRS) behavior in Pt/TiO2/Pt sandwich structures. The BRS is confined to a region near the ruptured end of conducting nanofilaments, which are composed of a TinO2n − 1 Magnéli phase formed by electroforming. The intermediate phase with an oxygen vacancy concentration between the insulating TiO2 and the residual conducting filament that formed at the interface region was considered to be the switching layer (SL). The change in filament shape caused by a variation in the compliance current during filament formation resulted in a different filament rupture location and SL configuration. Precise control of the filament formation and rupture process resulted in SLs connected in an anti-parallel configuration. It was possible to reconfigure the SLs in the same fashion without any restraints, which allowed an unlimited memristive operation to be achieved. This paper presents a new technique in voltage sweep mode that applies a compliance current as a tool to achieve a memristor with unlimited operation.
Memristive devices are promising components for nanoelectronics with applications in nonvolatile memory and storage, defect-tolerant circuitry, and neuromorphic computing. Bipolar resistive switches based on metal oxides such as Ti O 2 have been identified as memristive devices primarily based on the “pinched hysteresis loop” that is observed in their current-voltage (i-v) characteristics. Here we show that the mathematical definition of a memristive device provides the framework for understanding the physical processes involved in bipolar switching and also yields formulas that can be used to compute and predict important electrical and dynamical properties of the device. We applied an electrical characterization and state-evolution procedure in order to capture the switching dynamics of a device and correlate the response with models for the drift diffusion of ionized dopants (vacancies) in the oxide film. The analysis revealed a notable property of nonlinear memristors: the energy required to switch a metal-oxide device decreases exponentially with increasing applied current.
Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things (IoT) deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory (DRAM) with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops (NVFFs) seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.
This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.
The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2^n×n (n×2^n) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.
Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.
In this paper, two new zero-sleep-leakage flip-flop (F-F) circuits are proposed to make the sleep leakage literally zero. At the sleep-in time, the F-F's data are transferred to memristor retention latch; thus, the F-F can be completely cutoff from the external power supply saving the energy leak during the sleep time. The conditional storing circuit in the F-F (type-2) can reduce switching power by 87% in storing the data than the F-F (type-1). And, the crossover time of the F-F (type-2) is shortened by 97% than the F-F (type-1).
We investigate the exponential dependence of switching speeds in thin-film memristors for high electric fields and elevated
temperatures. An existing nonlinear ionic drift model and our simulation results explain the very large ratios for the state
lifetime to switching speed experimentally observed in devices for which resistance switching is due to ion migration. Given
the activation barriers of the drifting species, it is possible to predict the volatility and switching time for various material
systems.
In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device.
Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.
Restoration of logic information in the NVDL circuit. (a) VDD supply to the circuit. (b) Output Q when restoring logic '0'. (c) Output Q when restoring logic '1
- Fig
Fig. 8. Restoration of logic information in the NVDL circuit. (a) VDD
supply to the circuit. (b) Output Q when restoring logic '0'. (c) Output Q
when restoring logic '1'.
Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications
Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory
(Memristor) Devices for Low Power Mobile Applications," IEEE J.
Solid-State Circuits, vol. 47, no. 6, pp. 1483-1496, 2012.
Enhanced SPICE Memristor Model with Dynamic Ground
- P W C Ho
- F O Hatem
- H A F Almurib
- T N Kumar
P. W. C. Ho, F. O. Hatem, H. A. F. Almurib, and T. N. Kumar,
"Enhanced SPICE Memristor Model with Dynamic Ground," in IEEE
International Circuits and Systems Symposium, 2015.