Avalanche Robustness of SiC MPS Diodes

Abstract

Silicon carbide merged pin-Schottky (MPS) diodes are predestined to withstand high avalanche energies due to deep implanted p+-regions within the active area of the device. This paper shows unclamped-inductive-switching (UIS) measurements at state-of-the-art 650V and 1200V diodes of MPS type at different conditions, e.g. at Infineon’s G5 SiC Schottky diodes. The dependency of the avalanche energy versus the applied inductance is studied in detail and the minimum of this characteristic is explained. Robust and weak diode designs are compared. Repetitive avalanche tests at challenging conditions show the robustness of the used MPS design. First studies at SiC MOSFETs show also a comparatively high avalanche capability.

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Avalanche Robustness of SiC MPS Diodes
Thomas Basler, Infineon Technologies AG, Germany, thomas.basler@infineon.com
Roland Rupp, Infineon Technologies AG, Germany, roland.rupp@infineon.com
Rolf Gerlach, Infineon Technologies AG, Germany, rolf.gerlach@infineon.com
Bernd Zippelius, Infineon Technologies AG, Germany, bernd.zippelius@infineon.com
Mihai Draghici, Infineon Technologies Austria AG, Villach, mihai.draghici@infineon.com
Abstract
Silicon carbide merged pin-Schottky (MPS) diodes are predestined to withstand high
avalanche energies due to deep implanted p+-regions within the active area of the device.
This paper shows unclamped-inductive-switching (UIS) measurements at state-of-the-art
650 V and 1200 V diodes of MPS type at different conditions, e.g. at Infineon’s G5 SiC
Schottky diodes. The dependency of the avalanche energy versus the applied inductance is
studied in detail and the minimum of this characteristic is explained. Robust and weak diode
designs are compared. Repetitive avalanche tests at challenging conditions show the
robustness of the used MPS design. First studies at SiC MOSFETs show also a
comparatively high avalanche capability.
1 Introduction
Driven by the target of lower VF values, the base doping of a SiC Schottky diode has to be
increased. This leads directly to higher electric field strengths at the Schottky barrier and thus
to higher leakage currents. To overcome this drawback, the MPS design uses implanted
p+-regions to reduce the electric field at the Schottky barrier [1,2,3], see Fig. 1 a). For
instance, the 5th generation of Infineon’s SiC diodes use hexagonal p+-regions to obtain an
effective and homogenous shielding, as shown in Fig. 1 b).
a) b)
Fig. 1: a) Schematic cross section of an MPS diode structure, showing the onset points of impact
ionization, dashed arrows show the current flow at high currents; b) Hexagonal cell structure of
Infineon’s 5th generation SiC diode with MPS design, black – Schottky area

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Enabled by this structure, the avalanche breakdown occurs typically in the cell field of such
devices below the p+-regions. This is the base for achieving a good and stable avalanche
behavior. Additional to that, the junction termination design must be chosen well to avoid
early breakdown and a good ohmic contact to the p+-regions is necessary for low on-state
losses and a high surge-current ruggedness, see also [4,5,6]. The following investigations
and measurements were performed on Infineon’s latest MPS generation of 650 V and 1200 V
SiC Schottky diodes. With the help of a robust avalanche capability, the diodes are self-
protected against overvoltages or they may be used for protecting the typically non-
avalanche rugged IGBTs. Also the reduction of voltage safety margin of power devices may
be possible, e.g. to use a 900 V class device for a 600 V DC-link voltage in a two-level
topology.
2 Unclamped-Inductive-Switching Behavior
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To prove the good avalanche ruggedness of the MPS concept, UIS tests were performed.
For that, the test diodes were connected in parallel to a 1700 V IGBT, see Fig. 2 a). When the
IGBT turns off a pre-adjusted current, an overvoltage is induced across the switch and the
diode runs into avalanche breakdown. A classical UIS test is typically performed at only 50 V
DC voltage which is far away from practice. Therefore, UIS tests with DC voltages up to
800 V (for 1200 V diodes) were performed. Due to the low intrinsic carrier density of SiC, the
tested diodes are predestined to block a high voltage after the UIS pulse.
a)
b)
Fig. 2: a) Test circuit with optional parallel resistor R to damp LC oscillations; b) Schematic current and
voltage waveforms during UIS test, dissipated energy during UIS pulse: !"# $%
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For showing the energy variation versus the applied inductance the measurements where
carried out between L=9 µH and L=10.7 mH. This changes the turn-off current and the
clamping time tP. Furthermore, repetitive avalanche tests with lower EAV were performed, too.
Fig. 3 shows a first representative waveform of an 8 A rated 1200 V diode. During the last
pulse before destruction EAV,max=6.8 J/cm2 was dissipated. With the help of the voltage
waveform, the maximum junction temperature during clamping is estimated with Tj,max=230 °C
in Fig. 3 b), assuming a homogenous temperature and current distribution. For this
estimation, the temperature dependency of the breakdown voltage of this diode was
measured in advance on a heat plate at Ir=30 mA with 0.33 V/K. However, the 230 °C cannot
explain directly destruction. Current inhomogeneities and the anisotropy of impact ionization
which is known for SiC devices (see e.g. [7]) are supposed to be the root cause for
destruction.

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a) b)
Fig. 3: a) Last UIS pulse of an 8 A rated 1200 V SiC MPS diode before destruction with
EAV,max=6.8 J/cm2 at L=3.8 mH, VDC=50 V, T=25 °C; b) Temperature estimation derived from the
measured voltage waveform from Fig. 3 a), VBR=f(T) was measured in advance on a heat plate with
approx. 0.33 V/K.
3 Results from Diode Measurements
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In a first step, different junction termination designs are compared. In Fig. 4 the failure
patterns of a 20 A and 8 A rated 1200 V MPS diode are shown. The 20 A diode was destroyed
directly at the beginning of an UIS clamping pulse and was not able to clamp any
overvoltage. The early breakdown failure point could be found at the transition from active
area to junction termination. In contrast to that, the 8 A diode was destroyed only after
dissipating a larger amount of energy. The failure spot is randomly distributed within the
active area which indicates a more robust design. The diodes have the same cell structure in
the active area, only the junction termination has a different design.
a)
b)
c)
Fig. 4: a) Early breakdown failure pattern of a 20 A/1200 V diode with an insufficient junction
termination design; b) Failure pattern of a robust junction termination of an 8 A/1200 A diode after
dissipating 6.9 J/cm2 of energy; c) TCAD (Technology Computer Aided Design with Sentaurus Device)
simulation results: breakdown voltage of cell field compared to breakdown voltage of p--JTE, picture
taken from [1]
Tj,max≈230°C!

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In [1], TCAD simulations showed for a p--JTE (junction termination extension) that a specific
dose windows must be selected to pin the breakdown point within the active area, see
Fig. 4 c). If not, early breakdown occurs as happened for the diode in Fig. 4 a).
In a next step, diodes of a lower voltage class, namely 6 A/650 V devices with robust junction
termination, were measured. Fig. 5 shows the last pulse before destruction. At room
temperature an EAV,max of approx. 3.7J/cm2 could be achieved. At a junction temperature of
175 °C EAV,max is reduced by 40 % and the initial breakdown voltage value VBR,start is slightly
higher, see Fig. 5 b). The failure spot was found within the active area.
a)
b)
Fig. 5: UIS waveforms of 6 A/650 V MPS diode class, L=3540 µH, VDC=50 V; a) At room temperature,
EAV,max=3.7 J/cm2; b) At 175 °C, EAV,max=2.2 J/cm2
To make the clamping condition even more challenging, the 8 A/1200 V diode used in Fig. 3
was directly stressed with 800 V DC voltage after the clamping pulse, see Fig. 6. This would
be a more practical condition.
Fig. 6: UIS waveforms of 8 A/1200 V MPS diode class, L=3044 µH, VDC=800 V, Tj,start=25 °C,
EAV=4.6 J/cm2
VBR,start!

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The diode showed no earlier destruction and could withstand approx. the same max.
clamping energies as in Fig. 3. As stated above, the temperature rise during UIS is not high
enough to raise the intrinsic-carrier density ni to regions where the leakage current levels will
lead to thermal runaway. And this even though the saturation-current term js is dependent on
ni² as given in the overall leakage current density jr of a pn-junction (Schottky contact
contribution neglected):
,-.$ -/0 -123 $ 4 ' 56
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(80 9:
0 56';123
<123
=
,,,,
(1)
with q – elementary charge, Dp – diffusion constant of holes, Lp – diffusion length of holes,
ND – base doping, wSCR – space-charge region, <SCR – lifetime in the space charge region.
For a deeper investigation, the EAV=f(L) characteristic is used, see Fig. 7. In this Figure a
minimum in EAV,max can be found for an 8 A/1200 V diode in a TO-220 housing at L=400 µH.
Beside the burn mark in the active area, the failure picture shows strong molten anode
metallization even the hexagonal cell structure has become visible, see Fig. 7 b). For higher
inductances, EAV,max rises due to longer clamp pulse length, also shown in [3]. More and
more energy can already be transferred to adjacent layers (solder layer, leadframe, etc.). For
very low inductances EAV,max rises, too. The energy is only stored in the SiC semiconductor
portion and cannot damage the anode metallization significantly which corresponds to the
failure pattern in Fig. 7 b) at 9 µH. This principle behavior holds also for other voltage/current
classes and is directly linked to the Zth characteristic.
a)
Fig. 7: a) Last-pass avalanche energy and turned-off current versus applied inductance (VDC=50 V,
8 A/1200 V diode, T=25 °C); b) Chip failure pattern at different inductances, EAV,max and turned-off
current
4 Stability Tests
To proof the overall stability during avalanche condition each 10.000 clamping pulses were
performed at EAV=2.85 J/cm2 at different conditions. The leakage current, breakdown voltage
and forward voltage drop were tested initially and after 10.000 pulses. Even at very
challenging conditions of 144 A at the breakdown branch (=Ioff) for an 8 A rated diode no
degradation could be observed, see Table 1. The shielding by the p+-regions is obviously
sufficiently dimensioned.
9µH!
30mH!
400µH!
hexagonal cell
structure visible
b)

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Table 1: Static characterization of an 8 A/1200 V SiC MPS diode before and after 10.000 avalanche
pulses at different conditions. No significant change in values was observed.
2.85 J/cm2,
10k pulses
tp=12.3 µs
Ioff=10.7 A
tp=3.4 µs
Ioff=38 A
tp=0.92 µs
Ioff=144 A
initial
end
initial
end
initial
end
IR@1.2 kV [µA]
1.40
1.39
1.26
1.21
1.35
1.36
VF@8 A [V]
1.46
1.46
1.49
1.48
1.47
1.47
VF@80 A [V]
7.05
7.06
7.26
7.28
7.11
7.12
At the beginning it was mentioned that an avalanche-rugged MPS diode may be used to
protect a non-avalanche rugged switch in circuits with higher parasitic inductance. In that
case, the parallel diode has to clamp a certain amount of energy with switching frequency
(e.g. in an inverter for high load-current cases). To test this, an 8 A/1200 V diode was tested
under repetitive UIS configuration with a switching frequency of 4 kHz at 800 V VDC. The test
was continued until thermal equilibrium, see Fig. 8. During every single UIS pulse an energy
of 28 mJ/cm2 was dissipated. Also here, the MPS diode showed a very rugged behavior
without destruction. However, the protection feature will lead to higher overall switching
losses and should only be used at high- and over-load conditions.
Fig. 8: Repetitive UIS test of an 8 A/1200 V MPS diode with a frequency of 4 kHz, EAV=28 mJ/cm2,
VDC=800 V, L=3 mH.
5 UIS Behavior of 1200V SiC MOSFET
Due to the deep implanted p+-regions the MPS design can be used as reference for other
technologies like the SiC MOSFET (DMOS, Trench). Fig. 9 shows the same good avalanche
capability of a 40 mΩ/1200 V Infineon MOSFET as for the actual SiC MPS diode. An even
higher EAV,max of 9.7 J/cm² was found. Enabled by this, first 1200 V power switches with an
assured avalanche capability may become available.
However, in future work the MOS-gate stability must be proven especially for repetitive
avalanche condition since the critical field strength is 10 times higher for SiC compared to
silicon. Gate-oxide degradation must be prevented.

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a)
b)
Fig. 9: UIS waveform of a 1200 V Infineon SiC MOSFET at VDC=50 V, L=3.5 mH, T=25 °C; a) Last
pulse before destruction with EAV,max=9.7 J/cm2; b) Destruction pulse, fail during UIS pulse
6 Conclusion
The above measurements show that state-of-the-art SiC MPS diodes of 650 V and 1200 V
voltage class can have a rugged and high avalanche capability. Table 2 summarizes the
achievable avalanche energies at T=25 °C and L≈3 mH. A device with a thicker drift zone
seems to be more robust. First investigations at SiC MOSFETs indicate a potential towards
even higher avalanche capability.
Table 2: Comparison of avalanche energies between different technologies but same overall chip
thickness.
The SiC MOSFET shows the highest possible energy per area. Presumably, the point of the
maximum field strength is shifted deeper into the device which may help to distribute the
dissipated energy better within the semiconductor volume.
However, to achieve a high avalanche capability in general the junction termination design
must be chosen well and a sufficient shielding mechanism has to be applied to protect e.g.
Schottky contacts or MOS structures.
Enabled by a high avalanche capability, a higher level of power-electronic system protection
will be reached. Internal and external overvoltages can be clamped and switched off.
650 V
SiC MPS diode
1200 V
SiC MPS diode
1200 V
SiC MOSFET
EAV,max @ ≈3mH
3.7 J/cm²
5 J/cm²
9.7 J/cm²

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References
[1] Rupp et al. Avalanche Behaviour and its Temperature Dependence of Commercial SiC MPS
Diodes: Influence of Design and Voltage Class. 26th International Symposium on Power
Semiconductor Devices & IC's (ISPSD 2014), 2014
[2] M. Treu et al. A surge current stable and avalanche rugged SiC merged pn Schottky diode blocking
600V especially suited for PFC applications. Materials Science Forum vol. 527-529: 1155-1158,
2006
[3] Konstantinov, S. Jinman, S. Young, F. Allerstam and T. Neyer. Silicon Carbide Schottky-Barrier
Diode Rectifiers with high Avalanche Robustness. International Exhibition and Conference for
Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2015),
2015
[4] S. Fichtner, S. Frankeser, R. Rupp, R. Gerlach, T. Basler and J. Lutz. Ruggedness of 1200V SiC
MPS diodes. Proceedings of the 26th European Symposium on Reliability of Electron Devices,
Failure Physics and Analysis (ESREF 2015), Microelectronics Reliability. vol. 55. issues 9-10, pp.
1677-1681, 2015
[5] S. Fichtner, J. Lutz, T. Basler, R. Rupp, R. Gerlach. Electro-Thermal Simulations and Experimental
Results on the Surge Current Capability of 1200 V SiC MPS Diodes. 8th International Conference
on Integrated Power Electronics Systems (CIPS 2014), Nuremberg, VDE Verlag Berlin, Offenbach,
S. 438 – 443, 2014
[6] O. Harmon, T. Basler and Fanny Björk. Advantages of the 1200V SiC Schottky Diode with MPS
Design. In Bodo’s Power Systems, December issue, ISSN: 1863-5598, 2015
[7] T. Hatakeyama. Measurements of impact ionization coefficients of electrons and holes in 4H-SiC
and their application to device simulation. In Phys. Status Solidi A, 206: 2284–2294.
doi: 10.1002/pssa.200925213, 2009