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To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This article presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap, and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches, Fast Median approach, LP approach, and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

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... Geometric structures such as the Voronoi diagram [29,30] and the Delaunay triangulation [5] partition the underlying space into regions based on proximity. There are various applications in chip manufacturing [19], geoinformatics [23], and pattern recognition [1,27]. ...

We investigate the problem of partitioning a rectilinear polygon $P$ with $n$ vertices and no holes % with no holes into rectangles using disjoint line segments drawn inside $P$ under two optimality criteria. In the minimum ink partition, the total length of the line segments drawn inside $P$ is minimized. We present an $O(n^3)$-time algorithm using $O(n^2)$ space that returns a minimum ink partition of $P$. In the thick partition, the minimum side length over all resulting rectangles is maximized. We present an $O(n^3 \log^2{n})$-time algorithm using $O(n^3)$ space that returns a thick partition using line segments incident to vertices of $P$, and an $O(n^6 \log^2{n})$-time algorithm using $O(n^6)$ space that returns a thick partition using line segments incident to the boundary of $P$. We also show that if the input rectilinear polygon has holes, the corresponding decision problem for the thick partition problem using line segments incident to vertices of the polygon is NP-complete. We also present an $O(m^3)$-time $3$-approximation algorithm for the minimum ink partition for a rectangle containing $m$ point holes.

The rectangular partitioning of a digital object, A (without holes) is presented here. The partitioning is obtained in such a way that the set of connected output rectangles are related to the straight skeleton of the corresponding digital object. The given digital object, A is imposed on background grid of size, g (say) and its inner isothetic cover, P is obtained which is the maximum area orthogonal polygon inside the digital object. The combinatorial rules are formulated to apply those on P to partition it into a set of rectangles such that it is related to the straight skeleton of P. The partitioning algorithm discussed here runs in where n being the number of pixels on the periphery of digital object and g being the grid size. The experimental result shows the efficiency of the algorithm.

We investigate the problem of partitioning a rectilinear polygon P with n vertices and no holes into rectangles using disjoint line segments drawn inside P under two optimality criteria. In the minimum ink partition, the total length of the line segments drawn inside P is minimized. We present an O(n3)-time algorithm using O(n2) space that returns a minimum ink partition of P. In the thick partition, the minimum side length over all resulting rectangles is maximized. We present an O(n3log2n)-time algorithm using O(n3) space that returns a thick partition using line segments incident to vertices of P, and an O(n6log2n)-time algorithm using O(n6) space that returns a thick partition using line segments incident to the boundary of P. We also show that if the input rectilinear polygon has holes, the corresponding decision problem for the thick partition problem using line segments incident to vertices of the polygon is NP-complete. We also present an O(m3)-time 3-approximation algorithm for the minimum ink partition for a rectangle containing m point holes.

Performing chemical mechanical polishing (CMP) modeling for physical verification on an integrated circuit (IC) chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC’s layout based on physical principles and empirical experiments, which is computationally costly and time-consuming. In this work, we propose a CmpCNN framework based on convolutional neural networks (CNNs) with a transfer learning method to accelerate the CMP modeling process. It utilizes a multi-input strategy by feeding the binary image of layout and its density into our CNN-based model to extract features more efficiently. The transfer learning method is adopted to different CMP process parameters and different categories of circuits to further improve its prediction accuracy and convergence speed. Experimental results show that our CmpCNN framework achieves a competitive root mean square error ( RMSE ) of 2.7733Å with 1.89 × reduction compared to the prior work, and a 57 × speedup compared to the commercial CMP simulation tool.

To enhance yield of fabricated chips, foundries normally insert dummy features to tape-out-ready layouts in order to improve pattern density uniformity. This process may unfortunately degrade the performance of analog/RF and high-speed digital integrated circuits. In this paper, we investigate the ways how to control pattern density distribution on different layers in analog layouts during the process of layout migration from an old technology to a new one or for design specification update in the same technology. We develop a new set of schemes for smartly modifying layout elements to improve pattern density uniformity besides the traditional dummy-insertion operation. The experimental results show that our proposed approach can account for up to 80% improvement towards the ideal density uniformity in the regular analog layouts. This promising option can significantly decrease the coupling-capacitance-induced parasitic effects due to the traditional sole dummy-insertion operation.

Let P be an orthogonal polygon with n vertices. A partition of P into rectangles is called conforming if it results from cutting P along a set of interior-disjoint line segments, each having both endpoints on the boundary of P. The stabbing number of a partition of P into rectangles is the maximum number of rectangles stabbed by any orthogonal line segment inside P. In this paper, we consider the problem of finding a conforming partition of P with minimum stabbing number. We first give an -time algorithm to solve the problem when P is a histogram. For an arbitrary orthogonal polygon (even with holes), we give an integer programming formulation of the problem and show that a simple rounding results in a 2-approximation algorithm for the problem. Finally, we show that the problem is NP-hard if P is allowed to have holes.

In deep-submicron VLSI manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost of layout storage. In advanced technology nodes, solving the tile-based dummy fill design is more and more expensive. In this paper, we propose a high performance dummy fill insertion framework, where the coupling capacitance issues and density variations are considered simultaneously. We also propose approaches to further consider density gradient minimization. The experimental results for ICCAD 2014 contest benchmarks demonstrate the effectiveness of our methods.

CMP fills are inserted to make metal density uniform and hence reduce post-polish height variations. Classical methods to insert fills focus on metal density uniformity, but do not take into consideration or are unable to minimize the impact of fills on circuit performance. In this paper, we develop a fill insertion method that heuristically minimizes coupling capacitance increase due to fill. Our optimization methodology builds on fill insertion guidelines previously developed in, e.g., [12] and [1]. Experiments show that the proposed optimization methods can reduce fill impact on coupling capacitances by up to 85% for 30% pattern density and up to 65% for 60% pattern density cases.

In very deep-submicron very large scale integration (VLSI),
manufacturing steps involving chemical-mechanical polishing (CMP) have
varying effects on device and interconnect features, depending on local
characteristics of the layout. To reduce manufacturing variation due to
CMP and to improve performance predictability and yield, the layout must
be made uniform with respect to certain density criteria, by inserting
“fill” geometries into the layout. To date, only foundries
and special mask data processing tools perform layout post-processing
for density control. In the future, better convergence of performance
verification flows will depend on such layout manipulations being
embedded within the layout synthesis (place-and-route) flow. In this
paper, we give the first realistic formulation of the filling problem
that arises in layout optimization for manufacturability. Our
formulation seeks to add features to a given process layer, such that
(1) feature area densities satisfy prescribed upper and lower bounds in
all windows of given size and (2) the maximum variation of such
densities over all possible window positions in the layout is minimized.
We present efficient algorithms for density analysis, notably a
multilevel approach that affords user-tunable accuracy. We also develop
exact solutions to the problem of fill synthesis, based on a linear
programming approach. These include a linear programming (LP)
formulation for the fixed-dissection regime (where density bounds are
imposed on a predetermined set of windows in the layout) and an LP
formulation that is automatically generated by our multilevel density
analysis. We briefly review criteria for fill pattern synthesis, and the
paper then concludes with computational results and directions for
future research

Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron very large scale integration have varying effects on device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability, the authors seek to make a layout uniform with respect to prescribed density criteria, by inserting "area fill" geometries into the layout. In this paper, they make the following contributions. First, the authors define the flat, hierarchical, and multiple-layer filling problems, along with a unified density model description. Secondly, for the flat filling problem, they summarize current linear programming approaches with two different objectives, i.e., the Min-Var and Min-Fill objectives. They then propose several new Monte Carlo-based filling methods with fast dynamic data structures. Thirdly, they give practical iterated methods for layout density control for CMP uniformity based on linear programming, Monte Carlo, and greedy algorithms. Fourthly, to address the large data volume and inherent lack of scalability of flat layout density control, the authors propose practical methods for hierarchical layout density control. These methods smoothly trade off runtime, solution quality, and output data volume. Finally, they extend the linear programming approaches and present new Monte Carlo-based methods for the multiple-layer filling problem. Comparisons with previous filling methods show the advantages of the new iterated Monte Carlo and iterated greedy methods for both flat and hierarchical layouts and for both density models (spatial density and effective density). The authors achieve near-optimal filling for flat layouts with respect to each of these objectives. Their experiments indicate that the hybrid hierarchical filling approach is efficient, scalable, accurate, and highly competitive with existing methods (e.g., linear programming-based techniques) for hierarchical layouts.

An O( k log( k )+ n ) algorithm is developed,
where n is the number of versions, to decompose rectilinear
polygons into rectangles. This algorithm uses horizontal cuts only and
reports nonoverlapping rectangles the union of which is the original
rectilinear polygon. This algorithm has been programmed in Pascal on an
Apollo DN320 workstation. Experimentation with rectilinear polygons from
VLSI artwork indicate that the present algorithm is significantly faster
than the plane sweep algorithm and the algorithm proposed by K.D.
Gourley and D.M. Green (1983)

Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local characteristics of the layout. To enhance manufacturability and performance predictability, we seek to make the layout uniform with respect to prescribed density criteria, by inserting "fill" geometries into the layout. We propose several new Monte-Carlo based filling methods with fast dynamic data structures and report the tradeoff between runtime and accuracy for the suggested methods. Compared to existing linear programming based approaches, our Monte-Carlo methods seem very promising as they produce nearly-optimal solutions within reasonable runtimes. I. Introduction As predicted by the International Technology Roadmap for Semiconductors (ITRS) [2], VLSI technology has entered deep submicron regimes, where the manufacturing process tends to have an increasingly constraining effect on physical layout design and v...

We introduce the fill optimization problem and benchmarks. We provide two new hotspot definitions, slot line deviation and outliers, both of which pertain to yield. We provide the inputs, expected output, as well as objectives and constraints of the problem.

In deep-submicron VLSI manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost of layout storage. In advanced technology nodes, solving the tile-based dummy fill design is more and more expensive. In this paper, we propose a high performance dummy fill insertion and sizing framework, where the coupling capacitance issues and density variations are considered simultaneously. The experimental results for ICCAD 2014 contest benchmarks demonstrate the effectiveness of our methods.

The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.

With the increasing need of the SoC (System on a Chip) design automation tools, analog routing is attracting more and more attention. An interactive analog router called SIAR based on splitting graph model was presented in [15]. Based on SIAR, this paper presents a new splitting graph construction (SGC) algorithm to speed up the graph construction process, and thus speed up the whole analog routing process. The presented SGC algorithm has the following features: (1) auxiliary points are added according to the obstacles' corner points, (2) there is no need to construct all the grids along the boundaries of the expanded obstacles, (3) a fast polygon-to-rectangle conversion algorithm is adopted to directly construct the splitting tiles needed by the splitting graph. Experimental results are promising and show 2× speedup on average.

In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.

In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verificat ion. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.

We present an overview of the most important methods that decompose an arbitrary binary object into a union of rectangles. We describe a run-length encoding and its generalization, decompositions based on quadtrees, on mathematical morphology, on the distance transform, and a theoretically optimal decomposition based on a maximal matching in bipartite graphs. We compare their performance in image compression, in moment computation and in linear filtering. We show that the choice is always a compromise between the complexity and time/memory consumption. We give advice how to select an appropriate method in particular cases.

While double patterning lithography (DPL) is still in active development, triple or even quadruple patterning has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle the layout decomposition problem for general multiple patterning lithography (MPL). The main idea is to reduce the problem to sets of concurrent bi-coloring problems. The overall solution is refined iteratively by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this approach is that the existing DPL techniques can be reused seamlessly. Any improvement of them can directly benefit to the MPL counterpart. Moreover, we observe that with the help of the SPQR-tree graph division method, each pass can be fulfilled in nearly linear time. In addition, to prevent the solution getting stuck in the local minima, a randomized initialization strategy is incorporated. The PWC method is executed certain number of times with different randomized initial solutions, out of which the best solution is selected as output. We have implemented our method for particular triple patterning lithography (TPL). The experimental results show that compared with two recently published methods for TPL, our method can reduce the number of conflicts up to 33.2% and 44.9% respectively.

The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.

An abstract is not available.

To reduce chip-scale topography variation in chemical mechanical polishing process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the density-driven dummy fill problem as a standard linear program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. Furthermore, dummy fill can also change the interconnect coupling capacitance which might lead to a significant influence on circuit delay, crosstalk, and power consumption. In this paper, we develop a dummy fill algorithm that can be applied to solve both the traditional density-driven problem and the problem considering fill-induced coupling capacitance impact. The proposed algorithm is both efficient and with provably good performance, which is based on a fully polynomial time approximation scheme by Fleischer for covering LP problems. Moreover, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte Carlo based heuristic methods. Final experimental results demonstrate the effectiveness and efficiency of our algorithms.

An algorithm is presented for partitioning a finite region of the digital plane into a minimum number of rectangular regions. It is demonstrated that the partition problem is equivalent to finding the maximum number of independent vertices in a bipartite graph. The graph's matching properties are used to develop an algorithm that solves the independent vertex problem. The solution of this graph-theoretical problem leads to a solution of the partition problem.

In this paper, we propose an algorithm for partitioning parameterized orthogonal polygons into rectangles. The algorithm is based on the plane-sweep technique and can be used for partitioning polygons which contain holes. The input to the algorithm consists of the contour of a parameterized polygon to be partitioned and the constraints for those parameters which reside in the contour. The algorithm uses horizontal cuts only and generates a minimum number of rectangles whose union is the original orthogonal polygon. The proposed algorithm can be used as the basis to build corner stitching data structure for parameterized VLSI layouts and has been implemented in Java programming language.

Chemical-mechanical planarization (CMP) and other manufacturing steps in every deep-submicron VLSI have varying effects on device and interconnect features, depending on the local density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method according to Y. Chen et al.(2002), our ILP-II method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining ideal quality of the layout density control and our iterated greedy method for MSFC PIL-II problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.

In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verification. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.

Reduced data storage, simplified data, and faster plotting of designs on graphics displaysÂ¿this algorithm has much to offer for IC mask making and CAD applications.

In oxide chemical-mechanical polishing (CMP) processes, layout
pattern dependent variation in the interlevel dielectric (ILD) thickness
can reduce yield and impact circuit performance. Metal-fill patterning
practices have emerged as a technique for substantially reducing layout
pattern dependent ILD thickness variation. We present a generalizable
methodology for selecting an optimal metal-fill patterning practice with
the goal of satisfying a given dielectric thickness variation
specification while minimizing the added interconnect capacitance
associated with metal-fill patterning. Data from two industrial-based
experiments demonstrate the beneficial impact of metal-fill on
dielectric thickness variation, a 20% improvement in uniformity in one
case and a 60% improvement in the other case, and illustrate that
pattern density is the key mechanism involved. The pros and cons of two
different metal-fill patterning practices-grounded versus floating
metal-are explored. Criteria for minimizing the effect of floating or
grounded metal-fill patterns on delay or crosstalk parameters are also
developed based on canonical metal-fill structures. Finally, this
methodology is illustrated using a case study which demonstrates an 82%
reduction in ILD thickness variation

Computing partitions of rectilinear polygons with minimum stabbing number

- Stephane Durocher
- Saeed Mehrabi