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Design and Analysis of Real Time Video Processing Based on DWT Architecture for Mobile Robots

  • K.L.E. Dr. M.S.Sheshgiri College of Engineering & Technology
  • K C College of Engineering and Management Studies and Research, Thane(E) 400607

Abstract and Figures

In this paper we have discussed the design constraints of a computer vision based mobile robot and processing the real time video received from the mobile robot. The focus is on applying DWT algorithm on the real time video so that memory size required for storage is reduced. The mobile robot which feeds in the live steaming of video of surrounding area is of low quality, which has to be processed preciously. Storage of video with respect to memory is also another issue which is addressed. Memory controller is also used as an interface between memory and the processing element.
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Procedia Computer Science 78 ( 2016 ) 544 549
1877-0509 © 2016 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license
Peer-review under responsibility of organizing committee of the ICISP2015
doi: 10.1016/j.procs.2016.02.100
Available online at
International Conference on Information Security & Privacy (ICISP2015), 11-12 December 2015,
Nagpur, INDIA
Design and Analysis of Real Time Video Processing Based on
DWT Architecture for Mobile Robots.
Pramod Kumar Naika*,Arun Tigadib,Dr.Hansraj Guhilotc,Vyasaraj.Td
aDepartment of Electronics & Communication Engg.,VCET, Puttur, Karnataka, India.
bDepartment of Electronics & Communication Engg.,KLE Dr. M.S.S.CET, Belagavi, Karnataka, India.
cPrincipal K C College of Engg, Thane, Mumbai, Maharastra, India.
dDepartment of Electronics & Communication Engg.,VCET, Puttur, Karnataka, India.
In this paper we have discussed the design constraints of a computer vision based mobile robot and processing the real time video
received from the mobile robot. The focus is on applying DWT algorithm on the real time video so that memory size required for
storage is reduced.The mobile robot which feeds in the live steaming of video of surrounding area is of low quality, which has to
be processed preciously. Storage of video with respect to memory is also another issue which is addressed. Memory controller is
also used as an interface between memory and the processing element.
© 2016 The Authors. Published by Elsevier B.V.
Peer-review under responsibility of organizing committee of the ICISP2015.
Keywords: DWT;Mobile Robots; Video Processing;Memory;
1. Introduction
The motivation of providing a Computer Vision mobile robot with high end Spartan 6 FPGA based video
processing is to provide the robot with autonomous capabilities which is reliable, effective and efficient. This kind
of mobile robot will help the rescue team to make use of the effective system for rescue operations. Natural calamity
like earthquakes, flood, explosions or any other catastrophes often result in collapsed buildings with casualties and
* Pramod Kumar Naik Tel.: +91-9481772690; fax: +91-8251-236444.
E-mail address:
© 2016 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license
Peer-review under responsibility of organizing committee of the ICISP2015
Pramod Kumar Naik et al. / Procedia Computer Science 78 ( 2016 ) 544 – 549
wounded people trapped under the debris. When such disaster occur it is very important that one has to search for
survivors with mobile robots with less human risk. Thus these robots will effectively search such areas which are
dangerous and due to their size they can move more effectively and locate survivors.
In order to address the issue of memory, Real Time Video Processing DWT architecture is designed, implemented
and analyzed in FPGA flow. At the heart of JPEG 2000 structure is a wavelet based compression technique provided
a number of advantage over Discrete Cosine Transform. In DCT compression there will be blockiness associated
with compressed video. Although DWT have rough edges they are able to render better picture. Since many years
new algorithms and mathematical approaches are used for signal analysis and signal processing. Pertaining to this
domain wavelets have gained both research interest and practical real time applications. Most of real time signal like
music and video are very complex with non-periodic features. So analyzing and extracting features for recognition
or monitoring of these signals have practical consequences.
2. Literature Survey
Since DWT requires intensive computations, several architectural designs using special purpose parallel processor
have been proposed have been proposed in order to meet many real time applications. The basic solutions include
parallel filter architecture, SIMD linear array architecture, SIMD multigrid architecture, 2D block based architecture
and the AWARE’s wavelet transform processor [10]. First three architectures mentioned above are parallel
processors which can be used for high level of abstraction. The 2-D block based architecture has four MAC unit
with VLSI implementation to perform and execute the forward and inverse transforms. The AWARE’s wavelet
transform processor is capable of computing forward and inverse wavelet transform for 1-D input using six filters
coefficients [11]. Most of the DWT computation is executed either in pipelined or parallel architecture with
extensive user control. There is a clear need for designing and implementing DWT architecture on FPGA with better
memory control for high end applications. Memory controller will act as a module which will take care of
synchronising and refreshing the needs of external memory being connected and requests generated by the
processing elements.
3. FPGA Implementation of Multipliers
During the design of DWT video processing unit, the performance depends on speed of operation of the MAC
unit. In order to make the MAC unit perform faster we made functional changes by implementing different
multipliers in the design of MAC unit and using the best for design. The FPGA implementation results of various
multipliers are compared. From the multipliers we have arrived at the conclusion that Booth Multiplier consumes
more area and also more delay. Due to this fact it requires more time for data propagation from input register to
output register. It is also found that the delay of Vedic unsigned multiplier is fastest compared to these multipliers
mentioned below.
Figure 3.1 Propagation delay of Multipliers.
546 Pramod Kumar Naik et al. / Procedia Computer Science 78 ( 2016 ) 544 – 549
SDRAM Controller
4. Implementation of Real Time DWT Video Processing on FPGA
The heart of DWT computing process is always the MAC unit, therefore DSP engineers are constantly looking for
new algorithm and architecture in MAC to improve performance of the system. Thus various algorithm we can
constantly design and implement it on suitable hardware. The block diagram basically consists of a real time video
input block, DWT video processing block, output block and the entire video processing algorithm is implemented on
desired FPGA implementation. Initially we have real time video file which is to be processed is received from real
time camera which feeds in the input video. This video is processed in the processing block. The main objective is to
save the real time video for surveillance or any security measures in restricted areas. To save the video continuously
it will tedious task as it consumes lot of memory space. Thus to reduce the memory space utility, we compress the
real time video using DWT video compression technique. The major processing is done according to our algorithm
then the video compressed will be displayed in output video file.
This algorithm is designed in MATLAB Simulink which is finally implemented on a FPGA with certain
modifications in the MAC unit and controlling the processing using SDRAM controller. The DWT based
compression of video is done so that the memory size of video is reduced. As shown in the below figure 4.1 a
SDRAM controller has to be used to synchronies the requests raised from the processors. Memory controller is a
component which will take care of the required commands being generated for the proper operation of the external
RAM being connected. It will take for proper read and write cycles and even the proper refresh cycles to retain the
data being written on to it. As shown in the figure 4.1 below an SDRAM controller has to be used to synchronies the
requests raised from the processors. Memory controller is a component which will take care of the required
commands being generated for the proper operation of the external RAM being connected. It will take for proper
read and write cycles and even the proper refresh cycles to retain the data being written on to it.
Figure 4.1 Block Diagram of Real Time DWT Video Processing
Here in this paper we are discussing how video processing parameters can be improved on computer vision based
mobile robots to enhance their performance. Various video processing techniques are applied and few algorithms are
implemented keeping memory as major criteria. These algorithms are applied to real time video received from
wireless camera placed on mobile robot. The RTL of above algorithm is shown in the figure below after synthesis
during the FPGA implementation. The above model was synthesized using Xilinx 14.7 tool suite and implemented
on real time hardware. Our focus is on priority based flow control for different memory access streams. For this
purpose an architecture which resembles above block diagram is designed and implemented.
Pramod Kumar Naik et al. / Procedia Computer Science 78 ( 2016 ) 544 – 549
Figure 4.2 RTL of Real Video Processing
Once done, we are implementing the design on Spartan 6 FPGA. The algorithm created in Xilinx system
generator using JTAG is successfully implemented on Spartan6-LX45 FPGA board and the output is compared with
the software outputs obtained.
Figure 4.3 Input video Figure 4.4 Edge detected video
Figure 4.5 Composited video Figure 4.6 Compressed video
Although the DWT based video compression is achievable, it will be beneficial if parallel and pipelined
architecture which consumes low power and processes at high speed is offered by FPGAs. Today when we
purchase any mobile we look for high end video and multimedia processing. But these application consume huge
548 Pramod Kumar Naik et al. / Procedia Computer Science 78 ( 2016 ) 544 – 549
amount of memory. Thus this drawback can be overcome by using effective video compression algorithms. Thus
this paper explains the overall flow of enhancing and improving the performance. The results shown above are
experimental results demonstrated on Spartan 6 PFGA for high end video platform.
5. Design and Implementation of Mobile Robot
The construction of this rescue robot is very simple, instead of using MDF (Medium Density Fibre board), we
have used metal body of dimension 28x18cm, which gives a ground clearance of around 8cm. The reason behind
using this was the disadvantages encountered by MDF such as the quality of fibre may get staled due to weather
condition and the clearance between the ground and robot was around 1 to 2 cm. The distance between the two
wheels is around 24cm from shaft to shaft.
The body of mobile robot is incorporated by fixing Arduino Duemilanove board, motor driver circuit, XIGBEE
transceiver, GPS module, metal detection circuit, fire sensor, general purpose board servomotors and finally DC
motor. Each are connected separately by maintaining a proper distance between every components and maintain
1cm gap height from metal body of mobile robot, the reason behind this is to avoid the shorting of metal in PCB’s,
which may cause severe damage to the robot. At the end the battery is clamped at the bottom of the body of mobile
robot so that there the connection between board and battery is reduced. A MATLAB GUI was created which
incorporated the motion control of robot, motion control of servomotors, live video streaming through robot to the
GUI with a snapshot
Figure 5.1 Block Diagram of Real Time DWT Video Processing
6. Conclusion
The experimental setup for receiving real time video from mobile robot for analysis is processed in Spartan 6
FPGA. The mobile robot has a ground speed of 10 inches per second, battery life of approximately 55 minutes,
wireless range of between 75 and 100meters, weighs 2.5Kg and has a high level of mobility. The above video
processing algorithm was implemented on Xilinx’s Spartan-6 LX45 FPGA. The architecture uses 316 slices and 259
LUT slices for the above video processing algorithms. At the same time MAC performance is compared by using
Pramod Kumar Naik et al. / Procedia Computer Science 78 ( 2016 ) 544 – 549
various types of multipliers in the design. The proposed DWT unit can be extended for 3D real time video
I would thank the Vivekananda College of Engineering & Technology for providing the various facilities and
resources available. I would also thank KLE Dr. M.S.S.CET, Belagavi for their support in completing this work.
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