Conference Paper

Design space exploration for complex automotive applications: an engine control system case study

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Abstract

With technological advances, significant changes are taking place in automotive domain. Modern automobile combines functionalities ranging from safety critical functions such as control systems for engine to navigation and infotainment. To meet the performances requirements of these systems, automotive industry is shifting to multi-core systems. This increases the design complexity. Efficient and fast design space exploration frameworks are required to deal with this design complexity. This paper presents a framework for exploring automotive application design on multi-core systems. It considers an automotive-specific application modeling language named Amalthea and a distributed-memory multi-core system architecture for execution. The effectiveness of our framework is shown on an engine control application.

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... In addition, the crossbar becomes more difficult to arbitrate with increasing number of cores. The crossbar is suitable for a small number of nodes but not scalable as wire cost becomes even more expensive with manycores [1]. ...
... d 0 to d 3 in Fig. 5.17) to encode 1 bit of data to be transmitted. Fig. 5.18 shows the transition of two logical bits (i.e. from [1,1] to [1,1]) using the 1-of-2 and 1-of-4 protocols. A total of 4 wire transitions occur for 4-phase 1-of-2 as shown in Fig. 5.18a, while only two wire transitions is observed for 4-phase 1-of-4. ...
... d 0 to d 3 in Fig. 5.17) to encode 1 bit of data to be transmitted. Fig. 5.18 shows the transition of two logical bits (i.e. from [1,1] to [1,1]) using the 1-of-2 and 1-of-4 protocols. A total of 4 wire transitions occur for 4-phase 1-of-2 as shown in Fig. 5.18a, while only two wire transitions is observed for 4-phase 1-of-4. ...
Thesis
Full-text available
More computing cores are now being integrated on a single chip in order to meet the ever-growing application demands for high performance and low power computing systems. As the number of cores continues to grow, so is the demand for scalable on-chip communication networks that can deliver high-speed communication among the cores. Contrary to traditional on-chip networks, Networks-on-Chip(NoCs) have emerged as a mature alternative interconnect for manycore architectures since it provides enhanced scalability and power efficiency. Typical NoC routers consist of buffers which serve as temporary data storage. However, studies have shown that buffers are often unutilized (i.e. idle or underutilized) especially when executing applications with non-uniform traffic patterns or bursty behaviours. This is because most typical routers dedicate a set of buffers to their input and/or output ports and these buffers can only be exploited by dataflows using them, which leads to significant performance degradation. Therefore, router architectures capable of maximizing buffer utilization for performance gains are indispensable. In order to maximize buffer resource utilization, this thesis proposes a novel NoC router concept called Roundabout NoC (R-NoC) that is inspired by real-life multi-lanes traffic roundabout. Contrary to existing approaches, R-NoC provides intrinsic and effective resource utilization. However, roundabout-inspired routers are susceptible to deadlocks due to their ring-like architecture. Contrary to existing solutions, R-NoC achieves deadlock-freeness and enhanced network performance over typical NoCs without compromising network area/power. This thesis further exploits R-NoC highly parametric architecture in order to produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.
... Ce travail a été approfondi [12] afin d'inclure, entre autres, une méthode d'exploration de l'espace de conception, proposant des solutions pareto-optimales. Une méthode pour l'exploration d'espace de conception est également proposée par K. Latif et al. [94] pour des applications automobiles. Une approche orientée graphes et automates est également présentée par X. ...
... Les méthodes décrites précédemment concernent essentiellement les systèmes embarqués [133,13,94] et MPSoC [11,12]. Cependant, il existe aussi un intérêt pour la modélisation de systèmes HPC. ...
Thesis
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... Le niveau transaction-level modeling (TLM) [100][101][102][103][104] [111]. Les systèmes étudiés dans cet article adoptent des organisations différentes concernant la mémoire (cf. Figure 3.6). ...
Thesis
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