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PROPOSED IEEE-CS STANDARD FOR BINARY FLOATING POINT ARITHMETIC.
Abstract
A standard for binary floating point arithmetic is briefly described. There is a very real possibility that it will be adopted by many manufacturers and implemented on a wide range of computers.
... Kahan et al. [8] provided 12 commercially important arithmetic expressions, showing different word sizes, precisions, false positive techniques, and overflow and underflow behavior. Additional formulas have been developed. ...
... The sign bit specifies the sign of the binary number, i.e., 0 for positive and 1 for negative. The exponent field represents both the positive and negative exponents [8]. A bias is added to get the stored exponent. ...
Graphical abstract Abstract The compact and accurate way of representing numbers in a wide range is the advantage of floating-point (FP) representation and computation. The floating-point digital signal processors offer the IPs that should have the features of low power, high performance, and less area in cost-effective designs. The proposed paper demonstrates the design and implementation of a 32-bit floating-point arithmetic unit (FPAU). The arithmetic operations performed by the FPAU are in the IEEE 754 single precision format for FP numbers. Before performing the 32-bit FP arithmetic operations, the input operands are converted to IEEE 754 single precision. In order to make use of this functional unit in the processor designs, the proposed work discuss about the creation of custom IP. The validation and verification of this IP will be done with the Xilinx Vivado Design software. Here, the verification is performed with VIO hardware debug IP and Zed board. This FPAU IP can be used in DSP applications and can also be used as a floating-point arithmetic block in semi-custom microprocessor and microcontroller designs. 1.0 INTRODUCTION Precision is crucial in today's cutting-edge technologies for applications like digital signal processing. Calculations in engineering and technology use floating-point numbers to represent non-integer values. The IEEE Standard is the most widely used floating point standard. This standard specifies that FP numbers are represented either 32 bits or 64 bits. More applications, including those involving radars, photography, and telecommunications, require floating-point numbers. This logical approach for the proposed arithmetic operations is to perform them with 32-bit floating-point operands, which are needed in calculation applications. The Verilog hardware description language is used to implement the floating point algorith, which is used to achieve a small area goal. We employ two strategies in Verilog to improve performance. The performance of the circuit is described using the HDL in terms of speed and area. The primary CPU component, the ALU, uses 32 bits to represent floating-point arithmetic operations, logical operations, and other functions. A technical standard for computing FP numbers was developed by the IEEE and is known as the IEEE 754 standard. It has addressed a number of issues that made various FP implementations challenging to use and less portable. As a result, IEEE Standard 754 is a widely used representation for real numbers on computers
... As an approximation to the exact arithmetic operations + , -, x , / performed on pairs of real numbers, the floating- [l], [2]. However, when floating point operations are combined, even for a computation as elementary as a w b [fl c, the relative error of the result may be as large in magnitude as the greatest floating-point number representable in the computer [3]. ...
... For M = 5 and C = 4, p a r t (1) of the figure shows these elements before normalization, In the example, there are 7 leading zeros. Part(2) shows these elements after normalization. ...
A principal limitation in accuracy for scientific computation performed with floating-point arithmetic is due to the computation of repeated sums, such as those that arise in inner products. A systolic super summer of cellular design is proposed for the high-throughput performance of repeated sums of floating-point numbers. The apparatus receives pipelined inputs of streams of summands from one or many sources. The floating-point summands are converted into a fixed-point form by a sieve-like pipelined cellular packet-switching device with signal combining. The emerging fixed-point numbers are then summed in a corresponding network of extremely long accumulators (i.e., super accumulators). At the cell level, the design uses a synchronous model of VLSI. The amount of time the apparatus needs to compute an entire sum depends on the values of summands; at this architectural level, the design is asynchronous. The throughput per unit area of hardware approaches that of a tree network, but without the long wire and signal propagation delay that are intrinsic to tree networks.
... Gradual underflow does not render underflow harmless in all situations. An earlier draft of the IEEE Standard included a "warning" mode to provide some security against loss of precision [Coonen 1980;Coonen et al. 1979;Feldman 1981;IEEE Task P754 1981]. However, the proposal was rather complex, and the protection provided would have been incomplete [Fraley and Walther 1979]. ...
... Consequently, if zeros and infinities have signs, it is best if there is a way to choose at times to ignore those signs, and instead treat the values as though they were unsigned [Coonen 1980;Kahan 1986]. At one time, a draft of the IEEE Standard included separate affine and projective modes to allow the programmer to select whether infinities and zeros should be treated as signed (affine) or unsigned (projective) [Coonen 1980;Coonen et al. 1979;Feldman 1981;IEEE Task P754 1981;Kahan and Palmer 1979]. The projective mode was ultimately dropped, however, in the interest of reducing the complexity of the final standard. ...
Language Constructs Termination exception mechanisms like in Ada and C++ are supposed to terminate an unsuccessful computation as soon as possible after an exception occurs. However, none of the examples of numeric exception handling presented earlier depends ACM Transactions on Programming Languages and Systems, Vol. 18, No. 2, March 1996. Handling Floating-Point Exceptions 167 on the immediate termination of a calculation signaling an exception. The IEEE exception flags scheme actually takes advantage of the fact that an immediate jump is not necessary; by raising a flag, making a substitution, and continuing, the IEEE Standard supports both an attempted/alternate form and a default substitution with a single, simple reponse to exceptions. A detraction of the IEEE flag solution, though, is its obvious lack of structure. Instead of being forced to set and reset flags, one would ideally have available a language construct that more directly reflected the attempted/alternate algorit...
New results are given on error in floating point multiplication. Certain choices of the base minimize the mean multiplicative error. These choices depend on which measure of error is selected. Some measures are included which were not in earlier studies. Some of the results have application to computer design.
Sometimes computational errors are easy to understand once all the uses, as an operand, of each computed value are known. Directed graphs provide a notational device for displaying these dependencies. Simple graph arguments show that gradual underflow improves the performance of certain computational procedures but not others. (Some procedures require deeper analysis.) Here we use graph arguments to show that if computer arithmetic is augmented with a denormal zero, then errors from gradual underflow are always comparable to the uncertainty due to rounding error, though the comparison involves a factor that can grow exponentially with the number of arithmetic operations. Thus for procedures where existence of a denormal zero is unnecessary and the exponential growth is impossible, gradual underflow diminishes the noise from underflow to a level that can safely be ignored.Manchmal lassen sich Berechnungsfehler leicht verstehen, wenn erst einmal fr jeden berechneten Wert alle Operationen bekannt sind, die mit ihm durchgefhrt werden. Mit Hilfe gerichteter Graphen lassen sich diese Abhngigkeiten aufzeigen. Einfache graphentheoretische Argumente zeigen, da allmhlicher Underflow die Ausfhrung gewisser Rechenvorgnge verbessert, von anderen dagegen nicht. (Einige Rechenvorgnge erfordern eingehendere Untersuchungen.) Hier verwenden wir graphentheoretische Argumente, um zu zeigen, da bei Ausstattung der Computer-Arithmetik mit einem denormal zero die Fehler durch allmhlichen Underflow stets mit der Unsicherheit durch Rundungsfehler vergleichbar sind, obwohl dieser Vergleich einen Faktor einschliet, der exponentiell mit der Anzahl der arithmetischen Operationen wachsen kann. Fr Berechungen, bei denen ein denormal zero unntig und der exponentielle Anstieg unmglich ist, vermindert allmlicher Underflow die Verflschung durch Underflow auf ein Ma, das vernachlssigt werden kann.
There are a number of existing floating-point systems (programming languages and libraries) which allow the computer user to produce computation with guarantees. These systems may be conveniently used as a component in theorem proving. Following a brief description of the methodology which underlies these systems, we tabulate them, indicating some properties and noting where they may be obtained for use. A brief appendix supplies an introduction to the formalism of the methodology.
A standard for binary floating-point arithmetic is being proposed and there is a very real possibility that it will be adopted by many manufacturers and implemented on a wide range of computers. This development matters to all of us concerned with numerical software. One of the principal motivations for the standard is to distribute more evenly the burden of portability between hardware and software. At present, any program intended to be portable must be designed for a mythical computer that enjoys no capability not supported by every computer on which the program will be run. That mythical computer is so much grubbier than almost any real computer that a portable program will frequently be denigrated as "suboptimal" and then supplanted by another program supposedly "optimal" for the real computer in question but often inferior in critical respects like reliability. A standard --- almost any reasonable standard --- will surely improve the situation. A standard environment for numerical programs will promote fair comparisons and sharing of numerical codes, thereby lowering costs and prices. Furthermore, we have chosen repeatedly to enrich that environment in order that applications programs be simpler and more reliable. Thus will the onus of portability be shared among hardware manufacturers and software producers.
The data-flow architecture is intended to support large scientific computations, and VAL is an algebraic, procedural language for use on a data-flow computer. VAL is apt for numerical computations but requires an error monitoring feature that can be used to diagnose and correct errors arising during program execution. Traditional monitoring methods (software traps and condition codes are inappropriate for VAL; instead, VAL includes a set of error data values and an algebra for their manipulation. The error data values and their algebra are described and assessed; the conclusion is that error values provide a clean way for a high-level language to handle numeric (and some other) errors.
This report identifies research topics in statistical database management. These topics are grouped into four major areas: characteristics of statistical databases, functionality/usage, metadata, and logical models.
We report on an implementation of the concurrent high level real-time language PEARL on an Intel 8086-based microcomputer. After a short introduction to the PEARL language emphasis is placed on the description of the method of implementation, one of the goals of which was to use standard high level languages and an existing real-time operating system as far as possible. This way an economical, but nevertheless efficient, implementation was achieved.
The computational results of traditional numerical algorithms on computers are usually good approximations to the solution of a given problem. However, no verification is provided for some bound on the maximum relative error of the approximation. As can be demonstrated by ill-conditioned examples, those approximations may be drastically wrong. The algorithms based on the inclusion theory (cf. [38]) do have an automatic verification process. Rather than approximations to the solution an inclusion of the solution is computed and the correctness of the bounds together with the existence and uniqueness of the solution within the bounds is automatically verified by the computer without any effort on the part of the user. The computing time of these algorithms is of the order of a comparable, standard floating-point algorithm (such as Gaussian elimination in case of general linear systems).
In the following some new results complementing the inclusion theory are given. One of the main results is that the inclusion sets need not to be convex. Therefore other types of inclusion sets such as torus-sectors can be used. Another main observation is that the new and old theorems can be proved without using fixed point theorems. Moreover improvements of existing theorems of the inclusion theory by means of weaker assumptions are presented.
Another fundamental observation is the following. It is well-known that a real iteration in IRn with affine iteration function converges if and only if the spectral radius of the iteration matrix is less than one. It can be shown that a similar result holds for our inclusion algorithm: An inclusion will be achieved if and only if the spectral radius of the iteration matrix is less then one. This result is best possible.
It is demonstrated by means of theorems and examples that even for extremely ill-conditioned examples very sharp inclusions of the solution are computed. The inclusions are almost always of least significant bit accuracy, i.e. the left and right bounds of the inclusion are adjacent floating-point numbers.
The division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations. This is due primarily to the need to test the result of one iteration before proceeding to the next. The technique described in this contribution reduces the iteration time by the use of a redundant quotient representation, which avoids the need to complete the arithmetic operation. A borrow–save subtractor (analogous to a carry–save adder) can then be used for the arithmetic. Further improvement is obtained by use of a lookahead decoding technique. Cost reductions are obtained either by use of uncommitted logic arrays, or by a novel borrow–save system using commercially available adder circuitry. A comparison of a number of divider units with a wide range of cost and speed is included.
A parallel computer specifically designed for the solution of
ordinary differential equations is described. The first version of the
machine contains thirty-two processors, running in an asynchronous
multiple-instruction/multiple-data mode, communicating with high-speed
parallel busses. Synchronization is accomplished by a microprogrammable
communication controller. A number of processors have been designed and
built for the machine. The processor types offer a wide variation in
solution speed and accuracy. To permit easy comparisons with analog and
hybrid systems, performance is measured by finding the highest frequency
sine wave which can be integrated in real time with an accuracy of 0.1%
or higher. Using this performance measure the performance limit of the
current machine is 2000 Hz. The structure is capable of solving systems
described by differential equations up to order sixty-four at these
performance limits
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