Article

Trends in Advanced Process Technology—Submicrometer CMOS Device Design and Process Requirements

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Abstract

Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a beating on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. MOSFET diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-µm calls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary.

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Article
This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.
Article
The barrier effects of tungsten inter-layers for aluminum diffusion have been studied in an aluminum/silicon ohmic-contact system, where the tungsten layers were deposited by chemical vapor deposition (CVD) and sputtering. Sintering was carried out at temperatures ranging from 450°C to 550°C and the interfacial reaction was then studied by 1.5 MeV He+ Rutherford backscattering spectroscopy. In the CVD tungsten infer-layer, no discernible reaction took place at each interface up to 500°C. However, reaction occurred at the aluminum-silicon interface in sputtered tungsten even at 450°C, and a WA112 compound was formed, indicating the achievement of a sufficient barrier effect in the CVD layer at 500°C. Tungsten diffused to the aluminum and/or the silicon at 550°C in both samples, and tungsten silicide layers were formed at the tungsten-silicon interface.
Article
Molybdenum nitride coatings on molybdenum using a direct reaction of molybdenum with ammonia is used to improve the gate electrode properties of Mo gate self-aligned MOSFETs. The Mo2N double layer gate shows resistance against oxidation, processing reagents and improved ion implantation masking. The work function of the double layer film was determined to be 4.69 ± 0.03 eV which is independent of the nitride thickness and annealing conditions. Boron implantation range is smaller in Mo2N than Mo. A Mo2N coating of 870Å over 2130Å Mo masks up to 60 keV B11 and 120 keV As75. The implantation study covers the energy range from 15 to 70 keV for boron and from 40 to 160 keV for arsenic.
Article
As linewidths decrease and the number of layers of interconnection increases, the problems of topographically uneven surfaces in VLSI processing become more severe. Several methods to smooth the topograhy, i. e. , 'planarize' it, have been suggested. Some of these use a coating spun-on in the manner used to apply photoresists. The effectiveness of this process and a subsequent 'reflow' bake hve been investigated using several different resists with isolated or coarse line structures. Preliminary reports on the effect of circuit structure density have been reported by us and, more recently, by others. In this paper, results using scanning electron micrographs (SEM), interference micrographs (IM), and profilometer traces (PT) on high density, fine lines are reported.
Article
Planarization of multilevel interconnection is most effective for achieving a higher packing density. However, it is shown by computer simulation that degradation of metallization step coverage becomes serious as th via aspect ratio increases. Conventional deposition methods, in which emitted particles flow onto the substrate and usually do not migrate, are shown to be inadequate for maintaining sufficient step coverage. A new deposition technique, RF/dc sputtering with RF bias for metal, is developed and found to provide sufficient step coverage and, moreover, planarity. In an application of the technique to aluminum film deposition, the existence of a resputtering effect was confirmed. Aluminum particles were found to deposit primarily near the bottom of the depressions and to fill up th depressions completely, through sputtering at a high bias. Steep, deep grooves and vias with aspect ratios up to were found to be completely filled with the aluminum film by deposition at resputtering rates higher than 50%. It was also found that substrate biasing has a decisive effect on giving aluminum films an almost complete (111) crystallographic texture.
Article
We have measured the size effect on the contact resistance (Rc) to shallow junctions in silicon utilizing two different metallization systems. RC(W), where W stands for the contact widths, is found to display a non-quadratic dependence. Thus, our experimental observations show that the commonly used device scaling theory which assumes that contact impedance increases inversely with the square of the scaling factor is incorrect. size effect, contact resistance.
Article
A process has been developed for smoothing surfaces of phosphorus-doped silicon dioxide (P-glass). Samples are coated with a positive photoresist which flows during application to form a relatively smooth surface. The photoresist is etched in a CF//4-O//2 plasma using conditions that etch the photoresist and the P-glass at nearly the same rates. Since the surface profile of the photoresist is preserved during etching, the P-glass is left with a relatively smooth surface. This process reduces step heights, usually by at least 50%, and decreases the angles at abrupt steps to 5 degree -30 degree . In contrast to the flowed P-glass process, planarization does not require high temperatures and is independent of phosphorus concentration.
Article
It is found that average interconnection lengths in a very large scale integrated (VLSI) circuit that is functionally partitioned do not continue to increase as device sizes are scaled down and chips become more densely packed. Although pin requirements still increase, this increase is much smaller than expected from common expressions of Rent's rule. These results suggest that the important dimension in VLSI is of information flow.
Article
A significant reliability related problem was detected during the course of a failure analysis performed on a 16K dynamic RAM. The problem was due to the presence of large silicon nodules in the aluminum metalization which, in comparison to the cross-sectional area of the metal stripe, were large enough to severely restrict current flow. Although silicon nodule formation, has been previously analyzed as a processing variable, it has not been regarded as a significant reliability concern at normal die temperatures. With the advent of VLSI technology and the resultant shrinking line widths, nodule formations must be re- evaluated as a potential yield and reliability concern. The nodule problem becomes serious when the nodule size reduces the effective metal line cross- sectional area such that significant current flow restriction occurs. MIL-STD-883C, Method 2018, Scanning Electron Microscope (SEM) examination procedures also do not readily detect these silicon nodules; nor do most other normal industry screening procedures. This paper discusses techniques used to locate the nodules, comparison of several different vendors product, theory of silicon nodule formation, ramifications to the VLSI industry and the reliability risk to the end user.
Article
An attempt is made to relate increasing performance/cost of VLSI chips to what it imposes on the constituent devices and materials. The requirements are discussed in terms of physical properties as quantitatively as possible. This highlights problem areas where further R and D efforts are needed for the next several years. Possible approaches to solve the problems are discussed and compared where alternatives exist.
Article
The properties of silicon nitride, oxynitride, and oxide films formed by the pyrolysis of various mixtures of , , and are presented. The variation in physical, optical, and electrical properties of this oxynitride series is examined. The electrical and passivation properties of these films on Si are examined and compared with oxides. These electrical data describe the general characteristics of nitride and oxynitride on top of Si and over thin (∼300Aå) and thick (∼1000Aå) thermal oxide films.
Article
We have analyzed the interfacial structure of selectively deposited LPCVD tungsten on monocrystalline silicon, polycrystalline silicon, and polycrystalline aluminum substrates. Cross‐sectional specimens were examined by transmission electron microscopy to determine the amount of substrate consumed by the selective deposition process and to assess the degree of lateral encroachment under masking layers for different conditions of deposition and surface preparation. The tungsten‐silicon interfacial structure was found to depend strongly on the initial surface preparation. Immersion in a dilute solution resulted in a smooth interface, while a glow‐discharge treatment led to highly irregular interfaces, which, in extreme cases, contained tunnels extending 1 μm or more into the silicon substrate. Layers formed in plus were found to consist of two layers, of which the lower layer is formed by the substrate reduction of .
Article
A dual layer metallization system, consisting of a thin contacting layer of titanium covered by a thick layer of molybdenum, has been developed for VLSI applications. At 400°C the thin titanium layer is shown to dissolve thin oxide layers on the silicon surface to make good ohmic contact. Thick molybdenum over the titanium layer has high conductivity, good step coverage, low electromigration, and very smooth surface morphology. This system is both electrically and mechanically stable. Both layers were sequentially sputtered without breaking the vacuum and patterned with a single‐step RIE process. Contact resistance to n+ silicon is about 10 Ω·μm2, and that to p+ silicon is about 19 Ω·μm2, which is lower than that of a W or contact. Leakage current and contact resistance were measured as a function of annealing temperature. The n+ contact does not degrade up to 650°C, whereas the p+ contact is reliable up to 600°C. The overall contact system is stable up to 550°C, maintaining the physical and electrical integrity of the film. SIMS analyses were used to help explain the variations observed in these parameters at high temperatures.
Conference Paper
A study was made of electromigration-induced short circult failure in multilevel metal structures. The material chosen for this study was Al deposited on a layer of TiW, a metallization prone to the formation of whiskers during current stress. The dominant failure mode was found to be interlayer metal shorts. Experiments were performed to examine the relationship between short circuit lifetime and temperature, current density, and interlayer dielectric thickness.
Conference Paper
As MOS gate dielectrics are scaled to thinner dimensions, lognormal statistics determine the limit at which aging screens are no longer effective in reducing the time-dependent failure rate of dielectric breakdown. This paper presents an alternative non-aging reliability screen as applied to ultra-thin DRAM storage gate dielectrics. Early breakdown is correlated with increased dielectric leakage current, which can be detected using the DRAM charge retention characteristics at elevated voltage across the storage dielectric. Accelerated lifetest of screened production 64K DRAMs has confirmed the effectiveness of using non-aging screens to enhance product reliability.
Conference Paper
Time dependent dielectric breakdown (TDDB) data for 100Å of thermally grown SiO2 has been analyzed using an Eyring model based on thermodynamic free energy considerations. The model describes well the following features of the data: (1) an apparent activation energy which is a function of the stressing electric field and (2) a field acceleration parameter that is a function of temperature. Quantitatively, the model suggests the proper field dependence for the activation energy and the observed temperature dependence of the field acceleration in the 100Å oxide material. The apparent activation energy is found to decrease from > leV at low field stressing (Eb(50%) - Es > 5 MV/cm) to <0.3eV at higher fields Eb(50%)- Es < 3 MV/cm). Also, the field acceleration was found to be approximately 6 decades/MV/cm at room temperature but reduces to 2 decades/MV/cm at 150C.
Conference Paper
It is shown that an Al-Si-Ti alloy containing 0.1-0.2wt.% Ti used as an IC-interconnect material reaches the electromigration strength of Al-Si-Cu and simultaneously avoids the disadvantages of Al-Si-Cu like enhanced corrosion susceptibility or dry etching problems. The stabilizing effect of Ti is demonstrated by life testing and additonally by monitoring changes of residual resistivity and heat transfer to the substrate during temperature current stress.
Conference Paper
A new failure mechanism resulting in open metal bit- lines was observed during reliability testing of vendor 64k dynamic random access memory (RAIM) products using sputtered Al-Si metallurgy. Life test data, physical failure analysis, and metal film characterization are presented, The observed phenomenan is not strictly electromigratiotn, but rather a temperature-dependent metal-deformation process, such as creep, resulting in intergranular fracture.
Conference Paper
Direct dynamic observations were made of aluminum electromigration by an in situ scanning electron microscope technique. Time lapse 16 mm moving pictures were taken of electromigration which occurred in a commercially available MC 14050 hex buffer. The circuit was biased above rated specifications to obtain a current density of 7×105 Amps/cm2. The movie film clearly demonstrated a number of new phenomena not previously noted by after the fact examination. Some voids were very mobile and moved up the metallization stripe by a voiding-refill process. Another voiding process was observed in which the aluminum disappeared from the top of a mesa at a point where the current density was essentially zero. The formation of a hillock was observed in which the aluminum growth stretched the aluminum silicate glass which covers the stripes, first by forming a dome and then by rapid vertical and lateral growth. Voids were observed forming within several microns of a growing hillock literally emptying aluminum by a river-like mechanism into the hillock structure that was not constrained by grain boundaries or other defects. Changes in growth patterns (hillocks and voids) were noticed when the circuits were exposed to air ambients for short periods of time. It was observed that the presence of a surface oxide on the walls of a void greatly retard the void growth indicating that a primary mechanism for aluminum transport is along the oxide free wall structure. Additional evidence supporting this migration mechanism is given in the text by high resolution electron micrographs.
Conference Paper
Fabricating BiCMOS test samples, performance and structures of 2 µm and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation, high-packing density LSIs by sharing the roles among them.
Conference Paper
We have fabricated MOSFETs with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all levels with the negative resist GMC in a tri-level configuration. Heat treatments have been as short as possible to preserve very shallow source-drain junction depths (<0.1µm). We observe quasi-long channel behavior for low bias voltages. Measured values for the transconductance are among the highest ever reported. For a channel length L = 0.14 µm, we obtain g m = 180 mS/mm for a gate oxide thickness of 160 Å.
Conference Paper
An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0.5µ. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.
Conference Paper
CMOS technology has been developed through several generations of design rules with an n-type substrate (where p-channel transistors were formed) and with a p-tub implanted and diffused region (where n-channel transistors were formed). In order to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a two-tub approach was adopted. Utilizing lightly doped epi on an n<sup>+</sup>substrate (for latch-up protection), nitride-masked self-aligned tubs, 10<sup>16</sup>cm<sup>-3</sup>surface doping and 600Å gate oxides, an 8-mask CMOS process (named 'Twin-Tub") was formulated. The combination of n on n<sup>+</sup>epi and careful I/O layout renders the circuits latch-up free. Novel aspects of the process, the devices it produces and finally the resultant circuit performance are herein described.
Article
This paper describes a method to improve the electromigration capacity of Al‐Cu or Al thin‐film interconnection metallurgy by incorporating a layer of intermetallic compounds of Al and transition metals. The improvement in lifetime can be 100 times greater than comparable Al‐Cu structures tested under the same conditions. Certain structural properties of the intermetallic compounds have been related qualitatively to the failure mode and electromigration lifetime. Results are discussed in an attempt to clarify the mechanisms by which an ordered phase (compound layer) can improve electromigration lifetime. Life‐test data obtained from the thin‐film metallurgy with Al–transition‐metal compound structures indicate that improvements can be achieved by one or a combination of the following factors: (a) blocking void propagation through the film, (b) reducing the rate of mass transport by electromigration, and (c) eliminating divergent damage sites by increasing the degree of preferred grain orientation. In many cases, the thickness of the intermetallic layer can be adjusted to yield a significant improvement in lifetime with only a small increase in stripe resistance.
Article
Interdiffusion barrier characteristics of molybdenum thin film with aluminum‐1% Si is studied between 733 and 763 K via sheet and contact resistance measurements, Rutherford backscattering spectrometry, secondary ion mass spectrometry, and x‐ray diffraction analysis. The results indicate that thermal annealing of Mo/Al‐1% Si thin film couples leads to MoAl 1 2 compound formation initially as a nonplanar front, but extensive annealing results in complete transformation of Al‐1% Si to MoAl 1 2 and a significant increase in contact resistance. The interdiffusion kinetics is diffusion controlled and shows parabolic time dependence, incubation periods, and extremely high activation energy value of 5.9 eV. The incubation periods and an high activation energy values are explained by the presence of silicon precipitates at the Mo/Al‐1% Si interface. Implications of these observations to VLSI device characteristics are discussed and a safe time‐temperature processing regime is proposed.
Article
A new angled‐surface‐moving model for surface planarization by rf bias sputtering is proposed. This planarization is achieved by angular selective etching of SiO 2 films on top of metal stripes. A two‐step rf bias‐sputtering technique was developed, based on the new model. In this technique, the substrate bias voltage was changed in two steps during bias sputtering. The first step was to fill gaps without microcracks. The second step was to planarize at higher substrate bias. The planarized SiO 2 layer surface, deposited on thermally oxidized Si wafers with Mo stripe patterns, had good flatness. A planarized 4‐level metallization test structure was fabricated by the two‐step rf bias‐sputtering.
Article
An electrical and structural characterization of the Al/Pd 2 Si thin‐film system on n‐type Si was performed with the use of Schottky barrier contacts and subsequent heat‐treatment cycles. Contact barrier energy ϕ Bn , as extracted from current–voltage and capacitance–voltage measurements, decreased initially from about 0.71 eV, characteristic of the Pd 2 Si interface, to a value of 0.65 eV. Auger electron spectroscopy analysis indicates the observed decrease in ϕ Bn corresponds to the decomposition of the Pd 2 Si layer. A drastic alteration of the diode morphology accompanied the decrease in ϕ Bn . Successive heat treatments at higher temperatures and longer times produced little subsequent change in the structural form of the surface, but yielded an increase in ϕ Bn to a value greater than 0.81 eV. Additional data indicated that Al may enter the n‐type Si as a compensating impurity during prolonged heat treatments.
Article
We have examined the thermal stability of Al–Si/TiSi 2 /Si Schottky diodes both with and without a sputter‐deposited W–Ti (10 wt. %) diffusion barrier after furnace annealing up to 550 °C, 30 min. The diodes having the diffusion barrier exhibit stable Schottky barrier heights up to 550 °C, 30 min. In contrast, after 450 °C, 30 min annealing, diodes which do not have a diffusion barrier exhibit Schottky barrier heights typical of Al/n‐Si. Metallurgical interactions have been investigated by He backscattering spectroscopy which shows a stable W–Ti/TiSi 2 interface up to 550 °C, 30 min annealing in samples having the diffusion barrier. The samples without a diffusion barrier show evidence of Al–Ti interdiffusion after 450 °C, 30 min annealing. Residual gas incorporation in the barrier layers was investigated by Ar ion sputter‐depth profiling Auger electron spectroscopy. Sheet resistance measurements and x‐ray diffraction analysis were used to investigate intermetallic phase formation. Selective wet etching combined with scanning electron microscopy were used to determine morphological changes at the TiSi 2 /Si interface as a result of annealing.
Article
Thin metal films of Cr, Ti, Mo, and W–Ti (10 wt.%) have been investigated for their effectiveness in preventing the Al–PtSi reaction which occurs during the post‐metallization alloy treatment of Ohmic contacts and Schottky diodes on integrated circuits. The metal films were deposited by two different dc magnetron sputtering systems. The processed structures were compared for their electrical and metallurgical stability as a function of alloy temperature up to 550 °C for 30 min, as well as for effects of a sputter‐etch versus a wet chemical dip prior to the barrier metal and aluminum alloy deposition. Degradation of the electrical behavior of the contact structures at the higher alloying temperatures is correlated with structural alterations of the layered structures by MeV He ion backscattering and Auger electron spectroscopy with Ar ion sputter‐depth profiling. Conditions under which each barrier metal is useful are presented.
Article
Stringent requirements on the electrical and metallurgical properties of metallization systems for use in advanced, very large scale integrated circuits have created the need to study new metal‐silicon systems. We have conducted a study of the Mo/Si direct contact system. The choice of molybdenum stems from its desirable electrical and metallurgical properties. To date, however, its contact properties to silicon were not examined in detail. Results of the present study show that Mo can result in low resistivities (≪5 Ω μm<sup>2</sup>) for both contacts to heavily doped p<sup>+</sup>‐Si and n<sup>+</sup>‐Si, provided appropriate care is taken in opening the contact windows. Further, we found the Mo/Si contact system to be stable under extended heat treatments at temperatures of up to 650 °C.
Article
We have studied the contact resistance in a metallization system that employs a direct contact between a tungsten–titanium alloy and shallow junctions in silicon. The values obtained in the present study are all within acceptable limits (≪100 Ω μm<sup>2</sup>) for very large scale integration applications. The metal–silicon system has been subjected to moderate heat treatments, similar to those required in processing two‐level metallization schemes. No detrimental effects on the electrical properties of these contacts have been observed.
Article
Electron injection into ultrathin nitrided oxides on silicon reveals both high densities of electronic defects, which readily capture electrons, and efficient tunnel emission of trapped charge. High‐temperature nitridation of thermally grown oxides was verified with Auger depth profiling. In 11–17‐nm‐thick nitrided oxides, the electron trap density is ≥1×10<sup>1</sup><sup>9</sup> cm<sup>-</sup><sup>3</sup> as determined from saturated charge accumulation, the majority of the traps are energetically situated more than 2 eV below the conduction band as determined by post‐injection anneals up to 300 °C, and the capture cross section is of the order of 10<sup>-</sup><sup>1</sup><sup>4</sup> cm<sup>2</sup> as estimated from the trapping kinetics. Complete extraction of trapped charge is achieved in the thinnest films (e.g., ≤11 nm thick), and the tunnel emission mechanism is evidenced by the independence of the discharge time on temperature. Implications of the above findings for applications of ultrathin nitrided oxides in very large scale integration and for their low sensitivity to ionizing radiation are discussed.
Article
We have studied molybdenum as a final metallization level over platinum silicide contacts for very large scale integration (VLSI) application. Molybdenum has been chosen owing to its good metallurgical and electrical properties. The Mo/PtSi contacts to n<sup>+</sup> and p<sup>+</sup> silicon have been found to be stable to heat treatments up to 700 °C for several hours. Values of the specific contact resistance range from ∼5 Ω μm<sup>2</sup> for a 60‐min heat treatment at 400 °C to ∼40–80 Ω μm<sup>2</sup> for a 120‐min treatment at 700 °C.