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Cramming More Components Onto Integrated Circuits
Abstract
The future of integrated electronics is the future of electronics itself. Integrated circuits will lead to such wonders as home computers, automatic controls for automobiles, and personal portable communications equipment. But the biggest potential lies in the production of large systems. In telephone communications, integrated circuits in digital filters will separate channels on multiplex equipment. Integrated circuits will also switch telephone circuits and perform data processing. In addition, the improved reliability made possible by integrated circuits will allow the construction of larger processing units. Machines similar to those in existence today will be built at lower costs and with faster turnaround.
... Nanotechnology focuses on the fabrication, characterization, and manipulation of structures in the size range of 1 to 100 nm, in at least one dimension [3]. In the field of information technology miniaturization is vital and is achieved by doubling the number of transistors in dense integrated circuits approximately every two years following Moore's law [4]. To maintain the trend of fabricating smaller and smaller devices two powerful methods are used. ...
... A particularly promising family of molecular building blocks are porphyrins with functional peripheral substituents. [3][4][5][6][7][8][9][10] Related studies mainly focused on relevant surface reactions such as the direct metalation of the porphyrin macrocycle, coordination of additional ligands and cross-linking via surface coordinative bonds. [3][4][5][6][7][8] The reaction of porphyrins with coadsorbed metal atoms under ultrahigh vacuum (UHV) conditions is especially interesting for the in situ synthesis of reactive metalloporphyrins such as iron(II)-tetraphenylporphyrins. ...
... [3][4][5][6][7][8][9][10] Related studies mainly focused on relevant surface reactions such as the direct metalation of the porphyrin macrocycle, coordination of additional ligands and cross-linking via surface coordinative bonds. [3][4][5][6][7][8] The reaction of porphyrins with coadsorbed metal atoms under ultrahigh vacuum (UHV) conditions is especially interesting for the in situ synthesis of reactive metalloporphyrins such as iron(II)-tetraphenylporphyrins. The latter are difficult to handle outside the vacuum, due to their high affinity toward oxygen. ...
The thesis at hand addresses the adsorption behavior of different tetraphenylporphyrin derivatives (naphthyl and cyano functionalization) on single crystal surfaces at and around RT by scanning tunneling microscopy. It presents a detailed investigation and discussion of intramolecular conformation, diffusion behavior, role of intermolecular interactions in the formation of supramolecular structures, and the interaction and reaction with coadsorbed metal atoms, which sets the stage for the fabrication of functional nanostructures from porphyrins. The publications [P2 and P4] address the adsorption behavior of the naphthyl-functionalized porphyrins 2HTNP and 2HTNBP. We observe a very peculiar adsorption behavior of 2HTNP molecules on Cu(111): Individual molecules are found to adsorb in the “inverted” conformation with upright standing pyrrole rings at RT, which are orientated along the main crystallographic directions of the substrate. Due to the asymmetry of the naphthyl groups, 16 different surface conformers are possible, 10 of which have a different appearance and could indeed be identified by STM. Interestingly, 2HTNBP molecules adsorb as individual molecules as well. On Cu(111), no island formation of 2HTNBP occurs, which indicates a strong interaction of this porphyrin with the substrate, similar to 2HTPP and 2HTNP. The possible driving forces could be a coordination of the iminic nitrogen atoms of the isoindole groups to Cu substrate atoms, like for 2HTPP and 2HTNP, and the larger footprint of the molecules. The investigation of the diffusion behavior of both molecules shows different mobilities, which can be classified into three categories, that is, low, medium, and high. While for 2HTNBP no information of the naphthyl orientation could be linked to the different mobilities, the mobility of 2HTNP is related to the naphthyl orientation relative to the main axis of the molecule along the iminic nitrogen atoms. Fast diffusing species have 3 or 4 naphthyl groups in τ-orientation (pointing in the direction of the movement, which is aligned with the crystallographic axis). Immobile species have only 0 or 1 naphthyl groups orientated in this direction, which equals 4 or 3 groups in α- orientation (away from the main molecular axis and diffusion direction). This behavior shows that the introduction of asymmetric functional groups in the periphery linked to the macrocycle via single C−C bonds can have a strong influence on the adsorption behavior by yielding a variety of non-chiral and chiral conformers, which behave differently in their diffusion. To expand our understanding of the influence of the asymmetric naphthyl group on the adsorption behavior of 2HTNP and 2HTNBP, we studied the adsorption behavior on Ag(111)as well. For 2HTNP on Ag(111), we observed a commensurable 7 -2 / 0 5 structure, leading to identical adsorption sites for each molecule on the surface. Upon annealing to 600 K, the commensurability with the substrate is lost and the structure transforms into a denser packed arrangement. Notably, the distance along one unit cell vector remains unchanged; however, it is no longer aligned along one of the surface high symmetry axes, resulting in only every third molecule sitting on the same adsorption site on the surface (within the margin of error). For 2HTNBP, we observed also island formation on Ag(111) at RT in non-commensurable structures, which are stabilized by T-type interactions between the naphthyl-groups of neighboring molecules. Upon annealing to 500 K, the structure converts to a structure with a slightly higher density, which is now stabilized by π-π stacking of neighboring naphthyl groups. Our studies reveal a pronounced difference of the adsorption of the porphyrins on Cu(111) and Ag(111) surfaces, which is maintained when the pyrrole groups are replaced by an isoindole group and the phenyl groups by naphthyl groups. In summary, the flexibility of the naphthyl group allows for the formation of different conformers on the reactive Cu(111), and structural motifs based on repulsive interactions occurring at too close specific adsorption sites or attractive interactions via T-type bonding or π-π stacking arrangements on Ag(111). The second part of this thesis focusses on the interaction and reaction of cyanofunctionalized phenylporphyrins 2HtransDCNPP and 2HTCNPP with metal atoms (Co and Zn) and is based on the publications [P1 and P3]. On Ag(111), 2HtransDCNPP molecules exhibit a bifunctional behavior toward coadsorbed Co atoms. In a first step, the four N atoms in the macrocycle of the molecules react with Co atoms under the formation of CotransDCNPP (metalation reaction). Cobalt-deposition onto 2HtransDCNPPs leads to a rapid and effective metalation reaction at RT. When switching the deposition order, the metalation reaction requires elevated temperatures. As a second step, the peripheral cyano groups can also coordinate with Co atoms. While a 4-fold coordination motif is preferred, also 3-fold, five-fold and six-fold motifs are observable. The metal–organic coordination structures appear at RT, and annealing at 400 K enhances the coordination process. The metalation reaction of 2HTCNPP with post-deposited Zn atoms to ZnTCNPP on a Ag(111) surface was investigated, and a reaction intermediate (SAT complex) was identified by scanning tunneling microscopy at RT. After Zn deposition onto a 2HTCNPP layer at RT, the formation of three different 2D ordered island types, which coexist on the surface, wasobserved. Within all three island types, a new species could be identified as a bright protrusion, the amount of which correlates with the amount of post-deposited Zn. This species is attributed to a metastable SAT complex. In this SAT complex, the Zn atom coordinates with the macrocycle while the pyrrolic hydrogen atoms are still bound to the nitrogen atoms. This metastable SAT complex has been previously observed by Shubina et al. in the corresponding metalation reaction of the non-cyano-functionalized 2HTPP to ZnTPP, with a characteristic signature in XPS. Upon heating to 500 K, the activation barrier for the subsequent reaction of the intermediate SAT complex to the metalated porphyrin is overcome, yielding ZnTCNPP, and hydrogen desorbs. As an alternative to thermal activation, the barrier for the reaction of the SAT complex to metalated ZnTCNPP can also be overcome by a positive voltage pulse applied to the STM tip. Furthermore, a peculiar long range ordered structure, which covers several terraces of the Ag(111) surface like a carpet, was observed after the deposition of Zn onto a layer of already metalated ZnTCNPP at RT. In conclusion, the thesis at hand gives valuable insights into the adsorption behavior of porphyrins on single crystal metal surfaces like Cu(111) and Ag(111). The functionalization plays a critical role to tailor the peculiar molecular-substrate or molecule-molecule interactions of porphyrins. The presented and discussed results of the publications [P1-4] indicate different strategies to tailor the adsorption behavior of porphyrins on surfaces, and thus deliver a toolbox for the fabrication of functional molecular architectures.
... Table 17: Summary of the performance of the device for the optimized modulator in Figure 43 ..... 118 Table 18: Summary of the performance of the structure of Figure 81 Table 21: Summary of the performance of the device for the optimized modulator in Figure 84 ..... 128 In order to increase the operational frequency of the transistors, the semiconductor industry downscaled the size of the devices. There is an empirical law, called the Moore's law [1], saying that for a constant fabrication cost, the number of transistors in the same surface of an electronic integrated circuit doubles every two years. Since the invention of the transistor [2], this empirical law seems to be true [3] but nowadays it is reaching its limit [4]. ...
... Combining Equation 95 and Equation 96 we obtain the following dispersion relation, A similar analysis can be done for a TE polarized plasmon. Nevertheless the continuity of Ey and Hx leads to the following relation, 1 ( 1 + 1 ) = 0 ...
This work aims to design a CMOS compatible, low-electrical power consumption modulator assisted by plasmons. For compactness and reduction of the electrical power consumption, electro-absorption based on the Franz-Keldysh effect in Germanium was chosen for modulation. It consists in the change of the absorption coefficient of the material near the band edge under the application of a static electric field, hence producing a direct modulation of the light intensity. The use of plasmons allows enhancing the electro-optical effect due to the high field confinement. An integrated electro-optical simulation tool was developed to design and optimize the modulator. The designed plasmonic modulator has an extinction ratio of 3.3 dB with insertion losses of 13.2 dB and electrical power consumption as low as 20 fJ/bit, i.e. the lowest electrical power consumption reported for silicon photonic modulators. In- and out-coupling to a standard silicon waveguide was also engineered by the means of an optimized Si-Ge taper, reducing the coupling losses to only 1 dB per coupler. Besides, an experimental work was carried out to try to shift the Franz-Keldysh effect, which is maximum at 1650 nm, to lower wavelength close to 1.55 {\mu}m for telecommunication applications.
... According to Moore's law the no. of transistors on a single chip has doubled every two years [1], for accommodating high speed and greater functionality on a single IC. This is possible due to further increment in the number of transistor components on a single chip which is possible because of the ever-shrinking size of a single transistor device that has already reached subnanometer regimes. ...
... The cutoff frequency is defined as the frequency point where the current gain assumes the value of unity or is close to the value of unity [15,16]. The cutoff frequency is given by the relation in (1), which is the ratio of the device transconductance (gm) to 2π times the total gate voltage (Cgg). As per the graph, the COFET (and EGFET) shows a much narrower and slightly higher peak than the conventional device owing to the much steeper rise of the drain current and thus a greater value of transconductance (gm), which compensates for the higher capacitance values for the device, which is why even though the gate capacitance of the COFET is more than conventional FinFET, the ratio of transconductance to the gate capacitance (gm/Cgg) of the COFET is greater. ...
This work is an analysis of various RF performance figure of merits of a fully gate-covered Junctionless FinFET at two gate lengths (20nm and 40nm) with a high-k dielectric layer as gate oxide and is compared to a conventional FinFET. The simulation results exhibit great performance increment for the smaller 20nm device in terms of cutoff frequency(fT) which shows about 20% increase, the maximum oscillation frequency (fmax) which is also amplified by more than five times. Other RF parameters such as Gain Frequency Product (GFP) and Transconductance Frequency Product (TFP) for the 20nm device, also exhibited a considerable increment over the conventional device. Gain transconductance frequency Product (GTFP) was also observed to be enhanced by more than 2 times. All these parameters make the device an attractive candidate for RF applications.
... Silicon carbide (SiC) has many attractive properties such as high breakdown strength, high saturation velocity, high thermal conductivity [1], and good microwave absorption [2,3]. Moreover, it is a key component of integrated circuits used in various devices such as computers and cellular phones [4][5][6]. Integrated circuits are tiny, complex electrical components that consist of multiple interconnected metal layers (interconnects) coupled to many electrical circuit elements within a small area. Cu and Ni are rapidly replacing Al in metal interconnects [7,8]. ...
To improve the adhesion between a silicon carbide (SiC) substrate and an electroless-plated Ni film, this study focused on the modification of a SiC substrate via direct fluorination (using F2 gas) at 100–300°C and 380 Torr for 10–120 min. During fluorination, the surface topography of the samples changed markedly at temperatures ≥200°C. However, the SiC surface fluorinated at 200°C adhered poorly to the electroless-plated Ni films because of the formation of hydrophobic layers such as those comprising CF2 and CF3 groups. At temperatures greater than 300°C, CF4 gasification of hydrophobic groups occurred on the SiC surface. This resulted in a SiC substrate with high surface roughness and hydrophilicity that strongly adhered to an electroless-plated Ni film. When the reaction temperature was 300°C and the reaction time was 30 min or longer, the plating adhered strongly to the substrate. The adhesion strength between the SiC substrate and the electroless-deposited Ni film could be enhanced by hydrophilizing and roughening the SiC substrate through direct fluorination with F2.
... Very Large Scale Integrated (VLSI) Circuits continue to adhere to Moore's law ^ [1] with an amazing growth in the last three decades. This trend has resulted in densities of multi-millions of gates per circuit. ...
p>Built In Self Test (BIST) offers an economical and effective solution to the problem of testing VLSI circuits for manufacturing defects. The testability insertion phase for BIST is normally after the logic synthesis and verification in VLSI design cycle. Most methods start from structural descriptions; they include testability features by re-arranging RTL descriptions in order to make the designs more testable. Such methods are sometimes called as high-level test synthesis. Considering testability at such a late stage in design flow often leads to problems such as exceeding chip area, inability to achieve the required throughput and degraded performance. Even though it can be argued that good results have been obtained with such approaches, we must keep in mind that, with the emergence of commercial behavioural synthesis tools, it is difficult for the designer to understand an automatically generated structural RTL description. With ever-increasing levels of complexity and an ever-shrinking time to market window, test synthesis must not be dissociated from design synthesis. High-level CAD tools allow designers to address testability concurrently with design at the highest level of abstraction, promoting the possibility of generating designs optimised both in terms of functionality and self-test. We show that by considering testability at the same time as other design parameters, a better overall solution can be obtained. This work shows that it is possible to generate optimised self-testable RTL from a behavioural description. This is achieved by developing novel and accurate incrementally iterative BIST resource estimation methods and integrating them within a unified synthesis flow. BIST resource estimation is done from the target architecture control path of the design behaviour during design space exploration. In the proposed integration for testability we exploit the available data flow graph information of the design for an automated generation of self test structures for the data path and controller pair.</p
... The MFB receiver is more suitable for Bluetooth than the Viterbi receiver because of its relative insensitivity to errors in modulation index and its ability to accommodate irrational values of h, but its complexity is prohibitive. However, computational power of state of the art DSPs increase rapidly according to Moore's law [39], and in this thesis we propose a more efficient realisation of the MFB receiver that will ensure it is a viable option for most applications, if not today then in the near future. ...
p> High-performance Receiver.
In order to choose a suitable receiver, we first consider the use of high-performance receiver algorithms such as the Viterbi and the matched filter bank (MFB) receiver, both of which exhibit several dB gain over alternative schemes. However, the MFB receiver is more favourable because of the stringent accuracy requirements of the Viterbi receiver on parameters such as carrier frequency and modulation index, both of which have considerable tolerances in Bluetooth systems.
Efficient Receiver
However, the MFB receiver requires several matched filters of considerable length, and is therefore prohibitive to most applications in terms of computational cost. Hence, through the formulation of a novel recursive realisation of the MFB, which employs a much smaller filter bank but processes.the results over several stages, we decrease its complexity by two orders of magnitude without any sacrifice in performance, and thereby make the MFB receiver a more practical option.
Reliable Receiver
Efforts were made to combat irregularities with the received signal such as multipath propagation, carrier frequency and modulation index offsets, which would otherwise undermine the effectiveness of the efficient MFB receiver, and which can be expected in Bluetooth networks.
To deal with dispersive channels we require an algorithm that is resilient to carrier frequency offsets that may exist, and would not yet have been corrected for. Additionally, because of the short bursty nature of Bluetooth transmissions, and the requirement for equalisation to take place before parameter synchronisation algorithms further along the signal processing chain can converge, it is desirable that the equalisation algorithm should converge relatively quickly. Hence, for this purpose we adopt the normalised sliding window constant modulus algorithm (NSWCMA). However, to cater for the correlation between samples of a Bluetooth signal that could make the procedure unstable, we apply and compare a new high-pass signal covariance matrix regularisation, with a diagonal loading scheme.
For parameter synchronisation, a new algorithm for carrier frequency offset correction that is based on stochastic gradient techniques, and appropriate for Bluetooth, is developed. We also show the intermediate filter outputs inherent in the efficient realisation of the MFB may be used to detect carrier frequency and modulation index offsets, which can then be corrected for by recomputing the coefficients of a relatively small intermediate filter bank.
The results of this work could make it possible to achieve the maximum bit error ratio specified for Bluetooth at a much lower signal to noise ratio than is typical, in harsh conditions, and at a much lower associated cost in complexity than would be expected. It would therefore make it possible to increase the range of a Bluetooth link, and reduce the number of requests for packets to be retransmitted, thus increasing throughput.</p
... This situation began to change in the beginning of the 1990s and changed fimdamentally aiound and after 1995, with the continuous shrinking in transistor sizes and the decrease in operating voltage levels (low-power computing). The push for ever-reducing geometries in order to meet the requiiements of Moore's law [3] prompted engineers to look for reliability "workarounds", driven by the need to produce opgrafz've electronics out of yecf fabrication lines. Fault tolerance was identified as such a workaround [4]. ...
p>On-line testing increases hardware reliability, which is essential in safety-critical applications, particularly in hostile operating conditions. High-level synthesis, on the other hand, offers fast time-to-market and allows quick and painless design space exploration. This thesis details the realisation of on-line testability, in the form of self-checking design, within a high-level synthesis environment. The MOODS (Multiple Objective Optimisation in Data and control path Synthesis) high-level synthesis suite is used for the implementation of this concept.
A high-level synthesis tool typically outputs controller / datapath hardware architectures. These two parts pose different self-checking problems that require different solutions. Datapath self-checking is realised using duplication and inversion testing schemes within the circuit data-flow graph. The challenge therein is to identify and implement suitable high-level transformations and algorithms to enable the automatic addition of self-checking properties to the system functionality. This further involves the introduction of an expression quantifying on-line testability and including it in the standard high-level synthesis cost function, thus materialising a three-dimensional design space, to be explored by the designer feeding the synthesis tool with the problem specifications and constraints.
In contrast, controller self-checking is not implemented within the synthesis process, but is rather the result of a post-processing synthesis step, directly applying an appropriate checker to the system control signals. Nevertheless, challenges include choosing suitable self-checking techniques, achieving the Totally Self-Checking (TSC) goal, and investigating ways to reuse any existing datapath self-checking resources for controller on-line testability. Solutions based both on parity-checking and on straightforward 1-hot checking are given, again providing the designer with enhanced opportunities for time-efficient experimentation in search for the best solution in every given synthesis project.
The self-checking structures are finally verified theoretically and experimentally, through fault simulation. Overall, the enhanced version of the MOODS system, produced as a result of this research work, enables the implementation of reliable electronics efficiently, so that reliability-critical applications can be accommodated in a mass production context.</p
... s law predicted in 1965 that every 18 months there will be a doubling of the number of components in intergrated electronics[60]. This forecast waa presented for the increase in performance through to 1975 but still holds true today.* ...
p>An integrated electrical thruster unit for use with work-class under water vehicles has a gap between two cylinders with the inner one rotating resulting in Taylor-Couette flow. It has a small clearance ratio with low Reynolds number turbulent Taylor vortices. To assess the frictional loss in the gap empirical equations were compared, but these show large discrepancies for the small gaps present in the thruster. From these empirical relations a 2mm gap was chosen for the design of the thruster unit. Published literature indicates that the start-up conditions affect the torque due to different Taylor vortex length and also raises questions about the existence of Görtler-type vortices within the turbulent Taylor vortices.
To analyse the flow an experimental rig was designed and constructed with a dynamically similar clearance ratio with a gap of 10mm and an inner radius of 710mm. The presence of Taylor vortices was clearly demonstrated, using bubbles to visualise the flow. A novel method of analysing the bubbles as a probability spectrum, to measure Taylor vortex length, has been developed. The friction resistance has been measured, demonstrating the empirical equations are approximately correct, from analysis of the power lost in the motor used to drive the rig and dynamometry attached to the outer cylinder.
The laminar flow has been successfully modelled with ELMORE, an in-house finite volume Navier-Stokes code with grid independent solutions. Studies were carried out on the effect of Reynolds number and end boundaries conditions on flow properties. These proved that if the vortex size is that of a critical length then the skin friction was the highest, unless adjacent to the end wall. It was also shown that is was possible to model just one vortex between two mirror boundaries.
Turbulent Taylor vortices have been studied using the low Reynolds number k-w formulation using ELMORE and CFX, a commercial, finite volume CFD code. Grid independent results for three radius ratios tested have explained a turbulent flow transition between turbulent two states. For pre-transition the turbulence production is dominated by the outflowing boundary of the Taylor vortex. As the Reynolds number increases, shear driven turbulence, (due to the rotating cylinder) becomes the dominating factor. The effect of Taylor vortex length on skin friction and vortex strength has been evaluated using ELMORE.
The domain has been extended to that of the full geometry, by implementing ELMORE as a parallel solver, to demonstrate the open end effects. These have allowed a comparison of the pressure with the bubble distributions from the experimental results. The transient start-up problem has been solved using a parallel 2-D DNS approach. Although in 2-D, it clearly shows that Görtler vortices are initially present and evolve into stable turbulent Taylor vortices. Four distinct steps have been identified as this flow develops.</p
... Over the past few decades, semiconductor technology has made progress through scaling down and performance improvements of semiconductors according to Moore's Law [1] and the Dennard scaling rule [2]. The planar MOSFET process was successfully replaced and commercialized because the so-called FinFET had better electrostatic control. ...
In this work, WS2 was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolayer WS2 field-effect transistor with a double gate structure (DG WS2-FET) was analyzed. It was confirmed that the effective capacitance, which is circuit power performance, was greatly changed by the extrinsic capacitance components of DG WS2-FET, and the spacer region length (LSPC) and dielectric constant (KSPC) values of the spacer that could affect the extrinsic capacitance components were analyzed to identify the circuit power performance. As a result, when LSPC is increased by 1.5 nm with the typical spacer material (KSPC = 7.5), increased operating speed (+4.9%) and reduced active power (–6.8%) are expected. In addition, it is expected that the spacer material improvement by developing the low-k spacer from KSPC = 7.5 to KSPC = 2 at typical LSPC = 8 nm can increase the operating speed by 36.8% while maintaining similar active power consumption. Considering back-end-of-line (BEOL), the change in circuit power performance according to wire length was also analyzed. From these results, it can be seen that reducing the capacitance components of the extrinsic region is very important for improving the circuit power performance of the DG WS2-FET.
... With continuous downscaling, SS (Sub-threshold slope) is one of the prime terms to recognize the efficiency of device; the reduced SS implies high switching speed of the device. However, in case of MOSFET it has got the limitations of 60 mV/dec since the dependency on the thermal voltage which is known as Boltzmann limitations [1,2]. Moreover, many of the substitute technology come into limelight when its one moves to nanoscale regime [3,4]. ...
This paper deals the hybridization of tunnel FET with the memristor for better execution of combinational and sequential circuits. Here, device structure of vertical tunnel FET and memristor are designed and their performance parameters are investigated. For transistor designing, we have introduced a 40 nm PIN Vertical Tunnel Field effect transistor as with ferroelectric oxide doped with Silicon material added to the device. Various electrical characteristics like drain current-Vgs, Quasi-Fermi Level (QFL), Electron and hole concentration, and surface potential are executed. It is noted that the Ferro material PIN structure Vertical TFET has superior than normal tunnel FET. The highest ON current of the proposed devices and largest ON/OFF current are claimed to be (1.15 × 10–5 A/µm) and (1011), respectively. Then memristor which shows reduced area, low power dissipation, and high durability is combined with Tunnel FET to implement the logic gates. In this regard, two of the logic circuits XOR and NAND gate implemented for circuit analysis. The implemented logic gates provide valid results when match with the conventional logic. Finally, the role of novel memristive devices; Memristor, conductive bridging RAM, phase change memory (PCM), spin devices along with floating gate transistor and optical device are also investigated and discussed for the replacement of the memristor.
... Comme nous l'avons vu dans les Chapitres 2 et 3, l'IA est utilisée dans de nombreux champs d'applications dont la biomédecine et la bio-informatique. Les succès réalisés dans ces domaines sont dus à l'explosion de la capacité de calcul (Moore, 1965) ...
Les projets de séquençage à haut débit produisent une énorme quantité de données biologiques brutes. Cependant, elles sont difficilement exploitables si elles ne sont pas annotées. Pour traiter ces données, des programmes d’annotation de génomes ont été développés, mais ces derniers sont encore trop sujet aux erreurs de prédiction, faisant de l’annotation des génomes un des défis majeurs en bio-informatique. Dans ce contexte, mes travaux de thèse s’organisent autour d’un trinôme : 1) l’amélioration de la prédiction des gènes eucaryotes codant pour des protéines en se focalisant spécifiquement sur les sites d’épissage 2) en exploitant des algorithmes d’intelligence artificielle (CNN et algorithmes évolutionnaires), 3) entraînés avec des données de haute qualité incluant une forte diversité d’espèces eucaryotes. Notre stratégie consiste à combiner l’ensemble des données validées avec les programmes développés afin d’améliorer la prédiction des gènes en diminuant le taux d’erreurs et éviter qu’elles ne se propagent dans les bases de données. De plus, ces travaux permettront une meilleure compréhension des organismes et de leurs mécanismes biologiques.
... La complejidad que puede llegar a presentar un sistema biológico, además de la complejidad de las causas de una enfermedad, hace que los cálculos requeridos para simular el proceso de interacción limite su aplicación o llegue a encarecer la investigación. Gordon Moore (1965) postula textualmente: "La complejidad de los costos mínimos de los componentes ha aumentado a una tasa de aproximadamente un factor de dos por año", lo cual derivó en lo que posteriormente se conocería como la ley de Moore,. Entendiendo que la potencia de los nuevos procesadores se duplica con respecto a sus predecesores cada dos años la ley se ha cumplido hasta el día de hoy, lo cual ha resultado en equipos de cómputo con menores limitaciones para realizar cálculos cada vez más complejos. ...
Resumen Dentro del campo de la química computacional, el acoplamiento molecular o molecular docking ha sido una metodología con un amplio auge. Las problemáticas actuales, tales como los elevados costos que involucran la investigación de nuevos fármacos, la gestión de residuos peligrosos o la remediación de espacios contaminados, han elevado el interés en los métodos computacionales que ayudan a optimizar estos proce-sos. Aunque la reducción de costos que ofrece el diseño asistido por computadora es alta, se debe considerar que entre más complejos sean los sistemas que se evalúen, se incrementarán tanto el costo como el tiempo que consumen los cálculos correspondientes para realizar una predicción adecuada, resultando en un efecto inverso al buscado. Afortunadamente, tal y como fue predicho por la ley de Moore, la potencia de los nuevos procesadores se duplica con respecto a sus predecesores cada determinado tiempo, resultando en equipos con una capacidad de realizar más cálculos en menos tiempo y en nuevo software con menores limitaciones para realizar tareas más complejas. Lo anterior también ha beneficiado la eficacia de las herramientas para realizar acoplamiento molecular, con lo cual a medida que se incrementa el poder de cómputo, disminuye la dificultad de evaluar sistemas más grandes y complejos.[1] El objetivo de este trabajo es proporcionar una breve revisión de la teoría, así como de los avances realizados usando esta herramienta en la investigación sobre cáncer.
... Semiconductor technology, as guided by the International Technology Roadmap for Semiconductors (ITRS) [1] and as described by Moore's law [2], has resulted in highly reliable and fast electronic processors. Further improvements, however, are hampered by prohibitively high power consumption associated with growing heat dissipation [3], and by physical limits that make further gains by size reduction difficult [4]. ...
Network-based biocomputation (NBC) is an alternative, parallel computation approach that potentially can solve technologically important, combinatorial problems with much lower energy consumption than electronic processors. In NBC, a combinatorial problem is encoded into a physical, nanofabricated network. The problem is solved by biological agents (such as cytoskeletal filaments driven by molecular motors) that explore all possible pathways through the network in a massively parallel and highly energy-efficient manner. Whereas there is currently a rapid development in the size and types of problems that can be solved by NBC in proof-of-principle experiments, significant challenges still need to be overcome before NBC can be scaled up to fill a technological niche and reach an industrial level of manufacturing. Here, we provide a Roadmap that identifies key scientific and technological needs. Specifically, we identify technology benchmarks that need to be reached or overcome, as well as possible solutions for how to achieve this. These include methods for large-scale production of nanoscale physical networks, for dynamically changing pathways in these networks, for encoding information onto biological agents, for single-molecule read-out technology, as well as the integration of each of these approaches in large-scale production. We also introduce figures of merit that help analyze the scalability of various types of NBC networks and we use these to evaluate scenarios for major technological impact of NBC. A major milestone for NBC will be to increase parallelization to a point where the technology is able to outperform the current run time of electronic processors. If this can be achieved, NBC would offer a drastic advantage in terms of orders of magnitude lower energy consumption. In addition, the fundamentally different architecture of NBC compared to conventional electronic computers may make it more advantageous to use NBC to solve certain types of problems and instances that are easy to parallelize. To achieve these objectives, the purpose of this Roadmap is to identify pre-competitive research domains, enabling cooperation between industry, institutes and universities for sharing R&D efforts and reduction of development cost and time.
... Underpinning most electronic systems is integrated circuit (IC) technology, which has been advancing exponentially in accordance with Moore's law [82]. Components are shrinking in size, and more are being packed onto chips. ...
Due to the ubiquity of electronic systems, they are relied on now more than they ever have been in the past. Since technology trends suggest that the reliability of these systems will continue to be a serious concern, and due to their use in safety critical domains, they must be robust. Modelling the reliability of systems, electronic or otherwise, affords an understanding of how to design them to be more reliable. The perspective is taken that hardware is assumed to be abundant but faulty, and the question of how to combine unreliable components to produce a reliable system using redundancy is addressed. This leads to a model based on plurality voting, in which the mathematical properties of the model are explored in depth. Additionally, many properties of plurality voting itself are explored and proved. The model is deliberately made to be very general and does not assume the availability of much exploitable information. The parameter space is explored freely, allowing for high levels of redundancy and covering any number of states. These properties make plurality voting a more practical choice than other popular voting methods such as majority voting. Plurality voting is a more involved and lesser explored voting mechanism, particularly on the scale applied in this work. It is found that the rate at which the number of error states grows and the entropy of the error distribution are amongst the most important factors in the reliability. An interesting connection is found between Renyi entropy and plurality voting that provides a practical approximation for calculating the reliability of an arbitrary error distribution in the context of the model. A conjecture is made about this connection and it is proved for a special case. Finally, interesting and complex patterns are discovered when plurality voting is applied in a hierarchical structure. The interactions between the reliability and cost characteristics of the structures reveal that hierarchical structures can be optimal in reliability and cost for regions of high reliability, providing reliability boosts for free. A conjecture is made about the general behaviour of the optimal set of structures to this effect.
... The ever-growing dependence of society on information technologies has lead to remarkable developments over the past decades. Transistor counts in modern processing devices have roughly doubled every two years, as empirically described by Moore's law [1,2], accompanied by similar gains in energy efficiency [3]. However, this exponential increase in computing power is reaching its limits, as miniaturization is becoming increasingly challenging due to thermal constraints [4] and the inevitable influence of quantum effects. ...
We present a proposal for a one-bit full-adder to process classical information based on the quantum reversible dynamics of a triple quantum dot system. The device works via the repeated execution of a Fredkin gate implemented through the dynamics of a single time-independent Hamiltonian. Our proposal uses realistic parameter values and could be implemented on currently available quantum dot architectures. We compare the estimated energy requirements for operating our full-adder with those of well-known fully classical devices, and argue that our proposal may provide a consistently better energy efficiency. Our work serves as a proof of principle for the development of energy-efficient information technologies operating through coherent quantum dynamics.
... Most importantly, it was the birth of Si complementary metal-oxide-semiconductor (CMOS) IC technology in 1963 [6], due to its scaling-enabled integration and economic advantages, that drove the IT revolution into the fast lane. Unfortunately, the scaling-based continuous advances in CMOS IC technologies, mostly driven by Moore's law [7], seem to be slowing down. On the other hand, demands for higher performance (e.g., speed) and more complexity (e.g., functions) of chips, mainly driven by data-centric IoET systems and applications, have been continuously increasing. ...
As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.
... Insgesamt ist die potentielle Leistungsverbesserung durch mehrere Rechenkerne jedoch geringer, als bis 2004 durch Speed-Up des Einzelkerns erreicht wurde [28]. Dennoch ermöglichte diese Mehrkern-Strategie ein Aufrechterhalten des Mooreschen Gesetzes, das die Zunahme der Anzahl an Transistoren pro Chip beschreibt [29]. Mit der aktuellen Entwicklung nähert sich die Verlustleistungsdichte von konventionellen Desktop-und Server-Prozessoren der maximal Möglichen von etwa 140 Watt [13], obwohl inzwischen auch eine Vielzahl von Low-Power Techniken beim Prozessor-Design einsetzt werden [19]. ...
The rapidly increasing spread of information and communication technology in the everyday lives of many people goes hand in hand with an equally rapidly increasing demand for energy-efficient computing power. Easily programmable processors currently provide the majority of this computing power. In the past, such systems were able to meet the increasing demands on computing power through architectural improvements and increases in system clock rates. Approaching the physical limits of conventional processor technology will require the use of new architectural approaches in the future in order to meet the increasing demand for efficient computing power. Field Programmable Gate Arrays (FPGA) have the potential to be an essential part of these new architectures due to their high flexibility and computing efficiency.
FPGAs are already of great importance as specialized implementation options, especially where high computing power is required. As a result, FPGA circuit design has become an increasingly important competence of highly trained electrical engineers. The possible transition from highly specialized niche technology to mainstream technology will require teaching FPGA concepts to a wide variety of target groups, including potential users. Here, the very high complexity of FPGA design represents a major challenge.
This thesis presents a comprehensive tool for flexible and precise scaling of the abstraction of the FPGA design flow. The components of this works approach are suitable to simplify the complexity of the different aspects of FPGA circuit design individually in such a way that the teaching of groups with different levels of knowledge becomes possible. The shown approach preserves all essential concepts of the FPGA circuit design in order to guarantee the successful teaching of the core aspects.
Several case studies show the successful application of the framework developed in the context of this work. The youth competition "INVENT a CHIP" shows the fruitful teaching of basic FPGA concepts to pupils in grades 8 to 13. The laboratory "Design Methods for FPGAs" at the Leibniz University Hannover offers master students in the field of electrical engineering the opportunity to gain in-depth and detailed knowledge about FPGAs. The concept of a novel laboratory for software developers shows the possible abstraction of FPGA design with a focus on hardware-related programming. In addition, the simplification of the FPGA design with the help of the presented tool is able to shorten the design time in rapid prototyping projects significantly. The implementation of a state-of-the-art FPGA demonstration system for video-based person detection using the framework illustrates this aspect.
... microbial communities (Slatko et al., 2018). In parallel, increases in computing power per Moore's law (Moore, 1965) and the development of new bioinformatic tools, machine learning algorithms, and data mining approaches now provide the necessary means to deal with such a huge amount of data (Gauthier et al., 2019;Goodswen et al., 2021). Extreme environments possess a larger than expected microbial diversity, considering the harshness of the conditions that extremophiles need to cope with (Shu and Huang, 2022). ...
... A narrow GNR not only brings the blade contact to PCM, but also serves as channel of a field effect transistor with high on/off ratio. Phase change devices with edge contact of GNRs have shown their potential as the building blocks of unconventional computing architectures to bypass the von Neumann bottleneck 32,33 and overcome the limits of Dennard scaling 34 . ...
Nonvolatile phase change random access memory (PCRAM) is regarded as one of promising candidates for emerging mass storage in the era of Big Data. However, relatively high programming energy hurdles the further reduction of power consumption in PCRAM. Utilizing narrow edge-contact of graphene can effectively reduce the active volume of phase change material in each cell, and therefore realize low-power operation. Here, we demonstrate that a write energy can be reduced to about ~53.7 fJ in a cell with ~3 nm-wide graphene nanoribbon (GNR) as edge-contact, whose cross-sectional area is only ~1 nm2. It is found that the cycle endurance exhibits an obvious dependence on the bias polarity in the cell with structure asymmetry. If a positive bias was applied to graphene electrode, the endurance can be extended at least one order longer than the case with reversal of polarity. The work represents a great technological advance for the low power PCRAM and could benefit for in-memory computing in future.
... In other words: the speed of arithmetic operations could grow exponentially without significantly increasing power consumption. The doubling of the number of transistors and the scaling between chip area and power use are known as Moore's law and Dennard's scaling respectively (Moore 1965;Dennard et al. 1974), and are two key trends to understand the evolution of computing performance and mathematical modeling over the last 50 years. Among others, they facilitated the onset of our current numerical, physics-based approach to model planetary climate change by sustaining the development of a "hierarchy of models of increasing com-plexity", as put by computeer pioneer and meteorologist Jule G. Charney (Balaji 2021). ...
Here we briefly reflect on the philosophical foundations that ground the quest towards ever-detailed models and identify four practical dangers derived from this pursuit: explosion of the model's uncertainty space, model black-boxing, computational exhaustion and model attachment. We argue that the growth of a mathematical model should be carefully and continuously pondered lest models become extraneous constructs chasing the Cartesian dream.
... System designs are increasingly exploiting heterogeneous, accelerator-rich designs to scale performance due to the slowing of Moore's Law [39] and the end of Dennard Scaling [21], [51]. While compute-bound workloads thrive in an acceleratorrich environment, memory-bound workloads such as graph algorithms and sparse algebra present the following challenges: (1) a low compute-per-data ratio, where a lot of the data accessed is not reused; (2) frequent fine-grained irregular memory accesses that make memory hierarchies inefficient; ...
Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work that utilizes prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bandwidth bottlenecks persist due to limited off-chip bandwidth. Approaches using in-memory processing (PIM) with Hybrid Memory Cube (HMC) surpass DRAM bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the granularity of the memory available to each processing core with HMC limits the level of parallelism. This work proposes Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with 16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, using both 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local; (2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; and (4) a novel traffic-aware task scheduling hardware that maintains high core utilization; and (5) a data placement strategy improving work balance. This work proposes architectural and software innovations to provide, to our knowledge, the fastest design for running graph algorithms, while still being programmable for other domains.
... RSA, DES, AES, SHA, and the elliptic curve are a few classical algorithms that use complex mathematics [1]. According to Moore's law, classical computation has limitations because of hardware constraints (miniaturization limits) [2]. The private and public keys are generated by classical algorithms. ...
It's conceivable to have a few dishonest participants when you want to exchange a secret key among participants in a certain network. Due to dishonest participants, a secret key could be altered and disclosed outside of a network. It is reasonable that each participant's involvement would be assessed by a certain organization. The same approach that a secret key must be protected by a header. The protocol to identify two dishonest members in a circular network was proposed by Liu et al. To identify conspirators, Sun et al. expand on the work of Liu et al. Sun et al. suggested a multiparty quantum key agreement protocol based on a circular-type, in which the dishonesty of each member was unknown. To investigate dishonesty, we append a header with a secret key to the Liu et al. and Sun et al. works. Because of the header, the following participants are aware of secret key tampering. Even if some participants became dishonest about a secret key, a circle-type network provided absolute security. There is no performance degradation of the proposed multiparty quantum key agreement protocol with addition of a header.
... Scheme of a photolithographic process using SiO2 and a negative tone photoresist.Soon after the invention of the integrated circuit, Gordon Moore of Fairchild found that for chip production there is an optimum cost of a single component of an IC with respect to the total number of components in the IC.143 This optimum is the best compromise between higher fabrication costs for smaller structures and non-effective material exploitation if the structures are too large. ...
This thesis focuses on the synthesis, fundamental characterization, and partly the application of amorphous low molecular weight materials and polymers. Non-polymeric glass formers, so-called molecular glasses, have gained increasing attention in the last decades. Their application ranges from thin-film processing for micro-manufacturing over organic electronics to pharmaceuticals. However, there is still a lack of understanding concerning fundamental properties of this material class. In particular, detailed investigations on the influence of presence and substitution position of dipolar substituents on T_g, glass-forming ability, and the dynamics of such glasses are missing. Furthermore, specific features in the behavior of asymmetric binary mixtures have recently been discovered. Further investigations of these specific features require tailor-made synthesis of novel molecular glasses to form stable mixtures with low molecular weight additives. While molecular glasses are used in many applications including lithography, they fail to offer specific requirements for resist materials in thermal scanning probe lithography. Thus, the use of polymers for this technique is inevitable. So far only one polymer has been established as resist material, therefore the development of further possible resist materials is of high interest. In this context, the introduction gives an overview about general properties of glass-forming materials, such as glass transition and relaxation behavior. The focus is on (non-polymeric) organic glasses and an overview of design principles yielding stable, high-T_g molecular glasses is presented. The focus then shifts to dynamics as observed in organic glasses and a literature overview is presented dealing with main and secondary relaxation phenomena as observed in organic glasses. As specific features are observed in dynamics of binary mixtures of such glass formers, literature studies addressing these phenomena are presented in more detail and current debates about this topic are discussed. The last part of the introduction gives an overview of the evolution of micro- and nano-lithography, briefly presenting the principles of UV-lithography and focusing on alternative lithographic techniques. State-of-the-art in thermal scanning probe lithography is presented including strategies to improve pattern transfer as well as recent developments of applications going beyond classical lithography for microelectronics. In total, this cumulative thesis consists of four additional chapters, two of which were published as two peer-reviewed full papers. The other two chapters are presented in a manuscript form and intended for submission as full papers shortly. An overview of these topics is presented along with a summary of the major results in the synopsis. The first chapter focuses on the influence of dipole containing nitrile groups and their respective substitution position on T_g and glass-forming ability of molecular glasses based on 9,9’-spirobi[9H]fluorene. The introduction of such highly interacting substituents raises T_g as a function of molar mass by a much higher extent than other substituents previously published in literature. The findings of this topic provide new insight in thermal properties of molecular glasses and may be beneficial for the application of molecular glasses in several fields of research and application. The second chapter features selected compounds studied in the first chapter and focuses on the influence of dipole containing nitrile groups on dielectric relaxation phenomena of these compounds. A clear difference is observed between nitrile groups that have a fixed orientation with respect to the stiff core and others that can change their orientation. The relaxation spectra are compared to those of other well-investigated glass formers. For compounds with a fixed nitrile group, a secondary process with features that have not been reported before is observed. In the third chapter a new asymmetric, binary system of non-polymeric glass formers with a high T_g-contrast of more than 200 K showing neither demixing nor crystallization over the entire temperature and concentration range is developed. Using dielectric spectroscopy, dynamic scanning calorimetry, and dynamic mechanical analysis, a conclusive picture of the dynamics of the investigated system is shown. The relaxation of the high-T_g component shows a plasticizer-effect upon mixing with moderate broadening of the process. The dynamics of the additive at low respective concentrations show a broad distribution of relaxation times and an Arrhenius-like evolution with temperature resembling that of materials in confined space. The obtained results support the interpretation that the concentration-dependent T_g of the α_2-process shows a maximum at intermediate additive concentrations, a currently highly debated issue. The fourth chapter focuses on poly(olefin sulfone)s as new resist materials for thermal scanning probe lithography. These polymers feature a low ceiling temperature and are therefore ideal candidates for this technique. In this context, high-resolution lithography with a resolution down to 10 nm is demonstrated. The obtained patterns are stable towards acidic conditions and thus offer new possibilities for the application of this technique. Sequential infiltration synthesis is used to obtain an etch-resistant hard-mask usable for a subsequent pattern transfer.
... The advent of parallelism in the modern day has brought upon rapid advancement in technology beyond even the predictions of Moore [1]. The efficiency and work rate of computer processes has seen monumental increment, where even the lowest consumer-oriented processors now completely dwarfing top of the line processors of yesteryears. ...
The field of formal language theory involves the construction of words or sentences through a meticulous framework called a system. The set of words derived from the same system is called a language, where it is readily capable of undergoing set operations such as union, concatenation, concatenation closure, -free concatenation closure, homomorphism, inverse homomorphism, and intersection. Recently, a system depicting chemical bonding that generates languages in a parallel manner has been introduced, called bonded parallel insertion-deletion systems. The systems utilize the operations of insertion and deletion on letters with integers attached on either side to produce words where the sum of consecutive integers is zero. In this case, the integers are the bonds of each letter. The system is said to be parallel since the application of the insertion and deletion rules occurs simultaneously at each possible position. The aim of this research is to determine the characteristics of the languages generated by these systems under various set operations.
... The main building block of conventional electronics usually comprises of semiconductor materials. The emergence of modern nanotechnology tools helps silicon-based electronics chips in taking a great leap in miniaturization; however, these semiconductor components shows some limitations when it became few nm in size [2,3]. To overcome such size limitation of semiconductor electronic components, scientists came up with the idea of using molecules as building blocks of electronic components, resulting in emergence of a new branch of science known as molecular electronics [4,5]. ...
Molecular scale plasmonics (MSP) is associated with the area of molecular electronics (ME) where the electronic property of molecules is exploited to generate or modulate plasmons at sub-wavelength confinement. The MSP and ME both occur at diffraction-limited regimes which gives an advantage of understanding both optical and quantum mechanical properties simultaneously. Thus, this emerging field could promise prospective applications in the field of ultrafast information processing, computation, nonlinear and ultrahigh-resolution electronic display, optoelectronic devices, etc. The combination of ME and MSP opens a window to understand the interaction of electromagnetic waves at metal-molecule interface with the help of recently emerging molecular electronic characterization tools in sub-wavelength range. Here, we discuss molecular scale plasmonics with the enunciation of a basic understanding of plasmonics. In addition to these, we systematically discuss various methods of plasmon excitation and detection, using the quantum mechanical models, because classical electrodynamics fails to illustrate the electromagnetic coupling in the sub-nanogaps formed by molecular junctions. Also, we have showcased numerous examples of recent advances in molecular electronic plasmonic including sub-nanometer air/vacuum and molecular gap quantum plasmonic systems. Finally, we conclude this chapter by mentioning the prospects and various challenges in terms of making efficient characterization techniques or better models to explain MSP.
... This bottleneck exists because of the large disparity in performance between the compute units and memory units in modern computing systems. Following Moore's law, the number of transistors in processors has been doubling about every two years, leading to an exponential increase in the power of the processor cores [47]. However, memory performance did not scale comparably which has made the cost of transferring data between the memory and the CPU in some cases more expensive than the actual computations to be performed on the data [48,49]. ...
Sequence alignment is a fundamentally memory bound computation whose performance in modern systems is limited by the memory bandwidth bottleneck. Processing-in-memory architectures alleviate this bottleneck by providing the memory with computing competencies. We propose Alignment-in-Memory (AIM), a framework for high-throughput sequence alignment using processing-in-memory, and evaluate it on UPMEM, the first publicly-available general-purpose programmable processing-in-memory system. Our evaluation shows that a real processing-in-memory system can substantially outperform server-grade multi-threaded CPU systems running at full-scale when performing sequence alignment for a wide variety of algorithms, read lengths, and edit distance thresholds. We hope that our findings inspire more work on creating and accelerating bioinformatics algorithms for such real processing-in-memory systems.
An optical frequency comb (OFC) has a diverse application portfolio, including spectroscopy, ranging, photonic computing, optical communication, and microwave photonics. The silicon photonics technology can reshape all these application areas. It offers compact, energy-efficient, and high-performance integrated photonic systems-on-chip at low cost and high reliability. The primary motivation of the thesis has been to conceptualize and implement the optical frequency comb technology in high bandwidth optical signal processing and optical communication systems in an integrated silicon photonic chip. This thesis explores ways to synthesize and utilize a special kind of OFC in a silicon photonic integrated circuit, where all the comb lines are of equal amplitudes and phase-locked. Such a comb results in a sinc-shaped Nyquist pulse sequence. These pulses can transmit data with the maximum possible symbol rate. Moreover, signal converters that link the analog and digital realms can efficiently leverage orthogonality to optimally utilize the optoelectronic bandwidth if Nyquist pulses are used for sampling. This work presents flexible optical Nyquist pulse generation with repetition rates up to 30 GHz and pulse bandwidths up to 90 GHz using integrated silicon photonic modulators. Besides generating such pulses, this thesis presents a novel source-free all-optical Nyquist pulse sampling technique based on the convolution of the signal spectrum with a rectangular phase-locked OFC. The method presented here can achieve sampling rates of three to four times the optoelectronic bandwidths of the incorporated optical or electronic devices. Further, this sampling technique has been extended to demonstrate an integrated time-magnifier system based on a SiN microring resonator. The proposed OFC-based sampling technique has been further extended to demonstrate an integrated signal agnostic Nyquist transceiver that enables the transmission of signals with the theoretically maximum possible symbol rate in a rectangular bandwidth. Several such rectangular spectral channels were combined into a superchannel and de-multiplexed separately. Moreover, due to its signal agnostic nature, the transceiver can be used for digital communication and analog radio-over-fiber links. Additionally, this thesis will propose and experimentally demonstrate one modulation format aggregation scheme using linear signal processing.
Nowadays microprocessors are among the most complex electronic systems that man has ever designed. One small silicon chip can contain the complete processor, large memory and logic needed to connect it to the input-output devices. The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1]. Even the embedded processors found in everyday devices such as mobile phones are far more powerful than computer developers once imagined. The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect all these components [2]. The speed of the microprocessor is determined by its clock frequency and cannot exceed a certain limit. Namely, as the frequency increases, the power dissipation increases too, and consequently the amount of heating becomes critical. So, silicon manufacturers decided to design new processor architecture, called multicore processors [3]. With aim to increase performance and efficiency these multiple cores execute multiple instructions simultaneously. In this way, the amount of parallel computing or parallelism is increased [4]. In spite of mentioned advantages, numerous challenges must be addressed carefully when more cores and parallelism are used. This paper presents a review of microprocessor microarchitectures, discussing their generations over the past 50 years. Then, it describes the currently used implementations of the microarchitecture of modern microprocessors, pointing out the specifics of parallel computing in heterogeneous microprocessor systems. To use efficiently the possibility of multi-core technology, software applications must be multithreaded. The program execution must be distributed among the multi-core processors so they can operate simultaneously. To use multi-threading, it is imperative for programmer to understand the basic principles of parallel computing and parallel hardware. Finally, the paper provides details how to implement hardware parallelism in multicore systems.
Almost half a billion people world-wide suffer from disabling hearing loss. While hearing aids can partially compensate for this, a large proportion of users struggle to understand speech in situations with background noise. Here, we present a deep learning-based algorithm that selectively suppresses noise while maintaining speech signals. The algorithm restores speech intelligibility for hearing aid users to the level of control subjects with normal hearing. It consists of a deep network that is trained on a large custom database of noisy speech signals and is further optimized by a neural architecture search, using a novel deep learning-based metric for speech intelligibility. The network achieves state-of-the-art denoising on a range of human-graded assessments, generalizes across different noise categories and - in contrast to classic beamforming approaches - operates on a single microphone. The system runs in real time on a laptop, suggesting that large-scale deployment on hearing aid chips could be achieved within a few years. Deep learning-based denoising therefore holds the potential to improve the quality of life of millions of hearing impaired people soon.
If you look at different versions of modern world history, it is not difficult to find a historical record of the movement of workers to destroy machines during the first industrial revolution. Since the age of steam, the faster the evolution of machines, the more intense the crisis felt by man, and the struggle of man against machines has never stopped.
L’étape de gravure des espaceurs de grille est de plus en plus exigeante avec la réduction de la longueur de grille des transistors CMOS. Des architectures 3D sont actuellement proposées pour améliorer leurs performances. De nombreuses contraintes doivent être respectée lors de la fabrication de ces architectures : un contrôle de la dimension critique, une faible consommation de Si constituant de la zone active, une absence de formation de pied au niveau du bas des espaceurs de grille mais aussi de la zone active. L’objectif de la thèse est de développer une nouvelle stratégie de gravure répondant à ces contraintes. Pour ce faire, les travaux ont porté dans un premier temps sur la compréhension des mécanismes de gravure du Si3N4 sélectivement au Si et au SiO2 dans une chimie à base de CH3F/O2/He avec ajout de SiCl4. Dans un second temps, un nouveau procédé de gravure cyclé a été développé pour pallier aux limitations d’une approche continue. La gravure consiste à alterner une chimie en CH3F/O2/He avec ajout de SiCl4 et une chimie en CH2F2/O2/CH4/He pour compléter la gravure des espaceurs de grille sur des architectures 3D. Après développement, nous démontrons que cette stratégie permet de dépasser l’état de l’art. La dimension critique des espaceurs est préservée tout en assurant, avec un nombre limité de cycles, l’élimination totale des espaceurs parasites. Enfin, des stratégies de gravure du matériau SiCOH dense par modification sur les premiers nanomètres ont montré des perspectives intéressantes pour ce type d’application.
Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power-delay product performance (∼122 aJ) with extremely low power (∼0.15 μW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.
The semiconductor industry is the backbone of exponentially growing digitization. Countries from the east and the west both are investing significantly to accelerate this growth. Chemical mechanical planarization (CMP) is one of the crucial technologies for expediting this growth. In 1986, IBM first developed CMP for the polishing of oxide layers. In 1988, it was deployed for the polishing of tungsten. Very soon, the CMP process became popular among the academic researchers and industries due to its global as well as local surface planarization capacity. As the number of active components in a wafer is increasing significantly, the feature size is decreasing for developing high performance integrated circuit (IC) chips. Along with the reducing feature sizes, multiple levels are being implemented. These additional levels necessitate multilevel interconnection. To accommodate all these features, CMP has become an inevitable process for both the semiconductor and solar cell wafer manufacturing industries. The CMP provides a critical support for achieving good surface finish at various levels of IC fabrication. Furthermore, the CMP is also used for the surface polishing of a wide range of materials including sapphire wafers, titanium based biomedical implants, aluminium, copper, YAG crystals, zirconium ceramics, cobalt, molybdenum etc. After its development, ample studies have been carried out for further improvement of CMP processes. However, the intricacy of the process parameters for different wafer & pad materials and slurry composition makes it difficult to indiscriminately apply to any wafer or alloys. Most of the studies have been discretely carried out either on a specific wafer material or based on controlled investigations of certain parameters. In this review paper, CMP has been analysed holistically based on its nanoscale tribological aspects. Several studies have been discussed for the relevant parameters at nano and microscale level including morphology, type, and size of abrasive particles, as well as the arrangement of polishing pad asperities and their conditioning to explore the nanotribological characteristics of CMP. Subsequently, atomic force microscopy (AFM) based studies on CMP have been discussed to correlate it with macroscale CMP. As our mother nature is facing environmental crisis world-wide, research communities should develop environment friendly processes for production. In this regard, the scientists are developing environment friendly CMP process to mitigate the burden of environment. At the same time, researchers can save a mammoth quantity of laboratory resources by carrying out the nanoscale studies of CMP using molecular dynamics simulation approach. In this review, both the green CMP and molecular dynamics studies related to CMP have been discussed. Moreover, the readers can grasp the challenges, difficulties, and achievements of CMP from the nanotribological point of view. Finally, the review presents some insights that can be implemented for further improvements of CMP process.
Optimization of thermal transport across the interface of two different materials is critical to micro-/nanoscale electronic, photonic, and phononic devices. Although several examples of compositional intermixing at the interfaces having a positive effect on interfacial thermal conductance (ITC) have been reported, an optimum arrangement has not yet been determined because of the large number of potential atomic configurations and the significant computational cost of evaluation. On the other hand, computation-driven materials design efforts are rising in popularity and importance. Yet, the scalability and transferability of machine learning models remain as challenges in creating a complete pipeline for the simulation and analysis of large molecular systems. In this work we present a scalable Bayesian optimization framework, which leverages dynamic spawning of jobs through the Message Passing Interface (MPI) to run multiple parallel molecular dynamics simulations within a parent MPI job to optimize heat transfer at the silicon and aluminum (Si/Al) interface. We found a maximum of 50% increase in the ITC when introducing a two-layer intermixed region that consists of a higher percentage of Si. Because of the random nature of the intermixing, the magnitude of increase in the ITC varies. We observed that both homogeneity/heterogeneity of the intermixing and the intrinsic stochastic nature of molecular dynamics simulations account for the variance in ITC.
Recently, the proposed deep multilayer perceptron (MLP) models have stirred up a lot of interest in the vision community. Historically, the availability of larger datasets combined with increased computing capacity led to paradigm shifts. This review provides detailed discussions on whether MLPs can be a new paradigm for computer vision. We compare the intrinsic connections and differences between convolution, self-attention mechanism, and token-mixing MLP in detail. Advantages and limitations of token-mixing MLP are provided, followed by careful analysis of recent MLP-like variants, from module design to network architecture, and their applications. In the graphics processing unit era, the locally and globally weighted summations are the current mainstreams, represented by the convolution and self-attention mechanism, as well as MLPs. We suggest the further development of the paradigm to be considered alongside the next-generation computing devices.
This chapter presents brief descriptions and working principles of 34 emerging technologiesEmerging technologies which have market diffusion and are commercially available. Emerging technologiesEmerging technologies are the ones whose development and application areas are still expanding fast, and their technical and value potential is still largely unrealised. In alphabetical order, the emerging technologiesEmerging technologies that we list in this chapter are 3D printing, 5G, advanced materials, artificial intelligence, autonomous things, big data, biometrics, bioplastics, biotech and biomanufacturing, blockchain, carbon capture and storage, cellular agriculture, cloud computing, crowdfunding, cybersecurity, datahubs, digital twins, distributed computing, drones, edge computing, energy storage, flexible electronics and wearables, healthcare analytics, hydrogen, Internet of Behaviours, Internet of Things, natural language processing, quantum computing, recycling, robotic process automation, robotics, soilless farming, spatial computing and wireless power transfer.
Memristors are intensively studied as being regarded as the critical components to realize the in‐memory computing paradigm. A novel electrochemical metallization memristor based on solution‐processed Pt/CuI/Cu structure is proposed and demonstrated in this work, with a high resistance switching ratio of 1.53 × 107. Owing to the efficient drift paths provided by Cu vacancies for Cu cations in CuI, very small operating voltages (Vset = 0.64 V and Vreset = −0.19 V) are characterized, contributing to ultralow standby power consumption of 9 fW and per set transition of 8.73 µW. Using CuI memristor arrays, a set of Boolean logic operations and a half‐adder are implemented. Moreover, by building the model for a 75 × 48 one‐transistor‐one‐memristor array, the feasibility of hardware encryption and decryption for images is verified. All these demonstrate that solution‐processed CuI memristors possess great potential in constructing energy‐efficient logic‐in‐memory computing architectures. A novel electrochemical metallization memristor based on solution‐processed Pt/CuI/Cu structure is proposed and demonstrated, exhibiting a high resistance switching ratio of 1.53 × 107, ultralow standby power consumption of 9 fW and per set transition of 8.73 µW. Using CuI memristor arrays, a set of Boolean logic operations and a half‐adder are implemented.
Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high‐performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n‐type TMDs such as MoS2 and WS2 grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p‐type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n‐type MoS2 and p‐type vanadium doped WSe2 FETs with non‐volatile and analog memory storage capabilities to achieve a non–von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n‐type and p‐type FETs, which is critical for any IC development. Inverters and a simplified 2‐input‐1‐output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non–von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials. In this work, large area synthesized n‐type MoS2 and p‐type vanadium doped WSe2‐based field effect transistors are integrated, with non‐volatile and analog storage capabilities to demonstrate digital logic and neuromorphic computing primitives highlighting the applicability of the fabrication process flow to realize 2D heterogeneous integrated circuits.
In recent times, logic circuit designing with quantum‐dot cellular automata (QCA) technology is being comprehensively researched because of its inherent miniature size, ultra‐high speed, low power dissipation, and better switching frequency in the nanoregime. In this paper, QCA implementation of a 3 × 3 SSG‐1 reversible gate is first proposed. This gate is then used to design a reversible full adder, reversible 1‐bit comparator, and reversible 4:2 compressor. To evaluate the performance of the proposed QCA designs, an in‐depth comparison with existing designs has been performed. It is seen that the proposed SSG‐1 gate is efficient from the existing designs which eventually leads to efficient designs of adders, comparator, and compressor digital circuits. To further validate this, these digital circuits have also been compared with the literature and performance improvement is clearly observed in these circuits. In addition to this, energy dissipation analysis of all proposed logic gates and digital circuits is also performed for different kink energy levels using the QCA Pro tool and their respective energy dissipation maps are also obtained. Based on this, it is seen that the proposed designs are cost‐efficient and dissipate less energy which makes them more appropriate for designing higher‐order lower power circuits.
Cognitive science has much to contribute to the general scientific body of knowledge, but it is also a field rife with possibilities for providing background research that can be leveraged by artificial intelligence (AI) developers. In this introduction, we briefly explore the history of AI. We particularly focus on the relationship between AI and cognitive science and introduce this special issue that promotes the method of inspiring AI development with the results of cognitive science research. Cognitive science provides background research that can be leveraged by artificial intelligence (AI) developers. In this special issue, we explore methods of inspiring AI development using the results of cognitive science research.
Magnons have demonstrated enormous potential for next‐generation information technology, namely the ability to build quasiparticle low‐power integrated circuits without the moving of electrons. An experimental bosonic magnon transistor with multifunction, low‐loss, and full‐wavelength control of propagating spin waves (magnon current) is developed in this work. Using a monolayer of graphene as the high‐efficiency thermal phonon source and a low‐loss electrically insulating ferrimagnetic single‐crystalline yttrium iron garnet film as the propagating spin‐wave channel, the presented transistor has three functioning regions of spin‐wave modulation at full wavelength: prominent amplification, complete cut‐off, and linear phase shift. The magnon‐phonon‐mediated nonequilibrium state created by the temperature gradient in this transistor works in two ways: when the thermal phonon flow is small, the positive thermal spin‐torque induced by the longitudinal spin‐Seebeck effect amplifies spin waves; when the thermal phonon flow is large, the magnon–magnon interaction due to nonequilibrium thermal magnon injection greatly contributes to spin‐wave cut‐off. Furthermore, linear adjustment of the spin‐wave phase by creating a thermal phonon bath is demonstrated. These findings reveal that the numerous magnon–phonon coupling mechanisms in magnetic insulators offer a promising platform for the implementation of reconfigurable magnonic transistors.
Cu–Cu joints have been adopted for ultra-high density of packaging for high-end devices. However, cracks may form and propagate along the bonding interfaces during fatigue tests. In this study, Cu–Cu joints were fabricated at 300 °C by bonding 〈111〉-oriented nanotwinned Cu microbumps with 30 μm in diameter. After temperature cycling tests (TCTs) for 1000 cycles, cracks were observed to propagate along the original bonding interface. However, with additional 300 °C-1 h annealing, recrystallization and grain growth took place in the joints and thus the bonding interfaces were eliminated. The fatigue resistance of the Cu–Cu joints is enhanced significantly. Failure analysis shows that cracks propagation was retarded in the Cu joints without the original bonding interface, and the electrical resistance of the joints did not increase even after 1000 cycles of TCT. Finite element analysis was carried to simulate the stress distribution during the TCTs. The results can be correlated to the failure mechanism observed by experimental failure analysis.
Das Bedarfs- und Kapazitätsmanagement (BKM) ist ein elementarer Bestandteil des Supply-Chain-Managements der Automobilhersteller. Aufgabe des BKMs ist es, den Ressourcenbedarf, der sich aus der erwarteten oder bereits realisierten Marktnachfrage ergibt, mit den Kapazitäten und Restriktionen der Lieferkette und des Produktionssystems zu synchronisieren. Eine wesentliche Herausforderung für das BKM besteht in der Unsicherheit und Volatilität der Anforderungen, die sich aus der Produktvielfalt ergeben. Informationstechnologie unterstützt zunehmend erfolgreich die komplexen BKM-Prozesse, wobei alle Systeme auf eine effiziente und ganzheitliche Produktrepräsentation angewiesen sind. Die Automobilindustrie sieht sich derzeit mit zwei bedeutenden Trends konfrontiert. Zum einen bewirkt die Diversifizierung des Antriebsstranges (insbesondere im Kontext der E-Mobilität) Veränderungen in der physischen Fahrzeugarchitektur. Zum anderen führt die Digitalisierung des Autos (z. B. autonomes Fahren) neue und veränderte Abhängigkeiten zwischen Komponenten ein (z. B. die Kompatibilität von Hardware und Software). Diese neuen und veränderten Abhängigkeiten sind bei der Entwicklung einer Produktrepräsentation für das automobile BKM angemessen zu dokumentieren. Das Ziel der vorliegenden Dissertation ist die Entwicklung einer effizienten und flexiblen Produktrepräsentation für das BKM der Automobilhersteller zur Abbildung logistikrelevanter Informationen digitalisierter Fahrzeuge.
Durch die beschleunigten Veränderungen des Automobils ist ein flexiblerer und effizienterer BKM-Prozess erforderlich. Dem BKM-Prozess liegen heute jedoch nicht alle benötigten Informationen zugrunde. Um dieses Problem zu adressieren, werden die Prozesseigenschaften anhand der Prozessvarianten des BKMs identifiziert. Durch eine Literaturrecherche und Experteninterviews werden Anforderungen und Produktinformationen aus den Unternehmensbereichen ermittelt, die in die Produktrepräsentation einfließen müssen. Die Produktinformationen aus den Unternehmensbereichen werden analysiert und segmentiert. Anforderungen und speziell Produktinformationen (Digitalcharakteristika), die durch die zunehmende Digitalisierung des Automobils zur ganzheitlichen Darstellung in die Produktrepräsentation integriert werden müssen, werden extrahiert. Durch die Digitalcharakteristika entstehen neue zu integrierende Abhängigkeiten, da sie Einfluss auf die Logistik haben. Zur Auswahl der Datenstruktur und des Konzeptes für eine effiziente und flexible Produktrepräsentation für den BKM-Prozess erfolgt eine weitere Literaturrecherche.
Auf Basis der Ergebnisse wird eine graphbasierten Ontologie der effizienten und flexiblen Produktrepräsentation konzipiert, welche die logistikrelevanten Informationen digitalisierter Fahrzeuge abbildet. Anhand eines realen Anwendungsfalls eines deutschen Automobilherstellers wird die effiziente und flexible Produktrepräsentation prototypisch umgesetzt und validiert.
Groundwater monitoring and specific collection of data on the spatiotemporal dynamics of the aquifer are pre-requisites for effective groundwater management and determine nearly all downstream management decisions. An optimally designed groundwater monitoring network (GMN) will provide the maximum information content at the minimum cost (Pareto optimum). In this study, PySensors, a Python package containing scalable, data-driven algorithms for sparse sensor selection and signal reconstruction with
dimensionality reduction is applied to an existing GMN in 1D (hydrographs) and 2D (gridded groundwater contour maps). The algorithm first fits a basis object to the training
data and then applies a computationally efficient QR algorithm that ranks existing monitoring wells (for 1D) or suitable sites for additional monitoring (for 2D) in order of importance, based on the state reconstruction of this tailored basis. This procedure enables a network to be reduced or extended along the Pareto front. Moreover, we investigate the effect of basis choice on reconstruction performance by
comparing three types typically used for sparse sensor selection (i.e., identity, random projection, and SVD, respectively, PCA). We define a gridded cost function for the extension case that penalizes unsuitable locations. Our results show that the proposed approach performs better than the best randomly selected wells. The optimized reduction
makes it possible to adequately reconstruct the removed hydrographs with a highly reduced subset with low loss. With a GMN reduced by 94 %, an average absolute reconstruction accuracy of 0.1 m is achieved, in addition to 0.05 m with a
reduction by 69 % and 0.01 m with 18 %.
We propose a facile, cost-efficient, environmentally friendly, and scalable process to renew single-walled carbon nanotube membranes serving as extreme ultraviolet (EUV) protective pellicles. The method comprises of high-temperature treatment of the membrane by Joule (resistive) heating at temperatures higher than 1000 °C and pressure below 0.3 Pa. Using model Sn aerosol nanoparticles, the primary contaminant from extreme ultraviolet light sources, we demonstrate the proposed method to clean the membrane with the power consumption as low as 20 W/cm². We show the proposed method to cause no harm to carbon nanotube structure, opening a route towards multiple membrane renovation. We confirm the applicability of the approach using in situ deposition from the semi-industrial EUV light source and subsequent Sn-based contaminant removal, which restores the EUV-UV-vis-NIR transmittance of the film and, therefore, the light source performance. The proposed method supports pulse-cycling opening an avenue for enhanced protection of the lithography mask and stable performance of the EUV light source. Additionally, the approach is suitable to other composite contaminants in a form of nanoparticles based on such species as Pb, In, Sb, etc.
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