Article

A GFSK demodulator for low-IF Bluetooth receiver

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An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process variations without requiring calibration. It can also track and cancel the time-varying local oscillator frequency offset between transmitter and receiver during the entire reception period. The chip was fabricated in CMOS 0.35-μm digital process; it consumes 3 mA from a 3-V power supply and occupies 0.7 mm<sup>2</sup> of silicon area. A 16.2-dB input signal-to-noise ratio is obtained to achieve 0.1% bit-error rate as specified in Bluetooth specs. The co-channel interference rejection ratio is about 11 dB. Theoretical and experimental results are in good agreement.

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... A low-intermediatefrequency (low-IF) architecture and a Gaussian frequencyshift keying (GFSK) modulation scheme are widely used in low-power wireless transceivers for these standards [1]–[3]. For recovering data from GFSK signals, several demodulators with good performance have been reported in [4]–[7]. However, the relatively high power consumption and large modulation index may prevent them from being used for some WPAN/WBAN applications with more stringent requirements on power dissipation and spectral efficiency. ...
... It is a mixed-signal frequency-to-voltage converter. The frequency information of the GFSK signal is mapped into the density of transition edges (phase quantizing points) by the phase quantizer in V A , and then through the fixed-width pulse generator (FWPG) and low-pass filter (LPF), this density is extracted into the voltage variation in V C for data decision [4]. Due to the compact structure, the phase quantization approach can attain good performance with low power consumption. ...
... To improve the spectral efficiency and/or adjacent channel interference rejection, it is desirable to achieve a lower min,GFSK . With both I and Q channels [4], min,GFSK is 0.32. In this work, through an equivalent four-threshold LPQ, we reduce min,GFSK to 0.16, which can fully cover the modulation index of the Bluetooth standard. ...
Article
An ultralow-power Gaussian frequency-shift keying (GFSK) demodulator with large tolerance for process variations and wide coverage of data rate for low-intermediate-frequency (low-IF) wireless receivers is presented. A novel multithreshold linear phase quantization technique is proposed to improve the demodulator sensitivity and relax the tradeoff between the selection of the IF and the data rate. A dynamic threshold slicer is employed to efficiently overcome the dc drifts caused by the input frequency offset. The demodulator achieves 490-mV input dc offset cancellation, 800-kHz frequency offset tolerance, and data rate coverage from 100 kb/s to 2 Mb/s. The measured signal-to-noise ratio (SNR) is 16.0 dB for a 0.1% bit error rate (BER) and a 0.25 modulation index. The demodulator has been fabricated in a 0.18-mum complimentary metal-oxide-semiconductor process with only 0.14-mm<sup>2</sup> active area and 450-muA current drawn from a 1.8-V power supply.
... To avoid a multibit ADC and the inherent automatic gain control (AGC), the BB filter is built selective enough to be followed by a limiter-discriminator frequency-shift keying (FSK) demodulator. Previous implementations of limiter-discriminator demodulators use an analog frequency discriminator yielding a considerable amount of power dissipation and design complexity [7], [8]. The present receiver exploits the BLE's relatively high FSK modulation index to perform analog-to-digital conversion using a flip-flop (FF) clocked at 32 MHz after the limiter amplifier. ...
... Fully digital demodulators may be compact and robust solutions but are prohibitive in low-power designs if requiring multibit ADCs and the associated AGC necessity [20]. Therefore, hybrid analog-digital demodulators have been the norm in classic Bluetooth receivers [8], [9]. However, when compared with classic Bluetooth, BLE allows for a higher FSK modulation index (0.5) and a longer preamble length (8 bit), which led us to the implementation of an all-digital demodulator without a multibit ADC [23]. ...
... Finally, substituting (6) and (39) in (35), and doing some algebraic manipulations, one arrives at the LNA expression given by (8). He is currently an Adjunct Professor with the Department of Maritime Engineering, Escola Náutica Infante D. Henrique, Paço de Arcos, Portugal. ...
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... The RF signal is amplified and down-converted to IF by the RF front end, then, the channel selection is performed by an active complex filter, which is described and proposed in this paper, and next the IF signal is passed through an amplitude limiter which removes any amplitude perturbations. As a final stage, a frequency modulation format (GFSK) demodulator is employed [6]. ...
... Fig. 9(a) shows the CM equivalent of an OTA with no CM control. Note that input CM signal is transferred to the output through the CM transconductance, which happens to be the same value as given in (6). Unless the CM impedance at the output node is low enough, this biasing approach provides high CM voltage gain and may cause CM instability. ...
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A 12th-order OTA-C complex filter with a nonconventional frequency tuning for a Bluetooth receiver is implemented in a low-cost mainstream 0.35-μm CMOS process. This proposed frequency tuning scheme is simpler than the conventional one based on phased-locked loop (PLL). Furthermore, a high-speed pseudo differential OTA using common-mode feedforward (CMFF) and common-mode feedback (CMFB) strategy is proposed. The filter bandwidth is 1 MHz and is centered at 2 MHz. Image and adjacent channels are attenuated by more than 45 and 27 dB, respectively. The integrated input referred noise is 29 μV<sub>rms</sub>, and the filter chip dissipates 4.7 mA from a 2.7 V supply. The theoretical and experimental results are in good agreement.
... The relationship between these two parameters can be computed as Generic models particularized for BT characteristics1516171819 Specific analytical studies on BT [20,21,23,26,28] [24,25,28] Design and implementation of BT demodulators4041424344454647 [48] A taxonomy of the scientific literature on the relationship between the BER rate and the SNR for the different modulations employed by BT ...
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Bluetooth (BT) is a leading technology for the deployment of wireless Personal Area Networks and Body Area Networks. Versions 2.0 and 2.1 of the standard, which are massively implemented in commercial devices, improve the throughput of the BT technology by enabling the so-called Enhanced Data Rates (EDR). EDRs are achieved by utilizing new modulation techniques (π/4-DQPSK and 8-DPSK), apart from the typical Gaussian Frequency Shift Keying modulation supported by previous versions of BT. This manuscript presents and validates a model to characterize the impact of white noise on the performance of these modulations. The validation is systematically accomplished in a testbed with actual BT interfaces and a calibrated white noise generator.
... Other references dealing with the optimization and implementation of BT demodulators for GFSK, p/4-DQPSK and 8 DPSK modulations can be found in [30][31][32][33][34][35][36][37][38]. ...
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... Limiter based demodulator utilizes multiple zero-crossing pulses throughout a symbol period for demodulation. For example, zero crossing detector (ZCD) generates a pulse when the clipped IF signal crosses zero level [7,8]. The generated pulse is followed by low pass filtering that results in demodulated data. ...
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A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset
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A direct-conversion single-chip radio-modem for Bluetooth is presented. The low power and high level of integration associated with a direct-conversion architecture is suited for consumer-oriented digital radio applications such as Bluetooth. The direct-conversion architecture radio resembles a software-defined radio that could be directly scaled to accomodate the next-generation Bluetooth system operated at 2 Mb/s.
Conference Paper
A fully-integrated radio-modem using a direct-conversion receiver architecture achieves -83 dBm sensitivity at 0.1% BER, +40 dBm IIP2, and -5 dB and -40 dB adjacent and alternate channel blocking C/I, respectively. The radio consumes 39 mA in receive and 37 mA in transmit mode with a 2.7 V supply. The 19.5 mm<sup>2</sup> chip uses a 0.35 μm 27 GHz f<sub>T</sub> SOI BiCMOS process
Conference Paper
This paper presents a design of low-cost continuous-phase binary frequency-shift keying (CP-BFSK) demodulator. The proposed demodulator does not require a post-detection filter to suppress sum-frequency components, and hence is suitable for a low-IF receiver architecture. Applied to a Bluetooth receiver with 500 kHz low-IF frequency, the demodulator reaches 10<sup>-3</sup> BER for 16.5 dB SNR and 1 Mbps data-rate. Small modulation indices between 0.28 to 0.35 are demonstrated. Using a 0.25-μm mixed-signal CMOS process, the demodulator occupies an active area of 0.22 mm<sup>2</sup>. The power consumption is 5 mW from a 2.5 V single supply
Conference Paper
A single-chip RF transceiver LSI for 2.4 GHz-band GFSK applications uses a 0.5 μm BiCMOS which provides 23 GHz f<sub>T</sub>. The transceiver consumes 34.4 mA in TX mode (PA, PLL) and 44.0 mA in RX mode (LNA, IR mixer, filters, limiter, RSSI, demodulator, PLL). It has a linear FV conversion demodulator with wide input-frequency range
Conference Paper
Linearization of power amplifiers using baseband signal processing is an important technique applied in digital mobile communication equipment. However, the linearizer performance has been severely influenced by IQ gain/phase imbalance and DC offset in quadrature modems, significant elements of linearizers. In order to eliminate these detrimental influences, a linearizer using a digital quadrature modem has been developed. This paper describes an adaptive predistortion linearizer using a simplified digital quadrature modem with which experimental results of less than -63 dBc of ACI (adjacent channel interference) have been obtained. This excellent performance may be applied in base stations relating to mobile communication systems
Conference Paper
This paper studies the problem of noncoherent detection of Gaussian minimum shift keying (GMSK). Particular attention is focussed on the popular case of BT=0.25, but the concepts presented apply to other cases as well in addition to the general case of continuous phase frequency shift keying (CPFSK). The optimum noncoherent detector is shown to consist of a bank of matched filters followed by a sequence estimator. The metric which must be optimized by the sequence estimator is explicitly given. A simple approximation is introduced which allows the number of matched filters to be reduced from 16 to 3 for GMSK (BT=0.25). A suboptimal metric is introduced which is interpreted as an N-symbol differential detection metric. Based on this metric, a receiver structure is then presented which uses the Viterbi algorithm with a 2 <sup>N</sup> state trellis to perform the sequence estimation. Simulation results indicate that it is possible to obtain performance within 1 dB of optimum coherent detection on either a Gaussian noise or a slowly Rayleigh fading channel with the N=4 symbol differential detector
Conference Paper
A robust frequency-offset compensation technique is proposed and studied for a low-cost noncoherent receiver which can demodulate both analog FM and digital π/4-differential quadrature phase shift keying (DQPSK) signals. In the noncoherent receiver, which employs a frequency discriminator, the RF/IF carrier frequency offset is converted into DC offset in baseband. A baseband DC-offset compensation technique with a modulo 2π operation is proposed to counteract the RF/IF frequency offset. Computer simulations and hardware experiments were conducted to evaluate the performance of the proposed receiver in a static additive white Gaussian noise (AWGN) environment with receiver frequency-offset. It is demonstrated that with the proposed technique using only five preamble symbols, the power penalty for π/4-DQPSK is 2 dB for ΔfT<sub>s</sub> = 10%, where ΔfT<sub>s</sub> is the offset frequency (Δf) normalized to the symbol rate (1/T<sub>s</sub>)
Article
A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm<sup>2</sup> die using TSMC 0.35-μm standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.
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The authors describe a signal-chip radio receiver for VHF and UHF digital wide-area paging transmissions up to 500 MHz with frequency-shift-keying (FSK) data rates up to 1200 Bd. All channel filtering is on-chip and the IC requires only 28 surface mounted external components and a quartz crystal to make a complete receiver. With -126-dBm sensitivity, 70-dB adjacent channel rejection, and 60-dB intermodulation immunity, it satisfies all known pager specifications, worldwide, using the POCSAG paging code. High-dynamic-range mixers, integrated gyrator filters, small-area high-pass filters, and an efficient FSK demodulator combine to give good performance with a current consumption of only 2.7 mA from a 2-V supply. High-density on-chip capacitors in a bipolar process designed for analog RF applications give a chip size of only 4.6×3.8 mm
Article
This paper describes the implementation of a differential Continuous Phase FSK (CPFSK) detector suitable for Low-IF receiver architectures. By using both in-phase and quadrature channels the double frequency term resulting after differential detection can be avoided. The digital detector assumes limited I/Q input signals which are 16 times oversampled. The proposed detector can be used for CPFSK with a modulation index in the range 0.28-0.5. Simulation results are given for a worst case situation in which the modulation index is 0.28. I Introduction Binary differential detection of FM has drawn a lot of attention in the past [FE85, SW83, Eka84, SS86]. Those receivers however, all apply a super heterodyne front-end architecture which first moves the received signal to an intermediate frequency. Fully integration of these receivers is not possible as the image-reject and channel selection filters will be off chip. Low-IF receiver architectures [CS95, BWS + 97] on the other hand enab...