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Analytical device-physics-based models for subthreshold drain
current in short channel SOI MOSFETs facilitate accurate and efficient
circuit simulation. These models also enable prediction of device
scaling limits determined by subthreshold conduction and comparison of
these limits with bulk MOSFETs for the same threshold and supply
voltages

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... This can be achieved by a technology called System on Chip (SoC). Soc means the complete functionality of a system resides on a chip means the processor, memory, I/Os and other peripheral interfaces are all part of single chip [1]. MOSFETs play a vital role in complete IC and hence its performance needs to be exemplified for better SCEs (short channel effects) immunity and electrostatic integrity at nano level. ...

... The different sections in this paper are organized as follows. In Section II, SOI-Finfet [1] details of architecture are discussed . Section III describes methodology used for simulation along Silvaco TCAD simulation flowchart. ...

... There are different types of MOSFETs developed according to the applications like Planar double gate, Omega gate, FINFET and Gate All Around MOSFET. All these MOSFETs will have gate dielectric material between the gate terminal and channel.As the device dimension is further decreases it cause the hot-carrier effects and will degrade the device performance [10][11][12][13][14]. ...

Metal gate technology is one of the promising methods used to increase the drain current by increasing the electrostatic controllability. Different metals have different work-function that controls the device performance very closely as gate to source voltage is the basic inputs for these. In this paper the dependency of gate metal work-function on device performance (both for nMOS and pMOS) is extensively investigated. The gate metal work-function value is taken as 4.2eV to 5.1eV with one increment to see the change in potential profile. With this condition, the I On current, I Off current, threshold voltage, transconductance also calculated for these structures. A decrease value in drain current (1e-6 to 1e-7 A) is observed for both the cases with increase in work-function of gate metal. However, the Off current is getting better (1e-7 to 1e-18 A) while moving towards higher metal work-function values. As a result of which the I On /I Off ratio increases which leads to higher device performances.

... The device was called XMOS because its cross section looks like the Greek letter χ. Using this configuration in 1993, a better control of the channel depletion region is obtained in a "regular" SOI MOSFET and in particular, the influence of the drain electric field on the channel is reduced, which reduces short channel effect [36]. ...

... Scaling of conventional CMOS transistors fabrication technologies has introduced signi due to the short channel effects and dramati leakage current which augments the power req 'OFF' state of the device [1]. Recently, m effect transistors have been introduced to shortcomings [2][3][4]. ...

In this paper, different multi-gate transistor configurations are analyzed using the BSIM-CMG model with emphasis on performance scaling with parameter changes. We examine the effect of key parameters on the leakage current, delay and dynamic power for basic logic gates and the mirror adder. Simulation results indicate a linear increase in the leakage current and the dynamic power with increasing number of fins. On the other hand, with larger number of gates, the static current decreases. Minimum static power dissipation can be achieved with high number of gates and a lesser number of fins.

... The SOl structures generate favorable subthreshold slope, parasitic capacitance, leakage current, and latch up effect. However, in contrast to bulk MOSFETs, the SOl architecture results in the particular short-channel effect as the scaling of the channel lengths [3]- [6]. Numerical and analytical approaches have been presented to suppress the short-channel effect by the optimization of the silicon-body thickness (Tsi-bod y ) or the bottom oxide thickness (Tbox) [5], [7], [8]. ...

This work explores numerically the short-channel effects in thin-body SOI MOSFETs with shallow source/drain architecture, where the junction depths are less than the associated silicon body thicknesses. Unique fringing field and short-channel behavior are observed in the unconventional SOI devices. Numerical results of the short-channel effects are compared with those in the conventional SOI MOSFETs. For given silicon body thicknesses, the shallow junction SOI devices exhibit the superior short-channel immunity over the conventional counterparts.

... The above expression has been derived assuming that the ®rst term of the series expansion of the potential is dominant [18,19]. The results presented in the analysis are consistent with the approximation since the Fourier±Bessel series coef®cients decay rapidly. ...

The present analysis proposes a 2D analytical model of SGT/CGT MOSFET for potential distribution, short channel threshold voltage and current voltage characteristics. The model takes into account the effect of source/drain resistance, field-dependent mobility, velocity saturation and drain-induced barrier lowering (DIBL) effect. Advantages of SGT/CGT MOSFET over conventional planar structures are analyzed in detail and the results obtained are verified with simulated data.

... However, despite its importance, few articles have dealt with the modeling of S, a key factor for transistor performance. Deterioration of the sub-threshold behavior increases the o-current level and standby power dissipation and reduces noise immunity [2]. Such characteristics become particularly important for low voltage portable electronics [7]. ...

A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide semiconductor field effect transistors is presented. The procedure utilizes a channel-potential expression appropriate for submicron dimensions. The final result is similar to that used for long channels except for a factor λ which represents the short channel effects. Comparison with different published results reveals excellent quantitative agreement.

... The device was called XMOS because its cross section looks like the Greek letter (Xi). Using this configuration, a better control of the channel depletion region is obtained than in a "regular" SOI MOSFET, and, in particular, the influence of the drain electric field on the channel is reduced, which reduces short-channel [4]. The first fabricated double-gate SOI MOSFET was the "fully DEpleted Lean-channel TrAnsistor (DELTA, 1989)", where the device is made in a tall and narrow silicon island called "finger", "leg" or "fin". ...

This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices.

... Previous efforts on deriving scaling limits have many short comings. Most previous works on determining the device scaling limit do not consider application dependent limits [105], [106]. Frank [103] derived scaling limits for bulk SCI MOSFETs for various applications, but considered tunable workfunction gates only. ...

The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications. Ph.D. Committee Chair: Meindl, James; Committee Member: Allen, Phillip; Committee Member: Cressler, John; Committee Member: Davis, Jeffrey; Committee Member: Hess, Dennis

With the rapid development of the information age, more and more new technologies such as big data and cloud computing are beginning to emerge. As a result, the demand for high data‐storage density is becoming more and more urgent. In the past 10 years, data‐storage density has been greatly improved by reducing the size of memory cells. However, as semiconductor technology nodes have shrunk, a number of problems have appeared in metal–oxide–semiconductor field‐effect transistor (MOSFET)‐based memory cells, such as gate‐induced drain leakage, drain‐induced barrier lowering, and reliability issues. Fortunately, due to their atomic thickness, high mobility, and sustainable miniaturization properties, 2D atomic crystals (2D materials) are considered the most promising substitute for silicon to solve those issues. This review investigates the use of 2D materials in nonvolatile and volatile memories, including MOSFET‐based memory, magnetic random‐access memory, resistive random‐access memory, dynamic random‐access memory, semi‐floating‐gate memory, and other novel memories.

General introduction of this Chapter shows the evolution of the SOI MOS transistor and retraces the history of the multigate concept. The advantages of multigate FETs in terms of electrostatic integrity and short-channel control are described, and the challenges posed by the appearance of novel effects, some of quantum-mechanical origin, are outlined.

In this paper the electrical characteristics of a novel nanoscale double-gate (DG) silicon-on-insulator(SOI) MOSFET, in which the front gate consists of two materials with different work functions, have been investigated by a full quantum-mechanical simulation. The simulations have been done by the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The quantum simulation results show that the new structure decreases significantly the leakage current and drain conductance and increases the on–off current ratio and voltage gain as compared to the conventional DG SOI MOSFET. In this new structure, the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain, resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

In this paper an analytical drain current model in sub-threshold region is proposed and can be used for MOS or PD-SOI transistors. The model can describe output current dependency on the drain voltage accurately as well as including short channel effects. The proposed model needs only two fitting parameters to predict the current of a transistor with very good accuracy and simply can be used in simulators. To validate the model, it is compared with two short, channel MOS transistors with different technologies by HSPICE simulations.

An analytic model is derived for predicting the anomalous ID−VGfS and ID−VDS characteristics in a floating body fully depleted silicon-on-insulator (SOI) nMOSFETs with parasitic bipolar junction transistor (BJT). All current components in the MOSFET as well as the parasitic BJT are considered in this model. It shows that the single-transistor latch in the ID−VGfS characteristics is due to multistable floating body potentials. The study also reveals that the breakdown and latch phenomena are strongly dependent on the parasitic bipolar current gain and multiplication factor. The effective mobility variation and short channel effects are included in this model. Furthermore parametric dependences, such as SOI film thickness and body doping concentration, are examined to alleviate the latch effect and give the physical insight for optimal design. Results obtained from this model are in good agreement with the measured ID−VGfS and ID−VDS characteristics.

A new vector called the ‘charge density’ or the ‘charge’ vector Q, is defined based on the Poisson equation. Q is used to perform a simple and visual vector analysis of the short channel effect (SCE). The concept of Q(x, y) combines the charge sharing model with the 2-D potential model into one consistent approach. This results in the derivation of a new function: SCE(p), where p is a point in N-dimensional space (N is the number of relevant device parameters). SCE(p) gives information on whether or not a particular device is subject to the SCE. This function was used to derive from theory the empiral scaling law of Brews et al. As an example, the Vτ roll-off is calculated and the influence of the substrate doping on the sub-threshold slope (S) is physically explained using the newly developed concepts.

A field effect transistor fabricated with an oxide channel has been shown to demonstrate switching characteristics similar to conventional silicon metal oxide field effect transistors. This device is believed to operate via a Mott metal-insulator transition induced by the gate field, and offers a potential technology alternative for the regime beyond silicon scaling limitations. © 1998 American Institute of Physics.

An alternative approach for the calculation of the threshold voltage of an SOI MOSFET, taking into account the potential drop in the silicon substrate, is proposed. The approach is extended to short channel devices and improves the predictions of the characteristics of a fully-depleted SOI MOSFET. The current-voltage characteristics are derived by including substrate effect, mobility degradation and channel length modulation in the current saturation region. The theoretical predictions of the model agree with the experimental data available in the literature.

Short-channel effects on the subthreshold behavior are modeled for fully depleted Si-SOI MESFETs through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant minimum bottom potential caused by drain-induced barrier lowering, accurate analytical expressions for short-channel threshold voltage and subthreshold swing are derived. This model is verified by comparison to a two-dimensional device simulator, MEDICI, over a wide range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.2 μm.

This paper discusses the device design of vertical surrounding
gate (VSG) MOSFETs. Poisson's equation is solved using a Laplace
reduction technique and Bessel functions to predict the device
characteristics. The concept of inverse natural/characteristic length
(γ) and critical length (L<sub>critical</sub>) is developed, which
serves as a tool for device optimization for improved performance.
Results thus obtained are in close proximity with published data
available in the literature

A new temperature dependent subthreshold region model for
partially depleted (PD) SOI MOSFET is presented. The model uses the
effective gate bias to replace the gate bias in the current expression.
This effective gate bias ensures smooth transition between tile strong
and weak conduction regions. The model circumvents the discontinuity
inherent in the MOS3 subthreshold region model. The model is applied to
different geometry (PD) NMOS and PMOS SOI devices over very wide
temperature ranges (25-300°C). The model results are closely
correlated the measured results at all temperatures

Short-channel effects (SCE) in ultrathin silicon-on-insulator
(SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model
for threshold voltage, including the kink effect, is presented. The
proposed model accounts for (1) a general nonuniform channel doping
profile, (2) the drain-induced V<sub>th</sub>- lowering enhancement
resulting from the interaction of (a) impact ionization, (b)
floating-body, and (c) parasitic-bipolar effects. Good agreement between
the proposed model and experimental data is demonstrated. Impact
ionization and floating-body effects dominate V<sub>th</sub> lowering
for drain voltages larger than
V<sub>dk</sub>≃B<sub>i</sub>.λ<sub>i</sub>/3, where B<sub>i
</sub> is the impact ionization coefficient, and λ<sub>i</sub> is
the impact ionization length, a structural parameter which, for a
single-drain SOI MOSFET, coincides with the SCE characteristic length
λ

In this paper the various performance advantages of SOI and SOS structures for submicron ULSI circuits will be described. In addition to the traditional speed and radiation-hardness advantages, there are several significant advantages of thin-film SOI compared to bulk structures for the submicron scaling of MOS transistors. These advantages include short-channel threshold voltage stability, improved sub-threshold slope, increased saturation current, and reduced hot electron effects. Both theory and data from several groups will be presented to illustrate these effects. Since these advantages all fall in areas that are critical limits to device engineering and scaling in the submicron regime, the motivation for using SOI should be even stronger as devices are scaled to smaller dimensions in the future. Consideration of SOI or SOS on the ULSI scale will require a technology capable of low defect films with a film thickness of 1000 A or less, however.
The prospects for minority carrier devices such as bipolar transistors for BI-MOS will also be discussed. Both device structure (lateral vs. vertical) and material quality are issues that must be addressed.

It is pointed out that, as MOSFET channel lengths are scaled below
about 0.15 μm, nonstationary carrier transport effects become
increasingly important. These effects can result in increased drain
current over what is expected from stationary transport theory (i.e.
velocity saturation), and in decreased hot-carrier energy spectrum
spread, or carrier temperature, leading to improved device reliability.
However, the magnitude of these effects depends strongly not only on
channel length but also on overall device design such as channel doping
configuration, drain junction depth, etc. Besides minimization of
junction depths, optimal device design requires a super-steep-retrograde
channel doping, with surface doping concentration no higher than mid-10
<sup>16</sup> cm<sup>-3</sup>. This can be achieved with indium doping
for NMOS, and antimony or arsenic doping for PMOS extreme submicron
transistors

SOI is a very promising technology for CMOS-VLSI applications. The use of thin silicon film drastically improves the device characteristics. In this paper we will discuss the main trends to perform a CMOS-SOI technology for high-speed and rad-hard applications.

Monte Carlo simulation is used to explore the characteristics of
an n-channel MOSFET at the presently perceived limits of scaling. This
dual-gated 30 nm gate-length FET is found to have excellent
characteristics for use in digital logic, including a transconductance
as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
The various motivations for this device design are discussed,
illuminating the reasons for claiming that it is at the limits of
scaling

A novel method for obtaining ultra-thin, defect-free silicon on
insulator (SOI) film is introduced. This technique uses epitaxial
lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP).
SOI films with thicknesses of 100 nm were obtained. These films were
used in fabrication and dual poly CMOS devices. The quality of the SOI
film obtained is the same as that of bulk silicon, and the device
characteristics are comparable with those of devices fabricated on bulk.
A minimum geometry unloaded inverter ring oscillator on SOI film
obtained by ELO and CMP showed a speed improvement of 3× over the
bulk devices

Summary form only given. A two-dimensional analytic model is described that is based on the solution of the Poisson's equation in the thin SOI as well as in the gate and buried oxides using an infinite series method. Using this model, the scaling dependence on the thickness of the SOI is studied. It is found that very thin SOI is suitable for deep submicron device application. In applications where bulk-substrate bias is not feasible, it may be possible to provide the equivalent bulk-substrate bias through metal-ion implanted into the buried oxides. The linear region threshold voltage was also investigated using this model and it was found that short-channel behavior in general improves with thin SOI

Buried SiO2, layers were formed by oxygen-ion (14O+) implantation into silicon. The impurity distribution of the oxygen-implanted silicon substrate was analysed by auger spectroscopy. The epitaxially-grown silicon layer on this substrate showed a good monocrystalline structure, and a 19-stage c.m.o.s. ring oscillator exhibited high performance in operation.

The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.

Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

Thin single-crystal silicon-on-insulator films with defect
densities as low as 8×10<sup>5</sup> dislocations/cm<sup>2</sup>
were formed by implantation of 1.5×10<sup>18</sup>
O<sup>+</sup>/cm<sup>2</sup> at 150 kV into bare silicon and annealing
at 1350°C for 6 h in nitrogen. Thin-film submicrometer MOS
transistors were fabricated with self-aligned TiSi<sub>2</sub> fully
covering sources, drains, and gates, and with p<sup>+</sup> and n<sup>+
</sup> polysilicon gates for PMOS and NMOS transistors, respectively,
but without a lightly doped drain. Transistors with gate lengths as
short as 0.4 μm exhibited essentially long-channel behavior with no
kink and with a high saturation current. The device physics was
investigated using PISCES simulations, which agreed well with the
experimental results. A ring-oscillator stage delay of 58 ps was
obtained for 1.0-μm gate length CMOS circuits operating at 5 V

An analytic solution of the Poisson's equation for MOSFETs on very
thin SOI (silicon on insulator) was developed using an infinite series
method. The calculation region includes the thin SOI and the gate and
buried oxides. The results of this model were found to agree well with a
two-dimensional (PISCES) simulation in the subthreshold region and the
linear region with small V <sub>DS</sub>. This model is used to
study the short-channel behavior of very small MOS transistors on thin
SOI. It is found that with very thin SOI, short-channel effects are much
reduced compared to bulk MOS transistors and depend on the
bulk-substrate bias. The model also shows that it is possible to
fabricate submicrometer transistors on very thin SOI even if the channel
doping is nearly intrinsic

The formulation and solution of the equations governing transistor
subthreshold behavior in explicit analytical form provide quantitative
predictions for minimum feature length as well as immediate information
on the relative importance of all major transistor fabrication
parameters. Such a formulation and a solution for subthreshold
conduction are presented. The importance of gate oxide thickness,
channel impurity concentration, source-drain junction depth, and applied
potentials are examined. The results suggest that successful advanced
process development programs must devise methods for ultrashallow
(<100 Å) source-drain junction formation and ultrathin (<50
Å) gate insulators. With vanishingly small (<50 Å)
junction depth, a 30 Å gate oxide dielectric and a channel
acceptor concentration of 2×10<sup>18</sup> per cubic centimeter,
one can achieve acceptably low subthreshold conduction at effective
channel lengths down to 0.06 μm at an operating temperature of 300 K

Short-channel effects in thin-film silicon-on-insulator (SOI)
MOSFETs are shown to be unique because of dependences on film thickness
and body and back-gate (substrate) biases. These dependences enable
control of threshold-voltage reduction, channel-charge enhancement due
to a drain bias, carrier velocity saturation, channel-length modulation
and its effect on output conductance, as well as device degradation due
to hot carriers in short-channel SOI MOSFETs. A short-channel effect
exclusive to SOI MOSFETs, back-surface charge modulation, is described.
Because of the short-channel effects, the use of SOI MOSFETs in VLSI
circuits provides the designer with additional flexibility as compared
to bulk-MOSFET design. Various design tradeoffs are discussed

The short-channel effect in fully depleted silicon-on-insulator
MOSFETs has been studied by a two-dimensional analytical model and by
computer simulation. The calculated values agree well with the
simulation results. It is found that the vertical field through the
depleted film strongly influences the lateral field across the source
and drain regions. The short-channel effect can be significantly reduced
by decreasing the silicon film thickness

A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

Simple but reasonably accurate equations are derived, which describe MOS transistor operation in the weak inversion region near tum-on. These equations are used to find the transfer characteristics of complementary MOS (CMOS) inverters. The smallest supply voltage at which these circuits will function is approximately 8 kT/q. A boron ion implantation is used for adjusting MOST tum-on voltage for low-voltage circuits. Copyright © 1972 by The Institute of Electrical and Electronics Engineers, Inc.

An overall view on low-voltage device and circuit design is
presented, beginning with a discussion of the low-voltage limit.
Low-voltage device design is then described. Low-voltage CMOS and BiCMOS
logic circuits are discussed. Circuit techniques for the low-voltage
DRAMs and SRAMs are presented. The low-voltage analog devices and
circuits are considered. The future direction of the low-voltage and
low-power ULSIs is discussed by comparing the switching energy of
electronic devices and brain cells

VLSI limitations from drain-induced barrier lower-ing Short channel MOST thresh-old voltage model

- R R Troutmani
- K N Ratnakumar
- James D Meindl

R. R. Troutman, " VLSI limitations from drain-induced barrier lower-ing,'' IEEE Trans. Electron Devices, vol. ED-26, no. 4, Apr. 1979. [I21 K. N. Ratnakumar and James D. Meindl, " Short channel MOST thresh-old voltage model, " IEEE J. Solid-State Circuits, vol. SC-17 p. 937, Oct. 1982.

VLSI limitations from drain-induced barrier lowering

- R R Troutman