Available via license: CC BY-NC-ND 4.0
Content may be subject to copyright.
Available online at www.sciencedirect.com
2212-8271 © 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of the scientific committee of 48th CIRP Conference on MANUFACTURING SYSTEMS - CIRP CMS 2015
doi: 10.1016/j.procir.2015.12.043
Procedia CIRP 41 ( 2016 ) 870 – 874
ScienceDirect
48th CIRP Conference on MANUFACTURING SYSTEMS - CIRP CMS 2015
Optimization method for double-sided polishing process
based on kinematical analysis
Urara Satake
a,
*, Toshiyuki Enomoto
a
, Keitaro Fujii
a
, Kenji Hirose
a
a
Department of Mechanical Engineering, Graduate School of Engineering, Osaka University, 2-1 Yamada-oka, Suita, Osaka 565-0871, Japan
* Corresponding author. Tel.: +81-6-6879-7287; fax: +81-6-6879-7287. E-mail address: sata
ke@cape.mech.eng.osaka-u.ac.jp
Abstract
To achieve high surface flatness of silicon wafer in double-sided polishing (DSP) process, kinematical model of DSP process utilizing accurate
friction coefficient between wafer and polishing pad was investigated. On the basis of the proposed analytical model, optimization method of a
set of rotation conditions of upper/lower platens and inner/outer gears was developed. Optimizations for two types of DSP processes were
performed as case study and those results confirmed that the developed optimization method was effective in obtaining the appropriate rotation
conditions for achieving high surface flatness of wafer while decreasing the motor load of platens and gears.
© 2015 The Authors. Published by Elsevier B.V.
Peer-review under responsibility of the Scientific Committee of 48th CIRP Conference on MANUFACTURING SYSTEMS - CIRP CMS 2015.
Keywords: Polishing ; Flatness ; Silicon wafer
1. Introduction
In the semiconductor industry, there is a constant demand
for decrease in the design rule, that is, shrinkage of the line
geometries for improving the integration density of the
devices. According to the latest edition of the International
Technology Roadmap for Semiconductors (ITRS), DRAM
half pitch, which is the common measure of the technology
generation of the devices, is expected to be reduced to 14 nm
by 2021 [1]. To meet the above strict requirements, silicon
wafers as the substrates for most devices are demanded to
have highly flat surface, because both the resolution and the
throughput of lithography process are strongly affected by the
wafer flatness. In concrete, GBIR (Global Backside Ideal
Focal Plane Range) defined as the total thickness variation
across the entire wafer is required to be less than 100 nm for
300 mm wafers in current manufacturing process.
The surface flatness of wafer is basically determined in
polishing process as the final stage of the wafer
manufacturing. The polishing process of wafer typically
consists of two processes, namely, double-sided polishing
(DSP, Fig. 1) process [2] and single-sided polishing (SSP)
process. DSP process is extremely effective in achieving
highly flat and smooth surface of thin plate-shaped workpiece
economically.
In DSP process of wafer, the obtained wafer flatness is
depending on the polishing conditions such as rotational
speed of platens and gears, slurry flow pattern on polishing
pads, and temperature of platens and supplied slurry. In
particular, rotation conditions of platens and gears are well
known to have a large influence on the wafer flatness. The
obtained wafer flatness, however, cannot be estimated
accurately from the rotation conditions, which leads to large
difficulties in setting the appropriate conditions. The rotation
conditions, in fact, are determined by repeating try and error
in manufacturing process, resulting in the serious
deterioration of reproducibility and productivity.
To address the problem above, several theoretical methods
to determine the rotation conditions have been already
proposed [3,4]. However those methods have a serious
problem: the friction coefficient value between wafer and
polishing pad, which is one of the most critical parameters for
motion of the wafer against the pad, is extremely roughly
estimated due to difficulties in the actual measurement and, as
a result, cannot bring the effective rotation conditions in
practical process.
In this study, we investigated two types of procedures to
identify the wafer-pad friction coefficient, and then developed
© 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer
-review under responsibility of the scientifi c committee of 48th CIRP Conference on MANUFACTURING SYSTEMS - CIRP CMS 2015
871
Urara Satake et al. / Procedia CIRP 41 ( 2016 ) 870 – 874
the optimization method of rotation conditions utilizing the
identified friction coefficient.
2. Optimization method of rotation conditions for DSP
process
2.1. Kinematical model of DSP process
DSP
machine consists of an upper plate, a lower plate, an
inner gear, and an outer gear (Fig. 1). The rotation conditions
of them can be controlled independently. In DSP process,
workpieces are not fixed on chuck jig unlike other machining
process such as cutting process, grinding process and SSP
process. Each wafer, loosely held by a carrier making sun-
and-planet motion, rotates freely in a carrier hole while
revolving on the polishing pads.
Basically, removal distribution on wafer is proportional to
the sliding distance distribution against polishing pads.
Therefore flatness of the polished wafer, that is, uniformity of
the removal distribution on wafer is determined by the wafer
motion on polishing pads. The wafer motion, however,
cannot be controlled by the setting of rotation conditions as
desired. The revolution speed of wafer can be exactly
calculated from the rotation speed of gears. However, as for
the rotation speed of wafer, it is difficult to estimate the
accurate value from the rotation conditions. This leads to
large difficulties in determining the appropriate rotation
conditions.
Then we modeled the DSP process based on the
kinematical analysis considering the wafer rotation in a carrier
hole. We calculated the rotation speed of wafer assuming that
the wafer rotated in a carrier hole by the frictional force
against the pads, and then applied the calculated results to the
kinematical model.
2.2. Optimization method of rot
ation conditions
To determine the rotation conditions for achieving high
wafer flatness, we investigated the optimization method based
on the analytical model described in section 2.1. The
optimization procedure is as follows:
• Relative velocity of a certain position on wafer agai
nst
polishing pad is calculated as the difference between the
wafer speed and the pad speed on the position.
• Sliding distance of the position is
obtained by calculating
time differentiation of the relative velocity.
• By adopting the above calculation for all position on wafer,
sliding distance
distribution on wafer, that is, wafer
removal distribution is obtained.
• In almost the same way as described above, sliding
distance
distribution on pad, that is, pad wear distribution
is obtained. Uneven pad wear has a bad influence on the
wafer flatness.
• Objective functions for flatness of wafer and uneven wear
of
pads are calculated respectively as the difference
between the maximum value and minimum value of sliding
distance.
• The multi-objective function as the sum of the three
weighted
objective functions for wafer, upper pad, and
lower pad is calculated.
• The optimum solution is obtained
by minimizing the multi-
objective function using genetic algorithm. To achieve the
sufficient removal rate in the optimized condition, penalty
function about the total value of sliding distance through
the polishing time is set.
3. Optimization for DSP process of small-diameter wafers
3.
1. Influence of wafer rotation in carrier hole
on wafer
flatness
In DSP process, surface flatness of wafer is determined by
the relative motion of wafer against polishing pad. In
particular, rotation speed of wafer in a carrier hole is a
dominant factor for the wafer flatness.
In case that wafer rotation is too low (Fig. 2(a)), distance
between the center of polishing pad and a certain point on
wafer is almost constant during polishing. Due to the
difference in the pad speed, removal at the point 'a1' far from
the pad center is larger than that at the point 'a2' close to the
pad center. As a result, the wafer becomes tapered shape. On
the other hand, in case that wafer rotation is too high (Fig.
2(b)), wafer speed at the certain point is strongly depending
on the distance from the wafer center to the point. Due to this
large difference in wafer speed, removal at the point 'b1' far
from the wafer center is larger than that at the point 'b2' close
to the wafer center. As a result, wafer center gets thicker.
Fig. 1. Schematic of double-sided polishing process.
(a) Low wafer rotation (b) High wafer rotation
Fig. 2. Influence of wafer rotation on wafer flatness.
Lower platen
Inner gear
Upper platen
Outer gear
Polishing pad
Wafer
Carrier
Carrier hole
a1
Center of polishing pad
a1
a2
a2
: Higher pad speed
: Lower pad speed
b1
Center of wafer
b1
b2
b2
: Higher wafer speed
: Lower wafer speed
872 Urara Satake et al. / Procedia CIRP 41 ( 2016 ) 870 – 874
3.2. Identification of wafer-pad friction coefficient
Wafer rotation in a carrier hole is caused by the frictional
force between the wafer and the polishing pad. The wafer-pad
friction coefficient, therefore, significantly affects the wafer
rotation. Namely, the friction coefficient must be identified
with high accuracy for modeling of DSP process. Then
several methods to identify the friction coefficient have been
proposed and conducted for SSP process [5], where the
frictional force is actually measured during polishing.
However the actual measurement in DSP process is highly
difficult.
Then we investigated the identification procedure of wafer-
pad friction coefficient under the DSP conditions by actual
measurement using the SSP setup. The friction coefficient
depends on the relative velocity and the range of the velocity
in DSP of small-diameter wafer is overlapped with that in
SSP. In general, the relation between the relative velocity and
the friction coefficient is strongly affected by the lubricating
condition on the contact surface. In DSP process, the
lubricating condition between wafer and pad is extremely
different from each other on the upper side of wafer and the
lower side of wafer. On the upper contact surface between
upper side of wafer and upper pad, slurry is directly dropped
on several local points on wafer. In contrast, on the lower
contact surface between lower side of wafer and lower pad,
the whole surface of pad is uniformly covered with slurry.
Then we measured the frictional force between wafer and pad
using SSP setup (Fig. 3) while simulating the above two types
of lubricating conditions in DSP process.
The measuring setup is shown in Fig. 4, and the measuring
conditions are listed in Table 1. Polishing pressure, relative
velocity between wafer and pad, and supply rate of slurry
were set to correspond to the analysis conditions of DSP
process, which will be described later. For simulating the
lubricating condition of the upper contact surface, slurry was
directly dropped on the pad immediately before the wafer
passed. In contrast, for simulating the lubricating condition of
the lower contact surface, the pad surface was kept uniformly
covered with slurry. Fig. 5 shows the relation between the
relative velocity and the friction coefficient identified from
the measured frictional force. The identified results indicate
that the upper contact surface and the lower contact surface
are largely different from each other in the relation between
the relative velocity and the friction coefficient. On the upper
contact surface, the friction coefficient increases gradually
with the relative velocity. On the other hand, the friction
coefficient is constant regardless of the relative velocity on
the lower contact surface.
3.3. Optimization of rotation conditions
App
lying the identified friction coefficient to the analytical
model, optimization of rotation conditions was performed for
DSP process shown in Table 2. Table 3 lists conventional and
optimized conditions. The conventional condition is
commonly used in manufacturing processes. The calculated
removal distribution on wafer and GBIR value for each
condition are shown in Fig. 6. The sliding distance was
converted into a removal based on the typical removal rate.
GBIR was calculated assuming the completely flat surface of
wafer before polishing, that is, defined as the maximum
difference of removal across the whole wafer. Fig. 7 shows
the calculated wear distributions on upper and lower polishing
pads for each condition.
As shown in Figs. 6 and 7, the optimized condition
improves the wafer flatness compared with the conventional
condition. However, as for the pad wear, the large wear
Fig. 3. Schematic of single-sided polishing.
Fig. 4. Schematic of measuring setup of frictional force.
Table 1. Frictional force measuring conditions.
Fig. 5. Relation between relative velocity and friction coefficient.
Weight
Slurry nozzle
Polishing pad
Wafer
Platen
Polishing pad
Load cell
Wafer
Weight
Slurry nozzle
Polishing machine Single-sided polishing machine
Lapmaster SFT Corp., LP-15F
Polishing pressure 13.8 kPa
Workpiece
Diameter
Rotation speed
Silicon wafer (mirror finished)
5''
0 rpm
Polishing pad
Diameter
Rotation speed
Polyurethane foam pad
Nitta Haas Inc., MH-S15A
420 mm
5, 10, 20, 30, 40, 50, 60, 70 rpm
Slurry
Concentration
Supply rate
Colloidal silica
Fujimi Inc., GLANZOX-1302
1 wt%
120 mL/min
0
0.1
0.
2
0.3
0.4
0 100 200 300 400 500 600 700 800
Friction coefficient
Relative velocity mm/sec
◆ Upper contact surface ◆ Lower contact surface
873
Urara Satake et al. / Procedia CIRP 41 ( 2016 ) 870 – 874
occurs at the central part in radial direction of pad in both
conditions. This large wear is caused by the most frequent
pass of wafer and therefore cannot be improved unless the
initial setting position of wafer is changed.
4. Optimization for DSP process of ultra-large-diameter
450 mm
wafers
4.1. Identification of wafer-pad fri
ction coefficient
Recently, in addition to high wafer flatness, wafer size
transition from current 300 mm to 450 mm is required, which
is extremely effective in manufacturing cost reduction.
According to ITRS, the mass production of 450 mm wafers is
expected to be started by 2018 [1], and some wafer makers
have already started the trial and mass production. The larger
the wafer diameter is, the more difficult the achievement of
wafer flatness and the suppression of uneven pad wear are in
general. Moreover, problem about overload of DSP machine
motors was pointed out due to larger machine size and larger
polishing force for DSP process of 450 mm wafers. The motor
load is depending on the rotation conditions of platens and
gears. In DSP process of 450 mm wafers, therefore the
conditions must be determined considering not only wafer
flatness and uneven pad wear but also motor load. Then we
calculated load torque on motors of platens and gears, and
improved the optimization method described in section 2.2 by
additionally considering the objective function for motor load.
The relative velocity in DSP process of 450 mm wafers
changes over a very wide range and then is out of range in the
velocity in typical SSP setup, brought that the identification
procedure proposed in section 3.2 cannot be adopted. Then we
investigated the identification procedure utilizing the detected
and calculated motor current waveforms of platens and gears.
The motor current waveforms can be both experimentally
observed in DSP machine and analytically obtained using the
calculated load torque value. In the procedure, the value
which makes identical the analytical current waveform to the
experimental one is identified as the friction coefficient.
4.2. Optimization of rotation conditions
The proposed identification procedure
was applied to the
DSP process of 450 mm wafers listed in Table 4. Fig. 8 shows
the comparison between the observed motor current
waveform during DSP experiment and the analytical one
calculated using the identified friction coefficient. In this case
study, we used the motor current waveform of lower platen.
Applying the identified friction coefficient, the rotation
conditions were optimized for improving wafer flatness,
suppressing uneven pad wear, and decreasing motor load.
Table 5 lists conventional and optimized conditions. The
conventional condition is commonly used in the
manufacturing process. The calculated removal distribution
on wafer and GBIR value for each condition are shown in Fig.
9. Fig. 10 shows the calculated wear distributions on upper
and lower polishing pads for each condition. The calculated
results indicate that the optimized condition improves the
wafer flatness while suppressing the uneven pad wear at
almost the same degree as that in conventional condition.
The calculated results of change in the motor load torque
with polishing time are shown in Fig. 11. The optimized
condition extremely decreases both the average value and the
variation value of the load torque on gears compared with the
conventional condition (Fig. 11(a),(b)). However, as for the
load torque on platens, the average value is not almost
decreased while the variation value is extremely decreased
compared with that in the conventional condition (Fig.
11(c),(d)). The small average values of the motor load torque
of platens are achieved by reducing the total value of sliding
distance, that is, the total removal amount through the
polishing. Therefore decreasing the average values of the
motor load torque of platens cannot be achieved in any
rotation conditions with the sufficient removal rate.
Table 2. Analysis conditions for DSP process of small-diameter wafers.
Table 3. Rotation conditions of platens and gears.
(a) Conventional condition (b) Optimized condition
Fig. 6. Calculated removal distribution on wafer.
(a) Upper polishing pad (b) Lower polishing pad
Fig. 7. Calculated wear distribution on polishing pads.
Diameter of carrier
Diameter of wafer
116 mm
125 mm
Number of carriers per batch
Number of wafers per carrier
5
1
Polishing pressure 13.8 kPa
Conventional Optimized
Upper platen rpm -10.2 -10.2
Lower platen rpm 30.0 30.0
Inner gear rpm 3.0 -10.5
Outer gear rpm 10.2 10.2
GBIR : 99 nm GBIR : 90 nm
4.14
4.06
3.98
Removal ȝm
-60
0
60
0
60
-6
0
4.14
4.06
3.98
Removal ȝm
-60
0
60
0
60
-60
0
100
200
300
0
100 200 300 400
Sliding distance m
Position of polishing pad mm
0
100
200
300
0
100 200 300 400
Sliding distance m
Position of polishing pad mm
−
Conventional
−
Optimized
−
Conventional
−
Optimized
874 Urara Satake et al. / Procedia CIRP 41 ( 2016 ) 870 – 874
5. Conclusion
To improve wafer flatness in double-sided polishing
process, optimization method of rotation conditions of platens
and gears utilizing the identified wafer-polishing pad friction
coefficient was developed based on the kinematical analysis.
Case study
results of optimization confirmed that the
developed method was effective in obtaining the rotation
conditions for achieving high wafer flatness while suppressing
overload of motor on DSP machine.
References
[1] International technology roadmap for semiconductors committee. The
international technology roadmap for semiconductors 2013 Edition -Front
End Processes.
[2] Uhlmann E, Ardelt T. Annals of the CIRP; 1999;48:1. p. 281-284.
[3] Nakagawa Y. Journal of the Japan Society for Precision Engineering;
2006;72:5. p. 641-646.
[4] Hirose K, Enomoto T. Proceedings of 23rd Annual Meeting of the
American Society for Precision Engineering; 2008. p. 396-399.
[5] Takasaki R, Enomoto T, Tominaga S. Journal of the Japan Society for
Abrasive Technology; 2009; 53:8. p. 508-513.
Table 4. Analysis conditions for DSP process of 450 mm wafers.
(a) Experimental result (b) Analytical result
Fig. 8. Motor current waveform of lower platen.
Table 5. Rotation conditions of platens and gears.
(a) Conventional condition (b) Optimized condition
Fig. 9. Calculated removal distribution on wafer.
(a) Upper polishing pad (b) Lower polishing pad
Fig. 10. Calculated wear distribution on polishing pads.
Diameter of carrier
Diameter of wafer
811 mm
450 mm
Number of carriers per batch
Number of wafers per carrier
5
1
Polishing pressure 11.1 kPa
Conventional Optimized
Upper platen rpm -9.1 -10.0
Lower platen rpm 25.3 25.0
Inner gear rpm 7.1 4.0
Outer gear rpm 8.1 10.0
-225
0
225
0
225
-22
5
12.5
12.0
11.5
Removal ȝm
-225
0
225
0
225
-2
25
12.5
12.0
11.5
Removal ȝm
GBIR : 570 nm GBIR : 300 nm
Sliding distance m
Position of polishing pad mm
0 724 1100
1000
800
600
400
200
0
Sliding distance m
Position of polishing pad mm
0 724 1100
1000
800
600
400
200
0
−
Conventional
−
Optimized
−
Conventional
−
Optimized
(a) Inner gear
(b) Outer gear
(c) Upper platen
(d) Lower platen
Fig. 11. Calculated motor load torque.
35
37
39
41
43
45
1500 1550 1600
Current value A
Polising time sec
35
37
39
41
43
45
050100
Current value A
Polishing time sec
Amplitude : 2 ~ 3 A
Avera
g
e : 40 A
Amplitude : 3 ~ 4 A
Avera
g
e : 39 A
Load torque N䞉m
3400
3300
3200
3100
0
0 20 40 60 80 100
Polishing time sec
Variation Average
Conventional N・m 199 3244
Optimized N・m 143 3168
−
Conventional
−
Optimized
3300
3100
2900
0
Load torque N䞉m
020406080100
Polishing time sec
Variation Average
Conventional N・m 459 3017
Optimized N・m 155 3060
−
Conventional
−
Optimized
300
200
100
0
-100
Load torque N䞉m
020406080100
Polishing time sec
Variation Average
Conventional N・m 227 102
Optimized N・m 35 27
−
Conventional
−
Optimized
400
200
0
-200
0
20 40 60 80 100
Polishing time sec
Load torque N䞉m
Variation Average
Conventional N・m 438 125
Optimized N・m 7 69
−
Conventional
−
Optimized
