ArticlePDF Available

S-Box using AES Technique

Authors:
Anusuya Baby at United Arab Emirates University
Anusuya Baby
Christo Ananth at Samarkand State University named after Sharof Rashidov
Christo Ananth
Download full-text PDF
Read full-text
Download citation

Figures

Figures - uploaded by Christo Ananth
Author content
All figure content in this area was uploaded by Christo Ananth
Content may be subject to copyright.
Content uploaded by Christo Ananth
Author content
All content in this area was uploaded by Christo Ananth on Oct 30, 2017
Content may be subject to copyright.
S-Box using AES Technique
H. Anusuya Baby1, Christo Ananth2
1(PG Scholar/ECE, Francis Xavier Engineering College/ Anna University , India)
2(Assistant professor/ECE, Francis Xavier Engineering College/ Anna University , India)
Abstract— To design a substitution box (S-BOX) using both
encryption and decryption. From that, the proposed system can
achieve a higher throughput and higher energy efficiency. The
S-BOX is designed by using Advanced Encryption Standard
(AES). The AES is a symmetric key standard for encryption and
decryption of blocks of data. In encryption, the AES accepts a
plaintext input, which is limited to 128 bits, and a key that can be
specified to be 128 bits to generate the Cipher text. In decryption,
the cipher text is converted to original one. By using this AES
technique the original text is highly secured and the information
is not broken by the intruder. From that, the design of S-BOX is
used to protect the message and also achieve a high throughput ,
high energy efficiency and occupy less area.
Keywords— Advanced Encryption Standard (AES),
Substitution Byte, Cryptography.
I.INTRODUCTION
Cryptography is a technique which is used to protect the
information. In 1997 the National Institute of Standards and
Technology (NIST), a branch of the US government, started
a process to identify a replacement for the Data Encryption
Standard (DES). It was generally recognized that DES was
not secure because of advances in computer processing
power. The goal of NIST was to define a replacement for
DES that could be used for non-military information security
applications by US government agencies. Of course, it was
recognized that commercial and other non-government users
would benefit from the work of NIST and that the work
would be generally adopted as a commercial standard. The
NIST invited cryptography and data security specialists from
around the world to participate in the discussion and
selection process. Five encryption algorithms were adopted
for study. Through a process of consensus the encryption
algorithm proposed by the Belgium cryptographers Joan
Daeman and Vincent Rijmen was selected. Prior to selection
Daeman and Rijmen used the name Rijndael(derived from
their names) for the algorithm. After adoption the encryption
algorithm was given the name Advanced Encryption
Standard (AES) which is in common use today.
In 2001, the National Institute of standards and
Technology (NIST) found the Advanced Encryption
Standard (AES) Technique. It can be implemented in
hardware. There are a lot of disadvantages in DES
Technique. It is insecure and the message is easily broken by
the intruder. AES Technique has been widely used in a
variety of applications such as secure communication
systems and high throughput data servers.
.
The AES encryption algorithm is a block cipher that uses
an encryption key and a several rounds of encryption. A
cipher key is an encryption algorithm that works on a single
block of data at a time. In the case of standard encryption
technique the data is 128 bits, or 16 bytes, in length. The term
―rounds‖ refers to the way in which the encryption algorithm
mixes the data re-encrypting it ten to fourteen times
depending on the length of the key.
AES encryption uses a single key as a part of the
encryption process. The key can be 128 bits (16 bytes), 192
bits (24 bytes) or 256 bits (32 bytes) in length. The term
128-bit encryption refers to the use of a 128-bit encryption
key. With AES both the encryption and the decryption are
performed using the same key. This is called a symmetric
encryption algorithm. Encryption algorithm uses two
different keys that is public and a private key. Both are
called asymmetric encryption algorithm key technique. An
encryption key is simply a binary string of data used in the
encryption process. Because the same encryption key is used
to encrypt and decrypt data, it is important to keep the
encryption key as a secret and to use the keys that are hard to
guess. Some keys are generated by software used for this
specific task. Another method is to derive a key from a pass
phrase. Good encryption systems never use a pass phrase
alone as an encryption key.
The previous techniques used in the encryption are
parallel mix column and one target one process. The parallel
mix column occupies more area and delay. The one term
process also occupies more area and delay. So the complex
parallelism is introduced.. By using this technique , a higher
energy efficiency is achieved and also delay reduction is
possible. This technique is applied for so many applications
like military purpose, computer password and so on.
The reminder of this paper is organized as follows: section
2 explains the basic types of encryption. The encryption
types involve the brief explanation about four techniques
which we have given in the abstract. Section 3 presents the
complex parallelism. The section also explains the cyclic
loop of this mechanism. Section 4 discuss the simulation
results of one target one process, parallel mix column and
Complex parallelism.
II.TECHNIQUES INVOLVE IN ENCRYPTION
AES is a symmetric encryption algorithm, and it takes
a 128-bit data as a input and performs several rounds of
transformations to generate output cipher text. It is a
computer security standard issued by NIST for protecting the
electronic data. The basic processing unit used in this AES
algorithm is byte. AES is used to encrypt/decrypt data
285
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
blocks of 128-bits and it can be implemented in both
hardware and software. AES acts as a block cipher which
operates on fixed length group of bits of data. AES is a
stream cipher which means the plain text bits are encrypted
one and set of transformations have been applied to the bits.
It may vary during encryption process. The plain text input
and cipher output are the blocks of 128 bits. The number of
rounds depend on key size. Each 128-bit is processed in a
permutation and rotation operation. There are different
techniques involved in this encryption.
A. Substitution Byte:
It is a non- linear substitution byte. Each Byte is replaced
by another byte. This substitution Byte uses S-BOX for
generating the cipher text. This S-box involves two process.
First one is used to take the multiplicative inverse of finite
field of the matrix (i.e input data). Secondly, the Affine
Transformation is applied to the output of multiplicative
inverse. Area reduction is possible in this finite field and
finite field is used to create a compact field AES
implementation. In new technology, the S-Box can be
obtained from its truth table by using two level logic such as
sum of products and product of sum. If the above mentioned
technology is used , the primitive logic cells can be reduced
and also cell size can be optimized using synthesis tool. The
S- Box is computed from inverse of input to the original
input. The example of Affine Transformation is given by
Consider an example, 4X4 matrix is a input text and [s1
s2 s3 s4] is the inverse of the input . the remaining one [ 0
1 1 0 ] is a cipher key. The output is a [ z1 z2 z3 z4 ]. The
input is multiplied with inverse of input with a cipher key and
the output is obtained. The inverse input is the multiplicative
inverse of the given input matrix. The example of
Substitution Byte is given below.
Example of Substitution Byte input
Operation of Substitution Byte
B. Shift Row:
The technique used in this model is the transformation of
the row. Consider a 4x4 matrix, the first row of the matrix
remains unchanged. The second row , first bit is shifted to the
last one. Then the last one is shifted to the third place. Finally
the third row and forth row is finally rotated. The message is
shuffled. In otherwords, The row transformation can be
expressed as a reconstruction of the matrix using an key
expression for each element. The row expressions calculate
circular transformation .The example of shift row is given
below.
Example of Shift Row input
Operation of Shift Row
C. Mix Column:
During this process, the matrix of the input column is
shuffled. From that, the message is unbroken. It is similar to
Substitution Byte. It uses the polynomial function. It is also
based on finite field multiplication. The Mix column is based
286
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
on the multiplication of two matrices and xor operation of
both input and cipher key.
Example of Mix Column input
Operation of Mix Column
D. Add Round Key:
The sender sends a message to the receiver using a
password (i.e key). The key is known by both sender and
receiver. The key is added to the input ( which is in the form
of cipher text ). The message is not hackable by any other
intruders and also the information is more shuffled and
secure.
III. ANALYSIS OF SYSTEM TECHNIQUES
The different types of technique involve in this encryption
and decryption. There are three techniques
A. One Target and One Process:
The input is fed to the add round key. so the key is
mixed with input (i.e cipher text). Then the output of the add
round key is shuffled with sub byte, shift row, mix column
and add round key. This process is repeated upto nine times.
Then the ouput is processed with key elongation process.
The output of key elongation is send to the final stage add
round key. Finally the cipher text is generated from the plain
text by using this OTOP technique.
B. Parallel Mix Columns:
The OTOP model is easily hackable by intruder. So the
efficiency of OTOP model is small. This process is similar
to the OTOP model. The input is fed to the add round key (i.e
cipher text). The output is fed to the sub byte and shift row.
The output of the shift row is added to the parallelizing mix
column for shuffling the message. Then the output is added
to the add round key. The process is repeated for nine times.
The key elongation process is applied to the final stage
output. The efficiency of parallel mix column is much higher
than OTOP model. The area reduction is possible in this
parallel mix column.
C. Complex Parallelism:
The input is fed to the four main blocks that is replacement
bye, row transformation, shuffle the column and xor
operation with key. The process is simulated upto nine times.
The process is optimized with complex parallelism and the
message is secure with cipher keys.
Fig 1: Complex Parallelism
First the input is fed to the xor operation with key. The
process involves in this stage is inserting a key to the input
data. Then we have to send the data to replacement byte.
Parallelizing the replacement byte is used to secure the
message. The message is much more shuffled by combining
the replacement byte. Then the next one is row
transformation. This is used to transfer or shift the data. Then
the next step is shuffle the column. It is used to shuffle the
input with key. this is done by polynomial function. Then the
last one is xor operation with key. The input is xored with
key. The process is repeated upto nine times for shuffling the
message. Finally the original text is covered by cipher key
and the output of the data is cipher text(only with cipher
keys). The cipher text information is unbroken by any other
intruder. Finally the cipher text text input is given to the
reverse process of complex parallelism. The original
message is received by the S-box. Thus The information is
secured by using complex parallelism.
IV RESULTS AND DISCUSSION
The information is encrypted by using complex
parallelism. The simulation results of OTOP model and
Parallel Mix Column are discussed below. Finally the
encrypted output of complex parallelism is also given below.
A. One Target One Process:
The input is a 128-bit. The plain text is given to the OTOP
encryption key. The cipher text is generated by using cipher
287
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
keys. The OTOP model involves the process of SubBytes,
Shift Row, Mix Column and Add Round key. All the above
process is used to perform the message shuffling purpose.
The permutation and rotation process are done by using the
key elongation process. The message is secure and the
information is shuffled for security purposes. The number of
LUTs are reduced by 0.8%. Then the number of occupied
slices are decreased by 0.9%. The gate count is increased in
this OTOP model.
Fig 2: Compilation of OTOP model
The figure 2 shows the compilation of OTOP model. The
area utilization is 81% in this OTOP model. The delay is
calculated in the comparison table for area efficiency.
B.Parallel Mix Column:
The input is a 128-bit. The plain text is given to the
Parallel Mix Column encryption key. The cipher text is
generated by using cipher keys. The Parallel Mix Column
model involves the process of SubBytes, Shift Row, Mix
Column and Add Round key. All the above process is used to
perform the cyclic rotation for rotating the input keys . The
key elongation process is done by using key rotation. The
message is safe and the information is shuffled for security
purposes. The number of LUTs are reduced by 0.9%. Then
the number of occupied slices are decreased by 0.9%. The
gate count is increased in this Parallel Mix Column model.
Fig 3: Compilation of Parallel Mix Column
The figure 3 shows the compilation of Mix Column. The
area utilization is 96% in this Parallel Mix Column. The path
route delay is calculated
F.Complex Parallelism:
Fig 4: Compilation of S-Box
The design of S-Box is used to the protect the message.
The figure 4 shows the compilation of substitution byte.
The above figure shows the shuffling of message and also
elongating the key.
288
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
Fig 5: Encrypted data of Complex Parallelism
The figure 5 shows the proces of complex parallelism
encryption. It will show the complex parallelism process.
The process involves the operation of one task one
processor, Parallel Mix columns and complex parallelism.
Fig 7: Decrypted data of Complex Parallelism
It implements in 167 processor using complex parallelism
technique. The process is the combination of various
techniques like Substitution Byte, Shift Row Mix Column
and Add Round Key. The message is secure and the delay is
reduced by other methods. The figure 6 and 7 show the
compilation of complex parallelism. The delay of complex
parallelism is small compared to other techniques.
Fig 8: Compilation of Complex Parallelism
The above simulation results discuss the detailed
description of three models. The comparison table of area
and delay are discussed in the below section. The table 1
discusses the comparison of area with LUTs and route path.
The table 2 discusses the comparison of delay with path and
route delay.
TABLE 1: Comparison of Area
Encryption Name
LUT
Route Path
OTOP model
21658
11
Parallel Mix
Column
21658
11
Complex
Parallelism
21634
5
The OTOP model occupies more LUT in the hardware
implementation. The number of gates in the OTOP model is
very high .The parallel mix column occupies less LUT
compare to OTOP model and high compare to complex
parallelism. The number of gates occupied in the hardware is
same as the OTOP model. The complex parallelism
technique occupies less LUTs for hardware implementation.
The number of paths in the complex parallelism are less
289
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
compared to the both previous model. The path delay and
route delay is efficient in the complex parallelism compared
to the OTOP model and Parallel Mix Column.
TABLE 2: Comparison of Delay
Delay
Gate Delay
Path Delay
307.909ns
105.862ns
202.047ns
232.742ns
116.830ns
115.912ns
232.245ns
116.683ns
115.562ns
VI. CONCLUSION
In this brief, cryptography AES technique is presented to
protect the information. To increase the efficiency, the
complex parallelism technique is used to involve the
processing of Substitution Byte, Shift Row, Mix Column and
Add Round Key. Using S- Box complex parallelism, the
original text is converted into cipher text. From that, we have
achieved a 96% energy efficiency in Complex Parallelism
Encryption technique and recovering the delay 232 ns. The
complex parallelism that merge with parallel mix column and
the one task one processor techniques are used. In future,
Complex Parallelism single loop technique is used for
recovering the original message.
VII. REFERENCES
[1] E. Kasper and P. Schwabe, ―Faster and Timing-Attack Resistant
AES-GCM,‖ Proc. 11th Int’l Workshop Cryptographic Hardware and
Embedded Systems (CHES ’09), pp. 1-17, 2009
[2]Agarwal.A, Ander M.A, Gueron .S, Hsu. S.K, Kaul. H, Kounavis .M,
S.K. Mathew, F. Sheikh, R.K. Krishnamurthy, ―53 gbps Native GF(2^4)
Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection
in 45 nm High-Performance Microprocessors,‖ IEEE J. Solid-State
Circuits, vol. 46, no. 4, pp. 767-776, Apr. 2011.
[3].Bernstein.D and P. Schwabe, ―New AES Software Speed Records,‖
Proc. INDOCRYPT ’08: Ninth Int’l Conf. Cryptology in India: Progress in
Cryptology, pp. 322-336, 2008.
[4].Biham.E, ―A Fast New DES Implementation in Software,‖ Proc. Fourth
Int’l Workshop Fast Software Encryption, pp. 260-272, 1997.
[4].Borkar.S, ―Thousand Core Chips: A Technology Perspective,‖Proc.
44th Ann. Design Automation Conf., pp. 746-749, 2007.
[5].Cheng .W, D. Truong, T. Mohsenin, Z. Yu, T. Jacobson, G. Landge, M.
Meeuwsen, C. Watnik, P. Mejia, A. Tran, J. Webb, E. Work, Z. Xiao, and
B. Baas, ―A 167-Processor 65 nm Computational Platform with
Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency
Scaling,‖ Proc. IEEE Symp. VLSI Circuits, June 2008.
[6].Cheng W.H, D.N. Truong, , T. Mohsenin, Z. Yu, A.T. Jacobson, G.
Landge, M.J.Meeuwsen, A.T. Tran, Z. Xiao, E.W. Work, J.W. Webb, P.
Mejia, and B.M. Baas, ―A 167-Processor ComputationalPlatform in 65 nm
CMOS,‖ IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1130-1144, Apr.
2009.
[7].Chen Y.C, C.-J. Chang, C.-W. Huang, K.-H. Chang, and C.-C. Hsieh,
―High Throughput 32-Bit AES Implementation in FPGA,‖ Proc. IEEE Asia
Pacific Conf. Circuits and Systems, pp. 1806-1809, Nov. 2008.
[8].Gomez –Pulido. J, Granado-Criado.J, M. Vega-Rodriguez and J.
Sanchez-Perez, ―A New Methodology to Implement the AES Algorithm
Using Partial and Dynamic Reconfiguration,‖ Integration, the VLSI J., vol.
43, no. 1, pp. 72-80, 2010.
[9].Guo.Z, S. Qu, G. Shou, Y. Hu and Z. Qian, ―High Throughput,
Pipelined Implementation of AES on FPGA,‖ Proc.Int’l Symp. Information
Eng. and Electronic Commerce, pp. 542-545, May 2009.
[10].Hodjat.A and Verbauwhede.I, ―Area-Throughput Trade-Offs for Fully
Pipelined 30 to 70 Gbits/s AES Processors,‖ IEEE Trans. Computers, vol.
55, no. 4, pp. 366-372, Apr. 2006.
[11].Hodjat.A and Verbauwhede.I, ―A 21.54 gbits/s Fully Pipelined AES
Processor on FPGA,‖ Proc. IEEE 12th Ann. Symp. Field-Programmable
Custom Computing Machines, pp. 308- 309, Apr. 2004.
[12].Kuo.H, I. Verbauwhede and P. Schaumont, ―Design and Performance
Testing of a 2.29 gb/s Rijndael Processor,‖ IEEE J. Solid-State Circuits,
vol. 38, no. 3, pp. 569-572, Mar. 2003.
290
Vol. 3 Issue 3, March - 2014
International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
www.ijert.orgIJERTV3IS030404
... The ATLAS dataset or PH2 dataset pictures are considered for investigation in the majority of the papers. [61] proposed a system which can achieve a higher throughput and higher energy efficiency. The S-BOX is designed by using Advanced Encryption Standard (AES). ...
Call for Papers - Journal of Electrical Systems (JES), E-ISSN: 1112-5209, indexed in Scopus & Web of Science
Preprint
Full-text available
  • May 2024
At the forefront of technological innovation and scholarly discourse, the Journal of Electrical Systems (JES) is a peer-reviewed publication dedicated to advancing the understanding and application of electrical systems, communication systems and information science. With a commitment to excellence, we provide a platform for researchers, academics, and professionals to contribute to the ever-evolving field of electrical engineering, communication technology and Information Systems. The mission of JES is to foster the exchange of knowledge and ideas in electrical and communication systems, promoting cutting-edge research and facilitating discussions that drive progress in the field. We aim to be a beacon for those seeking to explore, challenge, and revolutionize the way we harness, distribute, and utilize electrical energy and information systems..
View
... The ATLAS dataset or PH2 dataset pictures are considered for investigation in the majority of the papers. [61] proposed a system which can achieve a higher throughput and higher energy efficiency. The S-BOX is designed by using Advanced Encryption Standard (AES). ...
Call for Papers - PROCEEDINGS ON ENGINEERING SCIENCES, P-ISSN-2620-2832, E-ISSN 2683-4111, indexed in Scopus
Preprint
Full-text available
  • Apr 2024
Proceedings on Engineering Sciences examines new research and development at the engineering. It provides a common forum for both front line engineering as well as pioneering academic research. The journal's multidisciplinary approach draws from such fields as Automation, Automotive engineering, Business, Chemical engineering, Civil engineering, Control and system engineering, Electrical and electronic engineering, Electronics, Environmental engineering, Industrial and manufacturing engineering, Industrial management, Information and communication technology, Management and Accounting, Management and quality studies, Management Science and Operations Research, Materials engineering, Mechanical engineering, Mechanics of Materials, Mining and energy, Safety, Risk, Reliability, and Quality, Software engineering, Surveying and transport, Architecture and urban engineering.
View
Call for Chapters- Edited Book: Quantum Networks and Their Applications in AI, IGI Global, USA, ISBN 9798369358320
Preprint
Full-text available
  • Apr 2024
The research on Quantum Networked Artificial Intelligence is at the intersection of Quantum Information Science (QIS), Artificial Intelligence, Soft Computing, Computational Intelligence, Machine Learning, Deep Learning, Optimization, Etc. It Touches On Many Important Parts Of Near-Term Quantum Computing And Noisy Intermediate-Scale Quantum (NISQ) Devices. The research on quantum artificial intelligence is grounded in theories, modelling, and significant studies on hybrid classical-quantum algorithms using classical simulations, IBM Q services, PennyLane, Google Cirq, D-Wave quantum annealer etc. So far, the research on quantum artificial intelligence has given us the building blocks to achieve quantum advantage to solve problems in combinatorial optimization, soft computing, deep learning, and machine learning much faster than traditional classical computing. Solving these problems is important for making quantum computing useful for noise-resistant large-scale applications. This makes it much easier to see the big picture and helps with cutting-edge research across the quantum stack, making it an important part of any QIS effort. Researchers — almost daily — are making advances in the engineering and scientific challenges to create practical quantum networks powered with artificial intelligence
View
Call for Papers- Journal of Wireless Mobile Networks, Ubiquitous Computing, and Dependable Applications (JoWUA), ISSN (Print): 2093-5374, ISSN (Online): 2093-5382, indexed in Scopus
Preprint
Full-text available
  • Apr 2024
JoWUA is an online peer-reviewed journal and aims to provide an international forum for researchers, professionals, and industrial practitioners on all topics related to wireless mobile networks, ubiquitous computing, and their dependable applications. JoWUA consists of high-quality technical manuscripts on advances in the state-of-the-art of wireless mobile networks, ubiquitous computing, and their dependable applications; both theoretical approaches and practical approaches are encouraged to submit. All published articles in JoWUA are freely accessible in this website because it is an open access journal. JoWUA has four issues (March, June, September, December) per year with special issues covering specific research areas by guest editors. The editorial board of JoWUA makes an effort for the increase in the quality of accepted articles compared to other competing journals..
View
Call for Papers - Utilitas Mathematica, E-ISSN: 0315-3681, indexed in Scopus
Preprint
Full-text available
  • Apr 2024
Utilitas Mathematica Journal is a broad scope journal that publishes original research and review articles on all aspects of both pure and applied mathematics. This journal is the official publication of the Utilitas Mathematica Academy, Canada. It enjoys good reputation and popularity at international level in terms of research papers and distribution worldwide. Offers selected original research in Pure and Applied Mathematics and Statistics. UMJ coverage extends to Operations Research, Mathematical Economics, Mathematics Biology and Computer Science. Published in association with the Utilitas Mathematica Academy. The leadership of the Utilitas Mathematica Journal commits to strengthening our professional community by making it more just, equitable, diverse, and inclusive. We affirm that our mission, Promote the Practice and Profession of Statistics, can be realized only by fully embracing justice, equity, diversity, and inclusivity in all of our operations. Individuals embody many traits, so the leadership will work with the members of UMJ to create and sustain responsive, flourishing, and safe environments that support individual needs, stimulate intellectual growth, and promote professional advancement for all.
View
Call for Chapters- Edited Book: Real World Challenges in Quantum Electronics and Machine Computing, IGI Global, USA, ISBN 9798369340011
Preprint
Full-text available
  • Apr 2024
Most experts would consider this the biggest challenge. Quantum computers are extremely sensitive to noise and errors caused by interactions with their environment. This can cause errors to accumulate and degrade the quality of computation. Developing reliable error correction techniques is therefore essential for building practical quantum computers. While quantum computers have shown impressive performance for some tasks, they are still relatively small compared to classical computers. Scaling up quantum computers to hundreds or thousands of qubits while maintaining high levels of coherence and low error rates remains a major challenge. Developing high-quality quantum hardware, such as qubits and control electronics, is a major challenge. There are many different qubit technologies, each with its own strengths and weaknesses, and developing a scalable, fault-tolerant qubit technology is a major focus of research. Funding agencies, such as government agencies, are rising to the occasion to invest in tackling these quantum computing challenges. Researchers — almost daily — are making advances in the engineering and scientific challenges to create practical quantum computers.
View
Call for Chapters- Edited Book: Real-World Applications of Quantum Computers and Machine Intelligence, IGI Global, USA, ISBN 9798369336014
Preprint
Full-text available
  • Apr 2024
It is no surprise that Quantum Computing will prove to be a big change for the world. The practical examples of quantum computing can prove to be a good substitute for traditional computing methods. Quantum computing can be applied to many concepts in today’s era when technology has grown by leaps and bounds. It has a wide beach of applications ranging from Cryptography, Climate Change and Weather Forecasting, Drug Development and Discovery, Financial Modeling, Artificial Intelligence, etc. Giant firms have already begun the process of quantum computing in the field of artificial intelligence. The search algorithms of today are mostly designed according to classical computing methods. While Comparing Quantum Computers with Data Mining with Other Counterpart Systems, we are able to understand its significance thereby applying new techniques to obtain new real-time results and solutions.
View
Call for Papers- Thematic Issue: Food, Drug and Energy Production, PERIÓDICO TCHÊ QUÍMICA, ISSN: 1806-0374 (Printed); 2179-0302 (Online), indexed in ESCI (Web of Science)
Preprint
Full-text available
  • Apr 2024
Published since 2004, Periódico Tchê Química (PQT) is a is a triannual (published every four months), international, fully peer-reviewed, and open-access Journal that welcomes high-quality theoretically informed publications in the multi and interdisciplinary fields of Chemistry, Biology, Physics, Mathematics, Pharmacy, Medicine, Engineering, Agriculture and Education in Science. Researchers from all countries are invited to publish on its pages. The Journal is committed to achieving a broad international appeal, attracting contributions, and addressing issues from a range of disciplines. The Periódico Tchê Química is a double-blind peer-review journal dedicated to express views on the covered topics, thereby generating a cross current of ideas on emerging matters.
View
Call for Papers - Onkologia i Radioterapia, P-ISSN-1896-8961, E-ISSN 2449-9161, indexed in Scopus
Preprint
Full-text available
  • Apr 2024
Onkologia I Radioterapia is an international peer reviewed journal which publishes on both clinical and pre-clinical research related to cancer. Journal also provide latest information in field of oncology and radiotherapy to both clinical practitioner as well as basic researchers. Submission for publication can be submitted through online submission, Editorial manager system, or through email as attachment to journal office. For any issue, journal office can be contacted through email or phone for instatnt resolution of issue. Onkologia I Radioterapia is a peer-reviewed scopus indexed medical journal publishing original scientific (experimental, clinical, laboratory), review and case studies (case report) in the field of oncology and radiotherapy. In addition, publishes letters to the Editorial Board, reports on scientific conferences, book reviews, as well as announcements about planned congresses and scientific congresses. Oncology and Radiotherapy appear four times a year. All articles published with www.itmedical.pl and www.medicalproject.com.pl is now available on our new website.
View
Call for Papers - Journal of Indian School of Political Economy, E-ISSN 0971-0396, indexed in UGC Group I
Preprint
Full-text available
  • Apr 2024
The journal is published every quarter and contains 200 pages in each issue. It is devoted to the study of Indian economy, polity and society. Research papers, review articles, book reviews are published in the journal. All research papers published in the journal are subject to an intensive refereeing process. Each issue of the journal also includes a section on documentation, which reproduces extensive excerpts of relevant reports of committees, working groups, task forces, etc., which may not be readily accessible, official documents compiled from scattered electronic and/or other sources and statistical supplement for ready reference of the readers. It is now in its nineteenth year of publication. So far, five special issues have been brought out, namely: (i) The Scheduled Castes: An Inter-Regional Perspective, (ii) Political Parties and Elections in Indian States : 1990-2003, (iii) Child Labour, (iv) World Trade Organisation Agreements, and (v) Basel-II and Indian Banks.
View
A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling
Conference Paper
Full-text available
  • Jul 2008
A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.
View
53 Gbps Native GF(2(4))(2) Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
Article
  • May 2011
Abstract-This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator fabricated in 45 nm CMOS, targeted for content-protection in high-performance microprocessors. 100% round computation in native GF(24)2 composite-field arithmetic, unified reconfigurable datapath for encrypt/decrypt, optimized ground & composite-field polynomials, integrated affine/bypass multiplexer circuits, fused Mix/InvMixColumn circuits and a folded ShiftRow datapath enable peak 2.2 Tbps/Watt AES-128 energy efficiency with a dense 2-round layout occupying 0.052 mm2, while achieving: (i) 53/44/38 Gbps AES-128/192/256 performance, 125 mW, measured at 1.1 V, 50 °C, (ii) scalable AES-128 performance up to 66 Gbps, measured at 1.35 V, 50 °C, (iii) wide operating supply voltage range with robust subthreshold voltage performance of 800 Mbps, 409 μW, measured at 320 mV, 50 °C (iv) 37% Sbox delay reduction and 25% area reduction with a compact Sbox layout occupying 759 μm2 (v) 67% reduction in worst-case interconnect length and 33% reduction in ShiftRow wiring tracks and (vi) 43 % reduction in Mix/InvMixColumn area with no performance penalty.
View
Thousand Core ChipsA Technology Perspective
Conference Paper
  • Jun 2007
This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.
View
A 21.54 Gbits/s fully pipelined AES processor on FPGA
Conference Paper
  • May 2004
This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining techniques, a maximum throughput of 21.54 Gbits/s is achieved. A fast and an area efficient composite field implementation of the byte substitution phase is designed using an optimum number of pipeline stages for FPGA implementation. A 21.54 Gbits/s throughput is achieved using 84 block RAMs and 5177 slices of a VirtexII-Pro FPGA with a latency of 31 cycles and throughput per area rate of 4.2 Mbps/Slice.
View
Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors
Article
  • May 2006
This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES). Different pipelined implementations of the AES algorithm as well as the design decisions and the area optimizations that lead to a low area and high throughput AES encryption processor are presented. With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18-/spl mu/m CMOS technology. Moreover, by pipelining the composite field implementation of the byte substitution phase of the AES algorithm (inner-round pipelining), the area consumption is reduced up to 35 percent. By designing an offline key scheduling unit for the AES processor the area cost is further reduced by 28 percent, which results in a total reduction of 48 percent while the same throughput is maintained. Therefore, the over 30 Gbits/s, fully pipelined AES processor operating in the counter mode of operation can be used for the encryption of data on optical links.
View
Design and performance testing of a 2.29-GB/s Rijndael processor
Article
  • Apr 2003
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-μm CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.
View
A Fast New DES Implementation in Software
Article
  • May 1999
  • Lect Notes Comput Sci
. In this paper we describe a fast new DES implementation. This implementation is about five times faster than the fastest known DES implementation on a (64-bit) Alpha computer, and about three times faster than than our new optimized DES implementation on 64-bit computers. This implementation uses a non-standard representation, and view the processor as a SIMD computer, i.e., as 64 parallel one-bit processors computing the same instruction. We also discuss the application of this implementation to other ciphers. We describe a new optimized standard implementation of DES on 64-bit processors, which is about twice faster than the fastest known standard DES implementation on the same processor. Our implementations can also be used for fast exhaustive search in software, which can find a key in only a few days or a few weeks on existing parallel computers and computer networks. 1 Introduction In this paper we describe a new implementation of DES[4], which can be very efficie...
View
A Technology Perspective,‖Proc
  • Jan 2007
  • 746-749
  • Core S Borkar
  • Chips
Borkar.S, ―Thousand Core Chips: A Technology Perspective,‖Proc. 44th Ann. Design Automation Conf., pp. 746-749, 2007.
Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
  • Apr 2011
  • 767-776
  • Aes-Encrypt Composite-Field
Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors,‖ IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 767-776, Apr. 2011.
A 167-Processor ComputationalPlatform in 65 nm CMOS
  • Apr 2009
  • 1130-1144
  • B M Mejia
  • Baas
Mejia, and B.M. Baas, -A 167-Processor ComputationalPlatform in 65 nm CMOS,‖ IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1130-1144, Apr. 2009.