Quilt packaging: A revolutionary and flexible approach to high-performance system in package

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Indiana Integrated Circuits (IIC), LLC offers an alternative solution known as 'Quilt Packaging' (QP) specifically for RF/microwave systems composed of different materials. QP is a direct edge-interconnect technology that has experimentally demonstrated less than 0.1 dB of insertion loss across the entire bandwidth ranging from 50 MHz to more than 100 GHz without any resonances. It enables multiple die from different materials and processing technologies to be integrated into a monolithic-like system that performs essentially as if it has been created as a single chip. It also has a significant potential in MEMS integration, power management, and large-format imaging array applications, with significant cost and performance advantages. It has evolved from a basic research concept into an integration solution ready for wider-spread adoption.

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... The end result forces the system designer to make painful design trade-off choices between performance, thermal management, form factor, and power. A high-performance, customizable microchip integration technology called Quilt Packaging® (QP) [2][3][4][5][6][7] directly addresses these key areas for improvement, and empowers the system designer to overcome these design trade-off constraints. Figure 1 compares conventional, traditional packaging approaches with Quilt Packaging. ...
... Such 3D configurations include, but are not limited to, hemispherical curved arrays and orthogonal 3D architectures in which "daughter-card" chips with QP nodules are orthogonally inserted into corresponding sockets on a "motherboard" chip ( Figure 5). Particular advantages that QP can provide for 3D system configurations are as follows: {1} Allows the system designer to quickly and inexpensively explore design variations and tradeoffs related to unique form factors required for wearable devices; {2} Provides for rapid prototyping/manufacturing of miniaturized systems as an enabler of out-of-plane alignment and mechanical joining; {3} Provides for rapid prototyping and manufacturing of customized miniature systems using customizable interconnect geometry and I/O density for power, ground, and signal lines between chips [3]; {4} Provides extreme flexibility and customization of systems---QP can be implemented in a wide variety of substrates, including Si, GaAs, SiGe, InP, GaN, and SiC; {5} Allows assembly of mechanically stable curved systems without added complexity. ...
Conference Paper
A microchip integration technology called Quilt Packaging (QP) enables rapid prototyping of complex SoCs and microwave/RF systems, as well as optical, power, and DSP applications. QP is a direct edge-to-edge chip-level interconnect technology that can be implemented in a variety of materials and/or process technologies, and has been demonstrated in both planar and non-planar 3D architectures. Quilt Packaging technology can be applied to create a "Lego-like" design kit for ultra-fast prototyping and proof-of-concept chip-level system verification. Partitioning sub-components into small, inexpensive "chiplets" can allow for much faster design turns and greatly reduced first-pass prototype verification. In addition, QP enables low-loss, high-throughput chip-to-chip I/O interconnects while reducing size, weight, and power requirements, lessening the burden of design trade-offs for hardware system designers developing the next generation of microelectronic systems.
Full-text available
ldquoQuilt packagingrdquo (QP), a new superconnect paradigm for interchip communication, is presented. QP uses conducting nodules that protrude from the vertical facets of integrated circuits to effect a dense, fast, and reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is presented along with a discussion of advantages over traditional system-on-chip and other system-in-package technologies. A process flow and results of chip fabrication are detailed. Simulations show expected signal propagation between adjacent die of greater than 200 GHz, and measurements of interconnected chips confirming low losses and resonance-free operation to at least 40 GHz have been achieved.