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Pixel reset circuit is an important component of CMOS image sensor, whose characteristics affect the image quality directly. The performances of CMOS image sensor, such as dynamic range, anti-blooming, image lag and non-linearity, are analyzed. This paper also discusses the methods to improve performance through reset circuit. In this paper, two kinds of hard reset circuit with anti-blooming circuit are designed, one is the use of conventional cross-coupled configuration to implement reset level shift, the other is based on improved latch configuration with adding compensation transistor of threshold value, both schemes with different advantages and disadvantages adapt for different applications. The simulations reveal that both circuits implement can enhance dynamic range by 2 dB~3 dB, increase the ability of anti-blooming, and remove image lag and non-linearity at low-light level.
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... CMOS image sensor is not only widely used in portable digital camera, mobile phone camera, hand-held camera, digital Single lens reflex (SLR) camera and other consumer electronic products, but also in smart car, satellite, security, robot vision and other fields. At the same time, there are also intelligent CMOS image sensors or CMOS image sensor integrated with intelligent processing function on chip  . Due to the requirements of the shooting fast moving objects, the CMOS image sensor with global shutter must be used because the rolling shutter cannot meet the requirements in high-speed photography, automation and industrial applications  . ...
An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non‐linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self‐establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01% of the whole chip power consumption.
... Owing to the intrinsic higher integration, lower power consumption, faster speed, the demand for CMOS image sensors has lately grown very rapidly due to the increased application. Meanwhile, Backside illuminated (BSI) and 3D stacked CMOS image sensors have bring to high sensitivity and integrations for small pixels, which making up for insufficient than charge coupled device, will further expand the wider application [1,2] . ...
A technical investigation, research and implementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non‐ideal factor and error source of piecewise Digital to analog converter (DAC) in multi‐channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06%, a low photo response non‐uniformity of 1.5% respectively, and an excellent raw sample image taken by the prototype sensor.
A new CMOS image sensor column parallel ADC circuit structure for suppressing the kickback noise of the single slope comparators is proposed in this paper. In order to suppress the kickback noise of the original node, the crosstalk of the shared ramp reference is compensated by detecting the column ramp signal jumping, and the transmission of the noise on the shared reference line is blocked. The proposed approach has been verified and experimented in a 3072(H) × 2560(V) CMOS image sensor based on 55nm 1P4M CMOS process, and the sensor achieves 12bit precision column parallel digital quantization. In the worst case, when 1 to 1000 columns are flipped simultaneously, the kickback noise can be reduced to less than 1LSB and compensated quickly without additional power consumption and area. The measurement results show that the single slope ADC can be operated at 500MHz and achieved 4.6μs digital correlated double sampling row time for a 12-bit linear A/D conversion, the DNL is controlled within ±0.48LSB, the INL is not more than ±4LSB, and the SNR is up to 71dB. It is important that the power consumption of each column is only 24μW.
Pixel reset noise sets the fundamental detection limit on photodiode based CMOS image sensors. Reset noise in standard active pixel sensor (APS) is well understood and is of order kT/C. In this paper we present a new technique for resetting photodiodes, called active reset, which reduces reset noise without adding lag. Active reset can be applied to standard APS. Active reset uses bandlimiting and capacitive feedback to reduce reset noise. This paper discusses the operation of an active reset pixel, and presents an analysis of lag and noise. Measured results from a 6 transistor per pixel 0.35 micrometers CMOS implementation are presented. Measured results show that reset noise can be reduced to less than kT/18C using active reset. We find that theory simulation and measured results all match closely.
The disadvantages of traditional pixel reset circuit for image sensor, such as limit to dynamic range, fixed picture noise (FPN) and image lag, are analyzed. The advantages and disadvantages of two methods to improve reset circuit are compared. A new approach to use charge pump to improve reset circuit is presented. Enhancing dynamic range and removing FPN and image lag are implemented by using the new approach which selves the problems of two methods mentioned above. Simulation of all circuits is implemented based on process of 0.35 μm of CHRT.
The vertical integrated diode can sense blue and red illumination simultaneously, it can provide full color information with green/magenta filter on it. It can also be the pixel of the CMOS image senor for its fully compatible with standard CMOS process. Its basic principle is to use the silicon's differences of penetration depths of electromagnetic waves with different wavelengths, i.e., blue light with short wavelength is absorbed mainly at surface while red light with longer wavelength is absorbed deeper. Through extraction of photogenerated carrier at different depth by vertical integrated diode with two color filters, we get the full color image. The numerical simulation and the experimental device show that it can provide color information and can be applied in CMOS image sensor pixel design.
Fabricated in a standard 0.35 μm CMOS process, a new type detector designed for high energy particle tracking was studied in this work. The detector is based on monolithic CMOS active pixel sensor (MAPS) technology. Using standard CMOS process, signal processing circuits are integrated on the same substrate as the sensors and correlated double sampling (CDS) operation is realized inside pixel. The prototype consists of a 128×32 pixel array and pixel pitch is 25×25 square of micrometer. Measured by a radioactive source 55Fe, the temporal noise is only about 12 electrons and the residual offset is only about 4 electrons. The charge-to-voltage conversion factor (CVF) is about 60 μV/e-. During the tests, readout speed reaches 12 μ/frame.
Dynamic range is a critical figure of merit for image sensors. Often a sensor with higher dynamic range is regarded as higher quality than one with lower dynamic range. For CCD and CMOS sensors operating in the integration mode the sensor SNR monotonically increases with the signal. Therefore, a sensor with higher dynamic range, generally, produces higher quality images than one with lower dynamic range. This, however, is not necessarily the case when dynamic range enhancement schemes are used. For example, using the well capacity adjusting scheme dynamic range is enhanced but at the expense of substantial degradation in SNR. On the other hand, using multiple sampling dynamic range can be enhanced without degrading SNR. Therefore, even if both schemes achieve the same dynamic range the latter can produce higher image quality than the former. The paper provides a quantitative framework for comparing SNR for image sensors with enhanced dynamic range. We introduce a simple model to describe the sensor output response as a function of the photogenerated signal, dark signal, and noise for sensors operating in integration mode with and without dynamic range enhancement schemes. We use the model to quantify and compare dynamic range and SNR for three sensor operation modes, integration with shuttering, using the well capacity adjusting scheme, and using multiple sampling.