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Finite element analysis on the effect of solder joint geometry for the reliability of ball grid array assembly with flexible and rigid PCBS
Abstract
In the present study, three-dimensional (3D) finite element simulation on 132 PIN fleXBGATM package was performed to predict the effect of solder joint geometry on the reliability of Ball Grid Array (BGA) solder joints on flexible and rigid PCBs subjected to thermo-cyclic loading. The commercial FEA tool
ABAQUS Version 6.9 was used for the simulations of various shapes of solder joints such as barrel, column and hourglass. Apart from a global modeling, the submodeling analysis technique (local modeling) was also used on the critically affected solder joints, in order to enhance the computation efficiency. The accumulated creep strain and strain energy density were observed for each case, and optimum geometries were obtained. The model was validated with the published experimental data with the minimum percentage error of 3%. It was observed that the hourglass solder joint geometry was very crucial on the reliability of BGA solder joints, and for a given PCB, the optimal choice of hourglass solder joint geometry depended on its rigidity.
... The governing equations are complex partial differential equations (PDEs) that are difficult or impossible to solve analytically. Therefore, the discretization process takes place to convert the PDEs and corresponding boundary and initial conditions into discrete algebraic equations through the finite difference method (FDM) [95], finite element method (FEM) [41,48,81,86,91,[96][97][98][99][100][101][102][103][104][105][106][107][108][109][110][111][112], finite volume method (FVM) [96,97,[113][114][115][116], and lattice Boltzmann method [117]. The comparison between these discretization methods is briefed in Table 5 [12,117,118]. ...
... An hourglass shape of the solder joint can be obtained, and the board warpage can be minimized due to the selective heating in the solder joint. Lau et al. [104] also studied the effect of geometric parameters on 63Sn37Pb solder integrity using 3-D FE stress analysis. Among the various joint shapes (i.e., barrel, column, and hourglass), the stress at the joint corner of the hourglass geometry was lower; thereby, its rigidity was better. ...
... It was found that the temperature distribution in the oven was uneven, inhomogeneous, and influenced by the fan in the reflow soldering process. Lau et al. [104] studied the correlation between temperature distribution and thermal stress-induced. They observed that the temperature distribution was uneven during the solder solidification process. ...
This paper reviewed the state-of-art copper pillar technology in flip-chip packaging, driven by the semiconductor industry’s demands for thinner and faster data transmission. This technology with area array feature is a surface mount technology process used to form interconnection bonding between ball grid array chip and printed circuit board (PCB) by the reflow soldering process. The conversion of the flip-chip interconnection bump from the solder ball to the Cu pillar bump with the solder cap and the joint performance within the reflow oven are presented in this review. The simulation tools have recently facilitated the Cu pillar bump research during the PCB assembly process. Thus, this review focuses on the simulation modeling of the PCB assembly within a reflow oven using different numerical approaches. The thermal and air flow aspects of the reflow process are reviewed. The temperature distribution and the thermal stress condition of the PCB assembly within the reflow oven are predicted to understand better the fluid–structure interaction in the reflow oven. The considerations of air flow and thermal effects enhanced the study of fluid flow on the PCB assembly. Moreover, the Cu pillar technology challenges are also highlighted in this review. This review paper is expected to provide necessary information and direction to future researchers and industrial engineers when designing a brand-new surface-mounted component.
... Recently, however, many studies on nonlinear behavior characteristics of insulating materials in the substrate have been conducted. With the development of various transformation model formulas, studies on the effects of the nonlinear behaviors of materials on warpage have been conducted using simulation technology [20][21][22][23][24][25][26]. ...
... formulas, studies on the effects of the nonlinear behaviors of materials on warpage have been conducted using simulation technology [20][21][22][23][24][25][26]. ...
To analyze the effects of nonlinear behavior characteristics of prepreg (PPG) among the insulating materials of substrate and the residual stress of laminating process on the warpage of substrate, this study investigated the continuous laminating process using the numerical analysis by finite element method. The analysis results showed that the warpage of the substrate in the laminating process of PPG was very low, but it increased rapidly in the solder resist (SR) laminating process. As the laminating process of PPG continued, the stress inside the substrate increased continuously and it was predicted to decrease in the SR laminating process. These results confirmed that the warpage of the substrate is influenced the most by the SR laminating process, and that the warpage and stress of substrate accumulated in the laminating process of PPG have significant effects on the final warpage.
... Various studies using numerical simulations have been used to investigate underfill encapsulation process. These include the use of numerical studies such as finite element method (FEM) (Lee et al., 2009;Lau et al., 2014;Yeh et al., 2018), finite volume method (FVM) (Wan et al., 2009;Fei Chong et al., 2017;Ng et al., 2018), and Lattice Boltzmann method (LBM). LBM has been extensively used in microscale approach since the medium is made up of particles that represented the particle velocity distribution function at each grid point which is continuously colliding with each other. ...
... Furthermore, hourglass shape solder would protect the weak joint interface though the tradeoff would be an increase chance of having midpoint failure (Lau et al., 2014). The reason for this phenomenon is that hourglass shape solder joint has much higher adhesion strength than barrel-shaped solder joint due to the smaller contact angle (Liu and Lu, 2003). ...
Purpose
In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method.
Design/methodology/approach
Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results.
Findings
Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints.
Practical implications
This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages.
Originality/value
LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.
... The conventional and no-flow underfill processes are illustrated in Throughout the years, there has been considerable amount of conventional underfill research studies conducted on the BGA technology but limited for no-flow underfill [6]. Numerous approaches of numerical studies have been conducted for the conventional underfill process in recent years such as finite element method (FEM) [7][8][9], finite volume method (FVM) [3,5,[10][11][12][13][14] and Lattice Boltzmann method (LBM) [15][16][17][18]. Mostly the research on no-flow underfill process has been focused on experimental method that is costly and time consuming [19][20][21][22][23][24][25][26]. ...
No-flow underfill process was introduced to enhance the production lead time since the curing and reflow of solder interconnect and underfill are achieved simultaneously. In addition, no�flow underfill can produce near void-free flow during the assembly process. This paper investigates one of the important process of no-flow underfill which is the effect of chip placement speed towards the void formation by using finite volume method (FVM) based numerical simulation and experimental method. The simulation works reported that the increase in chip placement speed effectively increased the gauge pressure and velocity of the underfill flow. The highest chip placement speed in this study is 14 mm/s producing 12,300 Pa of gauge pressure and 0.1 m/s of underfill flow velocity. Somehow, the flow profiles revealed that finger-like profile was formed above 5 mm/s speed during the compression process of no-flow underfill that will lead to issue of void formation in the ball grid array (BGA) region. Based on this issue, it is important to choose the optimal parameter of placement chip speed to be implemented in the process. This study recommended the usage of below 5 mm/s of chip placement speed since the issue of finger-like formation is minimum thus the void formation in chip can be controlled effectively. This paper provides reliable insight to the industry to choose the best speed of placement chip of no-flow underfill process.
... At present, there is a gap of studies on the no-flow underfill found in literature with many research tend to study the conventional underfill since it is the most commonly used method by the industry to protect BGA. Substantial amount of numerical studies had been conducted for the conventional underfill process that can be classified into few approaches such as finite element method [7][8][9], finite volume method (FVM) [2,[10][11][12][13][14][15], and lattice Boltzmann method [16][17][18][19]. Generally, the research works on no-flow underfill process is usually conducted by means of physical experiment [1,[20][21][22][23][24][25][26]. ...
The conventional capillary underfill process has been a common practice in the industry,
somehow the process is costly and time consuming. Thus, no-flow underfill process is
developed to increase the effective lead time production since it integrates the simultaneous
reflow and cure of the solder interconnect and underfill. This paper investigates the effect of
different dispense patterns of no-flow underfill process by mean of numerical and experimental method. Finite volume method (FVM) was used for the three-dimensional simulation to simulate the compression flow of the no-flow underfill. Experiments were carried out to complement the simulation validity and the results from both studies have reached a good agreement. The findings show that of all three types of dispense patterns, the combined shape dispense pattern shows better chip filling capability. The dot pattern has the highest velocity and pressure distribution with values of 0.0172 m/s and 813 Pa, respectively. The high-pressure region is concentrated at the center of the chip and decreases out towards the edge. Low in pressure and velocity flow factor somehow lead to issue associated to possibility of incomplete filling or void formation. Dot dispense pattern shows less void formation since it produces high
pressure underfill flow within the BGA. This paper provides reliable insight to the industry to choose the best dispense pattern of recently favorable no-flow underfill process.
... These include the development of an empirical equation for predicting the thermal-fatigue life of solder bumps using the measured crack growth rate at the crack tip (H. Lau, et al., 2001); the prediction of the effect of solder joint geometry on the reliability of Ball Grid Array (BGA) solder joints on flexible and rigid PCBs subjected to thermocyclic loading (Lau, et al., 2014); the investigation of the impact of Inter Metallic Component (IMC) on the reliability of lead-free solder joints at elevated temperature operations (Amalu and Ekere, 2011) and modelling evaluation of Garofalo-Arrhenius creep relation for lead-free solder joints in surface mount electronic component assemblies (Amalu and Ekere, 2016). The results of these previous studies show that the thermal fracture mechanism of a solder joint interconnection can generally be sub-divided into two distinct modes. ...
As the cost of PV (photovoltaic) solar panels drops, it is widely expected that solar energy will become the cheapest source of electricity in many parts of the world over the next two decades. To ensure that PV solar modules have a long service life and can meet the PV manufacturer’s warranty, the PV modules need to have high reliability. Solar PV module manufacturers typically provide two warranties: a performance warranty which guarantees 90% of original power output after 10 years and 80% of original output of at 25 years; and an equipment warranty which guarantees their PV module will have a minimum of 10–12 years operation before failure. A critical part of the solar PV module assembly is the ribbon interconnection between the solar cells (i.e. the solder joint interconnections), and failure of the ribbon interconnection can adversely affect the performance and reliability of whole PV module. Ribbon interconnection failures have been linked to the thermal cracks which are initiated in the solder joint material during the high temperature ribbon interconnection manufacturing process; and then the crack propagation and growth associated with the thermal cycling of the ribbon interconnections under higher than ambient temperature PV module operating conditions. This paper reports on the study of high temperature crack initiation and propagation in different PV Module interconnection configurations by using XFEM in ABAQUS software. It concerns a necessary, urgent and fundamental revision of the manufacturing process that lies at the heart of PV module ribbon interconnection manufacture.
... Their finite element-based simulation results showed a fairly uniform reflow temperature profiles across all solder joints. Lau et al. [20] performed a finite element simulation to investigate the geometry size effects of BGA solder joints on creep fracture under thermal cycling. They found that the fracture of solder joints shifts into the interior when the height of the solder joints increases. ...
This study investigates the effects of filling level and fillet profile on a solder joint strength between pin-through hole (PTH) and a printed circuit board. The influences of filling level and fillet profile on deformation, von Mises stress and strain are the focus of this research. Five filling levels (20%, 40%, 60%, 80% and 100%) and fillet profiles (0.2, 0.4, 0.6, 0.8 and 1.0) are considered. The Abaqus software is used to examine the PTH structure. A tension test experiment is conducted on a single PTH connector, and its results are compared with the simulation results. The simulation and experimental results show an almost identical linear trend with an average discrepancy of 3.39%. Results show that an increase in the filling level and the fillet profile increases the structural deformation/displacement and the von Mises stress. The displacement and the von Mises stress of the PTH exhibit a linear correlation with the filling level and the fillet profile. This study is expected to provide a good understanding of solder joint strength during wave soldering.
... of the solder joints, the fracture position shifted from the interface of the chip and the solder joints to the interior of the solder joints [9], S.S. Lim et al [10] got the same results. J.H. Lee et al [11] measured the resistance changes of the solder joints during electromigration, the results revealed that the electromigration lifetime increased with the decrease of the height of the solder joints. ...
This paper investigated the geometric size effects on elements consuming at the solder pad under current stressing. The micro solder joints Cu/Sn-3.0Ag-0.5Cu(SAC305)/Cu with same volume and different heights (H1=300μm, H2=420μm and H3=520μm) were made for the electromigration test. The results indicated that the consumption of copper element at the solder pad increased with the increase of the height of the solder joints after reflow. In the electro-thermal aging test, the consumption of copper element at the cathode solder pad increased linearly with the increase of stressing time, and the average consumption rate increased with the increase of the height of the solder joints. It is suggested that the solder joints with a higher bump height had a lower dispersion of current density, which resulted in a higher current density in the migration routine of the metal atoms. Current density is the dominant driving force in the process of the electromigration. However, the consumption of copper element at the anode solder pad increased linearly with the increase of the square root of stressing time, and the average consumption rate has the same law with that at the cathode. The numerical simulation was also conducted under the same stressing conditions as the experimental tests. The results revealed that the solder joint with a higher bump height had a lager internal current density, which is consistent with the experimental results.
The reflow soldering process is crucial in flip chip applications for forming a high-quality interconnection joint. This paper aims to investigate the effect of bump diameters of solder bump and copper pillar bump on the reflow temperature distribution during the reflow soldering process. A simplified reflow oven is developed and the virtual reflow process is established using computational fluid dynamics (CFD) software. The simulation study is validated with the experiment result. The numerical findings show that the temperature distribution is uniform in the copper pillar bumps with different diameters but uneven for the solder bumps. This study provides a foundation and insights into the effects of copper pillar bump structure on the reflow temperature profile during the reflow soldering process.KeywordsCopper pillar technologyInfrared-convection reflow ovenComputational fluid dynamicsSurface mount technology
As a result of growing technological advancement, the increase in input and output terminals in electronic packaging has increased significantly. This signifies the commensurate rise in the number of solder joint interconnections. Hence, for the purpose of complying with the mission and vision of the electronic industry including the manufacturing of robust, efficient, and miniaturized devices, it is essential to incorporate reinforcing components into the existing traditional lead-free solders for the requisite materials modification. This short review article documents the progress made so far in the improvement of lead-free solders with selected reinforcement. The article covers the evaluation of the reliability level of solders reinforced with three targeted categories of materials such as carbon-based nanomaterials, interlayer components, and agricultural waste.KeywordsLead-free solderReinforcementCarbon-based nanomaterialsInterlayer componentsAgricultural wasteReliability
Finite element simulation was performed on 132 pin fleXBGATM package assembly using ANSYS Workbench 21.1 to investigate the integrated effect of solder geometry and intermetallic compound on the thermal fatigue reliability of lead-free solder joint. Various solder geometries represented by shape factor are simulated with intermetallic compound layer thickness of 0, 3 and 6 μm. Global model simulation was firstly performed to identify the most critically affected joint in the package assembly subjected to thermal cycling test based on highest accumulated inelastic strain. Subsequently, sub-modelling analysis technique was applied on the critical joint to enhance the computational efficiency. The results showed that the location of the critical joint is consistent irrespective to solder geometry and intermetallic compound. Hourglass shape generally enhances the reliability of the solder joint, and the optimum performance is found on shape factor of 0.604. Besides, intermetallic compound layer thickness degrades the reliability of solder joint with shape factor above 1 but improves the reliability of solder joint with shape factor below 1.
Recently, the copper pillar with solder cap interconnection has been introduced as an alternative for the solder bump interconnection to tackle the limitations, such as the collapsing nature of the solder bump and larger pitch size. This paper presents an effective simulation tool to evaluate the effects of different diameters of the copper pillar with solder capCopper pillar with solder cap during the reflow soldering process. A three-dimensional numerical approach is used to investigate the thermal behavior of the copper pillar with solder caps with different diameters. The interconnection bump diameters are 150, 200, 250, 300, and 350 μm. The model is developed and meshed using the Computational Fluid DynamicsComputational fluid dynamics (CFD) software. The temperature distributions of the copper pillar with solder capsCopper pillar with solder cap with different diameters during the reflow soldering process are predicted. The paper aims to provide an understanding of the effect of diameters on the temperature distribution of copper pillars with solder caps during reflow soldering.
This paper is about study on warpage, creep strain and the total strain energy density (TSED) effect on fatigue life of the solder joints in the embedded package under thermal cycling conditions by finite element method. In order to investigate the influence of material of solder joints in embedded package, four materials (SAC305, SnAgCu, Sn96.5Ag3.5, Pb97.5Sn2.5) of solder joints were used. Calculated results show that warpage of package was low, creep strain and TSED of solder joints were low in embedded package. Therefore the fatigue life of the solder joint in embedded package increases. Also, the fatigue life of solder joints of Sn96.5Ag3.5 would be highest among solder materials because of the lowest of TSED.
Graphical Abstract
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The diffusion velocity method (DVM), a version of vortex element method (VEM), was used to model the steady state, laminar natural convection flows along isothermal vertical plates and in isothermal vertical channels. For each case, numerical models were developed using DVM from the vorticity transport equation and the energy equation. This study shows that the diffusion velocity method is a viable numerical tool at modelling not only fluid flow problems but also the heat transfer problems. © 2010 by Maejo University, San Sai, Chiang Mai, 50290 Thailand.
The objective of this work is to model the fatigue damage process in a solder bump subjected to cyclic loading conditions. Fatigue damage is simulated using the cohesive zone methodology. Damage is assumed to occur at interfaces modeled through cohesive zones in the material, while the bulk material is assumed to be linear elastic. The state of damage at a cohesive zone is incorporated into the cohesive zone constitutive law by a elasticity-based damage variable. The gradual degradation of the solder material and the corresponding damage accumulation throughout the cycling process is accounted for by a damage evolution law which captures the main damage characteristics. The model prediction of the solder bump life-time is shown to be in good agreement with one of the commonly used empirical life-time prediction laws.
Summary form only given. A critical review of the life prediction
and accelerated testing of solder joints, including the role of
constitutive modeling and the factors of accelerated testing, is
presented in this paper. As a perfect example, a Ford solder joint
specimen was used to investigate accelerated testing factors under
various accelerated testing conditions in terms of thermal fatigue life.
Moreover, a typical PQFP (plastic quad flat pack) package was chosen to
clarify the significance of fatigue life prediction in terms of
different finite element models and unified and separated constitutive
models. Thermal fatigue life prediction of flip chip packages with ball
pitch sizes from 250 μm to 50 μm has been performed to illustrate
underfill strengthening mechanisms and obtain an upper bound of
accelerated testing factors, which can reduce testing time from three
years to one week. Rate/temperature-dependent nonlinear properties of
both eutectic solder and FP4526 underfill have been embedded in the
ABAQUS finite element analysis for flip chip packages. All of these
examples enlighten key points addressed in this report
Solder joint shape refers to geometry that molten solder can be achieved with spreading and wetting along the metal surface in the junction between components solder pins and printed circuit board (PCB) pad, to the metal surface contact angle and solder fillet shape[I]. BLP (Bottom Leaded Plastic) [2] which is not a type of thin out-line surface mount device(SMD) without the side lead is widely used in manufacturing of new generation memory such as SDRAM \ RDRAM \ DDR. For this non-lead SMD, the shape and reliability of solder joint is the focus of the study. In this paper, we select the C-BLP of 28-pin device as the research object, complete the forming model of solder joint shape based on minimum energy principle and the solder joint shape theory by using Surface Evolver software, and analyze two critical process parameters (solder volume and solder pad width) impacting on the solder joint shape. The study results show that the solder volume and pad width have a significant impact on the three-dimensional shape of BLP solder joint. The law of which is that: in the case of the other fixed parameters, as the increase of the solder volume, solder joint surface gradually changes from the relatively flat to the convex, solder joint gradually changes from the completely soldered to the partly soldered in the pad connections, and solder joint heights are gradually decreased; in the case of the other fixed parameters, as the increase of the pad in width, the solder joint surface gradually changes from the convex to the flat, solder joint gradually changes from the completely soldered to the partly soldered in the pad connections, and solder joint heights are gradually decreased. The actual solder joint shape designs of BLP devices can be instructed based on predicted results.
The visco-plastic behaviour of solder joints of two models of a flip chip FC48D6.3C457DC mounted on a printed circuit board (PCB) via SnAgCu solder is investigated using Anand's model. While the bumps of one of the models are realistic with 6μm thickness of intermetallic compound (IMC) at interconnects of solder and bond pads, the other are made up of conventional bumps without IMC at these interconnects. The solder bump profiles were created using a combination of analytical method and construction geometry. The assembled package on PCB was accelerated thermally cycled (ATC) using IEC standard 60749-25. It was found in the result of the simulation that IMC does not only impact solder joint reliability but also is a key factor of fatigue failure of solder joints. The IMC sandwiched between bond pad at chip side and solder bulk is the most critical and its interface with solder bulk is the most vulnerable site of damage. With reference to our results, it is proposed that non inclusion of IMC in solder joint models composed of Sn-based solder and metalized copper substrate is one of the major causes of the discrepancy on solder joint fatigue life predicted using finite element modelling and the one obtained through experimental investigation.
The use of PBGA (plastic ball grid array) electronic packages has been greatly increased in the last decade due to high I/O densities offered. The fatigue life prediction for them is a relatively new task in the electronic field. PBGA packages have more complex geometry than conventional SMT (surface mount technology) packages, such as Leaded and Lead-less Chip Carriers (LDCC and LLCC), in which the I/O pins are distributed along the perimeters of chip carriers and their geometries are suitable for two-dimensional (2-D) finite element (FE) simulation. This choice is not so clear in PBGAs. In this study, sectional 2-D, sliced three-dimensional (3-D), and 1/8th 3-D FE models for PBGA assemblies are compared to determine the appropriate FE models that are able to save computational time and memory while maintaining reasonable calculation accuracy. The comparisons and merits of each modeling approach are discussed. An energy-based method is used to predict the fatigue life for solder joints in PBGAs. The fatigue coefficients in the correlation equation, which were obtained previously from the analysis of traditional SMT packages, are updated for more accurate prediction. New fatigue coefficients are obtained for different modeling approaches.
In order to reduce the reliability testing time for new electronic products, a new highly accelerated mechanical-thermal (HAMT) test system has been developed. In this system, a cyclic out-of-plane deformation is imposed on a printed circuit board (PCB) assembly by twisting the PCB mechanically inside a thermal chamber. The combined effects of the mechanical deformation and the coefficient of thermal expansion (CTE) mismatch of different materials accelerate the failure of solder joints, so as to reduce the reliability testing time of the PCB assembly. To verify the test method, HAMT tests of plastic ball grid array (PBGA) assemblies were carried out in an isothermal environment. Finite-element (FE) simulations were conducted to predict the reliability of the PBGA assemblies under the isothermal/mechanical twisting (ITMT) loading condition. In this paper, the simulation results are presented. The failure locations in the PBGA solder joints under the ITMT loading condition are investigated, and the fatigue life of the interconnections is predicted using Darveaux's crack initiation and growth model. The simulation results exhibit a good correlation with the test results.
A review of fourteen solder joint fatigue models is presented here with an emphasis on summarizing the features and applications of each fatigue model. The models are classified into five categories: stress-based, plastic strain-based, creep strain-based, energy-based, and damage-based. Fatigue models falling outside these categories are categorized as ‘other empirical models’. Each model is presented under one category with the relevant parameters and applicable packages. Following each category, common issues such as thermal cycling conditions, solder joint geometry, and coverage are addressed. Two fatigue model application scenarios are discussed. In the first scenario, a set of existing fatigue test data is given to the engineer who must determine how best to interpret the data and which fatigue model(s) best apply. In the second scenario, a test scheme must be devised for a new chip scale package product. The number of cycles to failure (Nf) or fatigue life must be determined. A general procedure is presented for choosing an appropriate fatigue model(s) based on the package conditions and limited Finite Element Analysis time. This procedure is summarized in a flowchart.
In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect, for improving the solder joint reliability is also presented.
A generalized solder joint fatigue life model for surface mount packages was previously published by the author. The model is based on correlation to measured crack growth data on BGA joints during thermal cycling. It was subsequently discovered by Anderson et. al. that the ANSYSTM 5.2 finite element code used in the model had an error in its method for calculating plastic work. It was shown that significant error in life prediction could result by using a recent version of the code where the bug has been fixed. The error comes about since the original crack growth constants were derived based on plastic work calculations that had the bug. In this paper, crack initiation and growth constants are recalculated using ANSYSTM 5.6. In addition, several other model related issues are explored with respect to the crack growth correlations. For example, 3D slice models were compared to quarter symmetry models. Anand's constitutive model was compared with Darveaux's constitutive model. It was shown that the crack growth rate dependence on strain energy density always had an exponent of 1.10+/-0.15. This is in the range of the original correlation, so the accuracy of relative predictions should still be within+/-25%. However, the accuracy of absolute predictions could be off by a factor of 7 in the worst case, if the analyst uses a modeling procedure that is not consistent with that used for the crack growth correlation. The key to good accuracy is to maintain consistency in the modeling procedure
A number of models for thermomechanical stress analysis and fatigue failure of materials are reviewed and their capabilities and limitations are identified. The unified disturbed state concept (DSC) for constitutive modeling of materials and interfaces is presented and compared with other approaches. An approximate procedure based on the DSC is proposed for accelerated design-analysis and cyclic fatigue failure. Solutions of example problems using the DSC and associated computer (FE) procedures are included to illustrate its integrated and improved capabilities for analysis of stresses, strains, microcracking, fracture and fatigue failure, and reliability.
The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40⇔125°C, 15 min ramps, 15 min dwells and 0⇔100°C, 10 min ramps, 5 min dwells.
This study examines damage initiation and propagation in solder joints with voids, under thermomechanical cyclic loading. An accelerated thermal cycling test is conducted on printed wiring assemblies (PWAs) containing 256 input/output (I/O) plastic ball grid arrays (PBGAs) with voided solder joints. Destructive and nondestructive failure analyses of the solder balls are used to detect the presence of voids and to relate the extent of damage propagation to the number of thermal cycles. Particular cases of voided and damaged joints are selected from these tests, to guide the development of a strategy for modeling damage propagation, using a three dimensional global-local finite element analysis (FEA). The displacement results of the global FEA at the top and bottom of the selected solder balls are used as the boundary conditions in a local FEA model, which focuses on the details of damage initiation and propagation in the individual solder ball. The local model is error seeded with voids based on cases selected in experiment. The damage propagation rate is monitored for all the cases. The technique used to quantify cyclic creep-fat́igue damage is a continuum model based on energy partitioning. A method of successive initiation is used to model the growth and propagation of damage in the selected case studies. The modeling approach is qualitatively verified using the results of the accelerated thermal cycling test. The verified modeling technique described above is then used for parametric study of the durability of voided solder balls in a ChipArray Thin Core BGA with 132 I/O (CTBGA132) assemblies, under thermal cycling. The critical solder ball in the package is selected and is error seeded with voids with different sizes and various distances from damage initiation site. The results show that voids in general are not detrimental to thermal cycling durability of the CTBGA132 assembly, except when a large portion of the damage propagation path is covered with voids. Small voids can arrest the damage propagation, but generally do not provide a significant increase in durability because the damage zone deflects around the void and also continues to propagate from other critical regions in the solder ball.
In a finite element analysis, when localized behavior of a large model is of particular concern, generally one would refine the mesh until it captures the local solution adequately. Submodeling is an alternative way for solving this kind of problem. It provides a relatively accurate solution at a modest computational cost. For a valid submodeling analysis, the boundaries of the submodel should be sufficiently far away from local features so that St. Venants principle holds. Moreover special treatments are required for solving problems that involve path-dependent characteristics. This paper presents a general procedure to perform submodeling analyses for path-dependent thermomechanical problems without a priori assumptions on the structural response. The procedure was benchmarked using a bimaterial strip and demonstrated through analyses on a bump chip carrier package assembly. The procedure is conducive to the numerical assessment of fatigue lives of electronic packages.
Purpose – To provide an approach to fleXBGA design and reliability analysis. Design/methodology/approach – A two-dimensional (2D) plane strain finite element analysis model is established to simulate the thermo-mechanical behaviour of fleXBGAs which are subjected to thermo-cyclic loading under different temperature cycling conditions. The model has been used to consider the effects of printed circuit board (PCB) thickness, die size, package size, ball count, pitch and substrate configuration. The Anand constitutive model is adopted to simulate creep and plastic deformation of the solder joints. A fatigue life prediction model based on plastic shear strain range is then applied to predict the fatigue life of different kinds of fleXBGA. Findings – Comparison of fatigue life predictions and experiments show that the maximum prediction errors are mostly within ±50 per cent, and it can be concluded that a smaller die size, a thinner PCB, a smaller solder ball diameter, more balls, a smaller temperature range and a faster ramp rate are all helpful in improving the package fatigue life. Research limitations/implications – Not all properties of the packaging materials are available for design and reliability analysis. Advanced research should be focused on determining the mechanical properties of the packaging materials to improve the analysis accuracy. Practical implications – Design optimisation was used to determine the effect of structural parameters for the fleXBGA assembly on the von Mises equivalent stresses in the solder joints, which is one of the most critical factors for package reliability. The calculation results indicate that the equivalent stress in solder joints can be decreased about 19.7 per cent comparing with the initial structure and the fatigue life can be greatly enhanced. Originality/value – The suggested approach is very useful for fleXBGA assembly design. The reliability of the package can be greatly improved by using the modified geometric parameters.
Solder joints are often the cause of failure in electronic devices, failing due to cyclic creep induced ductile fatigue. This paper will review the modelling methods available to predict the lifetime of SnPb and SnAgCu solder joints under thermo-mechanical cycling conditions such as power cycling, accelerated thermal cycling and isothermal testing, the methods do not apply to other damage mechanisms such as vibration or drop-testing. Analytical methods such as recommended by the IPC are covered, which are simple to use but limited in capability. Finite element modelling methods are reviewed, along with the necessary constitutive laws and fatigue laws for solder, these offer the most accurate predictions at the current time. Research on state-of-the-art damage mechanics methods is also presented, although these have not undergone enough experimental validation to be recommended at present.
The presence and change of thermal stresses in solders, which are used for mounting microelectronic packages on PC-boards,
will eventually lead to material fatigue. The number of cycles to failure can be predicted from empirical relations of the
Coffin–Manson type provided the increments of creep strains and/or energy densities are known, for example, from (rather extensive)
FE-simulations. A special problem arises for newly developed solders for which the Coffin–Manson equations are not known yet
and need to be established first from a combination of FE and costly reliability experiments. In any case the goal of the
industry and research institutions is to replace experiments as much as possible by reliable predictive simulations. However,
FE calculations, which are widely used to perform this task, can—as indicated—be rather time-consuming, due to the huge effort
involved for component meshing, and due to the various non-linear constitutive equations required for the description of creep
in solders and other package materials. In a previous paper (Müller and Hauck in Mech Adv Mater Struct, 15(6):485–489, (2008))
a simple analytical 1D-model was presented that allows computing characteristic damage quantities, such as creep strain and
creep energy density, for different solder materials and different temperature profiles in a very efficient manner, provided
a creep law is known. In this paper the proposed procedure is validated by comparison with results from detailed FE-simulations.
Numerous studies of the reliability of solder joints have been performed. Most life prediction models are limited to a deterministic
approach. However, manufacturing induces uncertainty in the geometry parameters of solder joints, and the environmental temperature
varies widely due to end-user diversity, creating uncertainties in the reliability of solder joints. In this study, a methodology
for accounting for variation in the lifetime prediction for lead-free solder joints of ball grid array packages (PBGA) is
demonstrated. The key aspects of the solder joint parameters and the cyclic temperature range related to reliability are involved.
Probabilistic solutions of the inelastic strain range and thermal fatigue life based on the Engelmaier model are developed
to determine the probability of solder joint failure. The results indicate that the standard deviation increases significantly
when more random variations are involved. Using the probabilistic method, the influence of each variable on the thermal fatigue
life is quantified. This information can be used to optimize product design and process validation acceptance criteria. The
probabilistic approach creates the opportunity to identify the root causes of failed samples from product fatigue tests and
field returns. The method can be applied to better understand how variation affects parameters of interest in an electronic
package design with area array interconnections.
KeywordsFatigue life–ball grid array–solder joint–inelastic shear strain–random variable–probabilistic analysis
The methodology for reliability analysis on the flexible electronics needs to be studied, both in the aspects of simulation and experimental tests. There appears to be very little work in the open literature on the reliability analysis of flexible electronics. In this article, we discuss FEM simulation in mechanical reliability analysis for the design of polyimide based multi-layer flexible printed wire boards. The reliability of the solder joints used to mount packages onto the flexible board under thermal cycling and drop test has been examined. An approximate simulation based approach has been developed to predict the equivalent material property of the multi-layer flexible board. The histogram feature in Adobe Photoshop has been introduced to evaluate the Cu percentage in a signal layer according to the drawing of the signal layer. Simplified FEA model has been built and a number of basic deformation modes have been simulated to retrieve the equivalent material property of a multi-layer flexible board. This approach has been verified by experimental measurement. In addition, it has been pointed out that for a multi-layer flexible board, it is not appropriate to just use the values of volume percentage of the components in a board as the weighting factors to evaluate the equivalent material property parameters of the board. The thermomechanical analysis has been conducted based on the industrial standard formula for solder fatigue life prediction relevant to the conventional PWB and package assembly. The simulation results are compared with experimental test data. The failure mechanism predicted by simulation is consistent with that observed in experimental tests. However, the simulation results of the solder fatigue life are about 1.8 times the test data. Further study is needed on extending or adjusting the conventional formula for solder fatigue life prediction so that it could be used in the case of multi-layer flexible board. The submodeling technique has been used in LS-DYNA to conduct strain and stress analysis on the critical solder during the board level drop test. Simulation results show that the solder shall fail first at the interface to the PWB side during the drop test. The effect of the change of the board thickness on the reliability of the-
solder joints has been investigated. It has been shown that the thinner the board, the smaller the peak values of the Von Mise stress and peeling strain at both the package and PWB sides of the solder joint interfaces. In addition, the correlation of the peeling strain on the critical solder with the bending strain on PWB near the critical solder has been examined. It has been shown that for a specific PWB platform, the more the bending strain on the board, and the more the peeling strain on the solder during drop test. Based on this study, the solder and/or PWB reliability could be efficiently evaluated by the combination of simulation and experimental measurements. The methods discussed in this article shall be useful in conducting reliability analysis of a general multilayer flexible board.
Purpose
The purpose of this paper is to develop simulation models for flexible‐printed circuit boards' flex‐rigid interfaces and to perform experimental tests in the laboratory in order to evaluate the cracking phenomena when these devices are submitted to thermal cycling.
Design/methodology/approach
A device was proposed in order to evaluate the reliability of flex‐rigid interconnections. Thermal cycling tests were performed in an environmental chamber and failure mechanisms investigated using optical and scanning electron microscope techniques. The failure modes were analyzed using computational modelling via the finite element method.
Findings
Through failure analysis, it was observed that device design and thermal expansion/contraction could contribute to the occurrence of high stresses in the copper pad connections. The simulation model proposed was able to identify the critical regions, as they had occurred in the tests. Thus, the qualitative approach may be considered successful enough to be applied in the early stages of design.
Research limitations/implications
The materials proprieties were considered as being linear. Thus, in order to enhance the simulation models to provide a quantitative model for the evaluation of product life, non‐linear (visco‐elastic) behaviour in the material properties and a fracture model should be considered.
Originality/value
Typical causes of cracking failure in electronic devices are related to mechanical stress, moisture, heat from transportation and field use. Thus, finite element analysis is an important tool in order to evaluate the reliability of electronic components regarding these types of loads in the early stages of design.
A wafer level packaging technique has been developed with an inherent advantage of excellent solder joint co-planarity essential for wafer level test and burn-in. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced by stretching the solder joint to achieve high aspect ratio and small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder joints has been found to be considerably better than that of the conventional spherical-shaped solder bumps.
The common structure of a wafer level package (WLP) has direct under-bump-metallization (UBM) and solders bumps attached to a silicon chip. These WLP solder joint connections have a relatively low structural compliance to the silicon chip. Studies have shown that low structural compliance typically result in issues with solder joint reliability and shorter fatigue life under thermal cyclic loading (TMCL). However, the reliability of such WLP assemblies can be improved by introducing a layer of low modulus-based material in between the chip and the UBM/solder bump, also known as a compliant layer. This paper studies the reliability of one instance of a WLP with a compliant layer during TMCL. This study was performed via finite element (FE) modeling and then compared with experimental results.
This investigation presents a detailed design procedure for a lead-free flip chip BGA package which includes solder bump profile prediction, FEM simulation, test vehicle design/fabrication and accelerated thermal cycle (ATC) testing to study the reliability issues of the flip chip packages. The solder joint reliability of a flip chip package depends on the solder materials and the solder geometry. Therefore, this study is divided into two main topics: one is the effect of solder joint material (eutectic 63Sn/37Pb solder and lead-free 96.5Sn/3.5Ag solder) on the solder joint reliability, and the other is the effect of the geometry on the Sn/Ag solder joint reliability. The trends of the ATC testing coincide with the FE analysis results, thus confirming that this analysis-fabrication procedure is feasible for the solder joint geometry and material design of a flip chip BGA package.
An area-distributed surface-mount technology that is suitable for
the solder assembly of VLSI packages onto printed circuit boards is
discussed. This double-bump technology entails the controlled
overlapping of two molten solder bumps on both package and substrate to
form a nearly cylindrical joint. A mechanical standoff is used to
control the final separation between the IC package and the printed
circuit board, and hence the solder joint height and shape. A simple
analytical model, which provides a good understanding of the solder
joint geometries which are achievable and how the joint geometry is
influenced by the principal design and process parameters, was
developed. This assembly technology offers several advantages. It is an
evolutionary development of the well established solder-bump technology,
but it provides a columnlike joint geometry and thus offers potential
for better reliability and higher density. It provides a large process
window because it allows for the inspection of wettability of package
and substrate before assembly, and the assembly process itself involves
the melting together of two molten solder surfaces. It offers the
potential for the electrical inspection of hidden solder joints
Solder joint thermal fatigue failure is a major concern for area array technologies such as flip chip and ball grid array technologies. Solder joint geometry is an important factor influencing thermal fatigue lifetime. In this paper, the effects of solder joint shape and height on thermal fatigue lifetime are studied. Solder joint fatigue lifetime was evaluated using accelerated temperate cycling and adhesion test. Scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), scanning acoustic microscopy (nondestructive evaluation) and optical microscopy were utilized to examine the integrity of the joint and to detect cracks and other defects before and during accelerated fatigue tests. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time.
A three-dimensional (3-D) solder liquid formation model is
developed for predicting the geometry, the restoring force and the
reliability of solder joints in an area array of interconnects [e.g.,
ball grid array (BGA), flip chip] with various pad configurations. In
general, the restoring force and the reliability of the solder joints
depend on the thermal-mechanical behavior of the solder, the geometry of
the solder ball, and the geometry layout/material properties of the
package. A good solder pad configuration could lead to a larger
restoring force along the gravitational direction (a higher standoff
height and a blunter contact angle) with better reliability
characteristics achieved. In this research, a second-reflow-process
approach is applied for the reliability enhancement of typical EGA
assemblies, including PBGA and SuperBGA assemblies. The results show
that for a typical PBGA assembly, the ratio of the enhancement by
application of the second-reflow-process approach is 2.03 based on the
Coffin-Manson criterion and 1.4 based on the energy density based
method, and more significantly, for a typical SuperBGA assembly, it is
7.17 and 2.422, respectively
CHAPTER II Process development for solder joints on power chips
- X S Liu
Liu, X.S. (2001). CHAPTER II Process development for solder joints on
power chips. Retrieved June 30, 2012, from http://scholar.lib.vt.edu/
theses/available/etd-04082001-204805/unrestricted/Chapter-2.PDF.
Reliability of plastic ball grid array assembly in ball grid array technology
- R Darveaux
- K Banerji
- A Mawer
- G Doddy
Darveaux, R.; Banerji, K.; Mawer, A.; and Doddy, G. (1995). Reliability of
plastic ball grid array assembly in ball grid array technology (Edited by J.
H. Lau). New York.
Cracking phenomena on flexible-rigid interfaces in PCBs under thermo cycling loading
- L Arruda
- R Bonadiman
- J Costa
- T Reinikainen
Arruda, L.; Bonadiman R.; Costa, J.; and Reinikainen, T. (2009). Cracking
phenomena on flexible-rigid interfaces in PCBs under thermo cycling
loading. Circuit World, 35(2), 18-22.