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A Current-Mode Dual-Slope CMOS Temperature Sensor
Abstract
A current-mode dual-slope CMOS temperature sensor is presented in this paper. It employs a proportional-to-absolute-temperature (PTAT) current generator, which operates in the sub-threshold region, and a novel temperature-insensitive CMOS inverter, replacing a traditional voltage comparator for power saving, to create PTAT pulsewidth. A binary counter is then utilized to quantize the pulse to a digital output value. It achieves a temperature inaccuracy of -3.39 degrees C-2 degrees C over the common industrial temperature range from -40 degrees C to 85 degrees C for five measured chip samples by utilizing the second-order curvature correction, and an average temperature resolution of 0.259 degrees C/LSB. The conversion rate of the digital output data is 3.5 kSa/s. The 2 V supply voltage is utilized and the total power dissipation is 14.286 mu W, leading to 4.082-nJ/Sa energy efficiency and 0.274-nJ degrees C-2 resolution figure of merit (FoM). It was fabricated by the TSMC 0.35-mu m CMOS process, and the core area occupies 0.0345 mm(2). The utilized dual-slope architecture has the advantages of compactness, power-saving, and high design flexibility.
... Temperature sensors are ubiquitous in a very broad range of applications. Examples include consumer electronic products, portable devices, industries, internet of things (IoT) and so on [1]. Traditional temperature sensors are usually discrete devices such as thermistors, platinum resistors, Pt wire, which are bulky and consume high power [2]. ...
... Nevertheless, many of the existing temperature sensors output the indirect information of temperature, such as counts [1], voltage [5], frequency [6], delay time [7], etc. They need an extra processor to process the output signals (calculation, transformation and average, communication, etc.). ...
In this paper, a digital CMOS temperature sensor based on duty-cycle modulation with digital calibration is presented. The temperature sensor generates a duty-cycle-modulated signal by applying a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current derived from substrate bipolar junction transistors (BJT) to an integrator followed by a window comparator. The duty-cycle-modulated signal is then converted to a digital representation of temperature with two counters. Calibration is performed in the digital domain with three calibration parameters. Dynamic element matching (DEM) and chopping techniques are also used to minimize the errors caused by the component mismatch. The prototype chip is fabricated in a 0.5\,\upmu \hbox {m} CMOS process. The chip area occupies . Measurement results from 11 test chips show that an inaccuracy of -1.1{-}0.5\,^{\circ }\hbox {C} is achieved over the temperature range from to 85\,^{\circ }\hbox {C} after calibration. The 2.5 V supply voltage is utilized and the total power consumption is 0.83 mW at a conversion rate of 0.5 kSa/s with a resolution of 0.0625\,^{\circ }\hbox {C/LSB}, leading to resolution figure of merit (FoM) and accuracy FoM.
... Due to the demand for small, low-dissipation devices, CMOS STSs are highly competitive and have strong appeal. Several CMOS time-domain STSs (TDSTSs) have been developed over the past 10 years [9][10][11][12][13][14][15][16][17][18][19][20]. Compared with CMOS voltage-domain STSs, which have highly favorable accuracy for voltage and process variations [21][22][23][24], CMOS TDSTSs possess the advantages of lower cost and lower circuit complexity. ...
... Compared with CMOS voltage-domain STSs, which have highly favorable accuracy for voltage and process variations [21][22][23][24], CMOS TDSTSs possess the advantages of lower cost and lower circuit complexity. Thus, several TDSTSs have been reported [10][11][12][13][14][15][16][17][18][19][20]. HSPICE simulations are precise but extremely time-consuming, particularly because STS simulations must simulate multiple temperature points to evaluate performance. ...
This study proposes a new behavioral simulator that uses SIMULINK for all-digital CMOS time-domain smart temperature sensors (TDSTSs) for performing rapid and accurate simulations. Inverter-based TDSTSs offer the benefits of low cost and simple structure for temperature-to-digital conversion and have been developed. Typically, electronic design automation tools, such as HSPICE, are used to simulate TDSTSs for performance evaluations. However, such tools require extremely long simulation time and complex procedures to analyze the results and generate figures. In this paper, we organize simple but accurate equations into a temperature-dependent model (TDM) by which the TDSTSs evaluate temperature behavior. Furthermore, temperature-sensing models of a single CMOS NOT gate were devised using HSPICE simulations. Using the TDM and these temperature-sensing models, a novel simulator in SIMULINK environment was developed to substantially accelerate the simulation and simplify the evaluation procedures. Experiments demonstrated that the simulation results of the proposed simulator have favorable agreement with those obtained from HSPICE simulations, showing that the proposed simulator functions successfully. This is the first behavioral simulator addressing the rapid simulation of TDSTSs.
... Some proposed temperature sensors [7]- [20] exhibit the required sensing accuracy for proper DTM. A typical requirement for multi-core systems is a modest absolute inaccuracy of 8°C and a more constrained relative inaccuracy of 3°C [8], [21]. ...
This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit to convert the local temperature into two biasing currents. These are then used to define two oscillation frequencies, whose ratio is proportional to absolute-temperature. Finally, the sensor back-end translates such frequency ratio into the digital temperature code. Thanks to its low-complexity architecture, the proposed design achieves a very compact footprint along with low-power consumption and high accuracy in a wide temperature range. Moreover, thanks to a simple embedded line regulation mechanism, our sensor supports voltage-scalability. The design was prototyped in a 180nm CMOS technology with a 0{\deg}C 100{\deg}C temperature detection range, a very wide supply voltage operating range from 0.6V up to 1.8V and very small silicon area occupation of just 0.021. Experimental measurements performed on 20 test chips have shown very competitive figures of merit, including a resolution of 0.24{\deg}C, an inaccuracy of 1.4{\deg}C, a sampling rate of about 1.5kHz and an energy per conversion of 1.06nJ at 30{\deg}C.
... However, they are susceptible to process variation which often require an expensive two-point calibration scheme to achieve the desired accuracy. Besides, their performance in supply sensitivity tend to be poor [18][19][20][21][22][23][24][25][26][27][28][29][30][31]. This letter presents a compact, low-power temperature sensor front-end based solely on MOSFETs, which is wellsuited for SoC designs. ...
This letter presents an 840µm² 557nW temperature sensor front-end designed for system on chip (SoC) thermal monitoring. The circuit is implemented using MOS transistors exclusively, which enhances its scalability with process technologies and compatibility with digital circuit processes. To address MOSFETs circuit’s process variation issues, a differential voltage readout scheme is employed. Dynamic element matching (DEM) is used to minimize mismatch of the circuit. The sensor is self-referenced, eliminating the need for an external reference voltage. Real-time voltage calibration (RVC) scheme is used to improve the performance of supply sensitivity. It is fabricated using a 55nm process, and the measurement results showed an error of -0.69/0.85℃ across 16 samples over a temperature range of 0℃ to 100℃ with a low-cost one-point calibration at 30℃, while the maximum supply sensitivity is 3.3℃/V.
... The original designs are based on bipolar transistors or p-n diodes of different sizes. One can also find solutions based only on the MOS transistors, which are achieved in CMOS technologies [23][24][25][26][27]. In such sensors, the PTAT voltage source consists of two n-type metal-oxidesemiconductor (NMOS) transistors, as presented in Figure 1. ...
This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied.
... Some proposed temperature sensors [7]- [20] exhibit the required sensing accuracy for proper DTM. A typical requirement for multi-core systems is a modest absolute inaccuracy of 8°C and a more constrained relative inaccuracy of 3°C [8], [21]. ...
This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit to convert the local temperature into two biasing currents. These are then used to define two oscillation frequencies, whose ratio is proportional to absolute-temperature. Finally, the sensor back-end translates such frequency ratio into the digital temperature code. Thanks to its low-complexity architecture, the proposed design achieves a very compact footprint along with low-power consumption and high accuracy in a wide temperature range. Moreover, thanks to a simple embedded line regulation mechanism, our sensor supports voltage-scalability. The design was prototyped in a 180nm CMOS technology with a 0
^{\circ }\text{C}\,\,-100\,\,^{\circ }\text{C}
temperature detection range, a very wide supply voltage operating range from 0.6V up to 1.8V and very small silicon area occupation of just 0.021mm
2
. Experimental measurements performed on 20 test chips have shown very competitive figures of merit, including a resolution of 0.24 °C, an inaccuracy of
, a sampling rate of about 1.5kHz and an energy per conversion of 1.06nJ at 30 °C.
A temperature sensor plays an important role in modern high-performance processing chips. A temperature sensing core with a high sensing accuracy is proposed in this article to meet the increasing demand for on-chip thermal monitoring. A comprehensive analysis of the thermal characteristics in subthreshold current is presented to achieve optimal sensing accuracy. The thermal information contained in subthreshold current is converted into a frequency which can be easily digitized in processing chips. The dynamic offset compensation (DOC) method is proposed to improve the supply sensitivity. In addition, small area and low power are also achieved due to its simple structure and low working current. The sensor is designed and implemented in the standard 0.153-
CMOS technology. After a two-point calibration and systematic error removal (SER), the proposed sensor has a measuring inaccuracy of +0.57
(
) within the temperature range of
-40\,\,^{\circ }\text{C}\sim
120 °C. The occupied area and power consumption of the sensor are only
and
, respectively. With the help of DOC, the sensor can achieve a supply sensitivity of 2.1 °C/V. This combination of high accuracy, small area, and low energy consumption makes this sensor suitable for on-chip dense thermal monitoring applications.
This paper presents a subthreshold-leakage-current-based fully CMOS temperature-to-digital converter with high accuracy and supply rejection. The subthreshold current ratio is constructed by different channel lengths of the same MOSFET type, providing high accuracy and less corner dependence. In addition, the supply sensitivity is enhanced by the proposed subthreshold-leakage-current-based sensing element (SE) and the frequency ratio of two identical currents to frequency converters (CFCs). The prototype was implemented in a 180nm CMOS process. It achieves an inaccuracy of ±0.8°C (
) from 0°C to 100°C after two-point calibration with a resolution of 120mK. Over a wide supply range from 0.8V to 1.6V, the temperature sensor shows a supply sensitivity of 0.9°/V at 30°C. Over the temperature range of 0–100°C, the power supply sensitivity is smaller than 3.4°C/V. Operating at 1V, the sensor has a power consumption of 20nW at 30°C, leading to an FoM of 14.4 pJ
.
In this paper, a highly accurate, fully digital temperature sensor with a curvature correction scheme is proposed. Conventional analog temperature sensors are complex and require a large area. Digital temperature sensors are simple with small area, but they have large inaccuracies due to process variations and curvature errors. In particular, curvature errors become more severe as the technology scales down. Thus, a highly accurate curvature correction method is proposed that can be used even in the latest technology nodes. The proposed curvature correction method achieves lower temperature errors with a smaller area than the conventional curvature correction method by using a simple correction. A temperature error that occurs up to 17 °C before the curvature correction is reduced to a range of -0.6 °C to +0.8 °C after the curvature correction. In addition, the measurement results indicate that the resolution is 0.09 °C /bit in the temperature range from 0 °C to 100 °C. The implementation in 14 nm technology node Xilinx ZCU102 field-programmable gate arrays proves that the proposed temperature sensor is very cost effective, while using only 85 slices. Compared with previous digital temperature sensors, the proposed temperature sensor achieves the smallest error and uses the smallest number of hardware resources while being implemented in a state-of-the-art technology node.
A novel direct resistive-sensor-to-digital readout circuit is presented, which achieves 16.1-bit ENOB while being very compact and robust. The highly digital time-based architecture employs a single voltage-controlled oscillator (VCO), counter, and digital feedback loop for the readout of an external single-ended highly nonlinear resistive sensor, such as an NTC thermistor. In addition to the inherent first-order noise shaping due to the oscillator, the second loop in SMASH configuration creates second-order noise shaping. Fabricated in 180-nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1-ms conversion time and consumes only 171 μW, resulting in an excellent 2.4-pJ/c.s. FOMW for a resistive sensor interface while occupying only 0.064 mm². The specific closed-loop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from -40°C to 125°C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3°C is achieved with only one-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high electromagnetic interference (EMI) immunity at the sensor node is demonstrated as well.
Comparators are very important circuits that can be found in a variety of applications, especially comparators whose reference level can be controlled. In this paper, a voltage‐controlled comparator whose reference voltage is controlled by a control voltage and a programmable comparator whose reference voltage is controlled by an input bit pattern are presented. These two comparators are analyzed quantitatively. The performance of the two proposed comparators is verified by simulation using the Berkeley predictive‐technology models (BPTM) of the 45‐, 32‐, 22‐, and 16‐nm complementary metal‐oxide semiconductor (CMOS) technologies with power‐supply voltages, VDD, of 1, 0.9, 0.8, and 0.7 V, respectively. The proposed controlled comparator is compared with the conventional latch‐type comparator from the points of view of the response time, the output amplitude, and the power consumption.
The Internet of Things (IoT) is emerging as one of the major trends for the next evolution of the Internet, where bil-lions of physical objects or things (including but not limited to humans) will be connected over the Internet, and a vast amount of information data will be shared among them. However, the cur-rent Internet was built on a host-centric communication model, which was primarily designed for meeting the demand of pair-wise peer-to-peer communications and cannot well accommodate var-ious advanced data-centric services boosted by the IoT in which users care about content and are oblivious to locations where the content is stored. In this paper, we propose a novel architecture for the future Internet based on information-centric networking (ICN), which is called DataClouds, to better accommodate data-centric services. Different from existing ICN-based architectures, we take the sharing nature of data-centric services under the IoT into consideration and introduce logically and physically formed communities as the basic building blocks to construct the network so that data could be more efficiently shared and disseminated among interested users. We also elaborate on several fundamen-tal design challenges for the Internet under this new architecture and show that DataClouds could offer more efficient and flexible solutions than traditional ICN-based architectures. Index Terms—Data-centric services, information-centric net-working (ICN), Internet architecture, Internet of Things (IoT).
Increasing population density in urban centers demands adequate provision of services and infrastructure to meet the needs of city inhabitants, encompassing residents, workers, and visitors. The utilization of information and communications technologies to achieve this objective presents an opportunity for the development of smart cities, where city management and citizens are given access to a wealth of real-time information about the urban environment upon which to base decisions, actions, and future planning. This paper presents a framework for the realization of smart cities through the Internet of Things (IoT). The framework encompasses the complete urban information system, from the sensory level and networking support structure through to data management and Cloud-based integration of respective systems and services, and forms a transformational part of the existing cyber-physical system. This IoT vision for a smart city is applied to a noise mapping case study to illustrate a new method for existing operations that can be adapted for the enhancement and delivery of important city services.
We present an ultra-low power temperature sensor embedded in the passive RFID tag using the TSMC 1P6M 0.18 standard CMOS process. Substrate parasitic NPN bipolar pair is exploited to generate the temperature dependent current signals for thermal sensing. A time-domain readout scheme which has high immunity to the on-chip resistor, capacitor and clock frequency process-voltage-temperature (PVT) spreads is further proposed. Measurement results of the embedded sensor within the tag system shows a sensing accuracy of (3sigma) from to 60 after one-point calibration at 20, with a sensing resolution of 0.3 and a sampling rate of 68 samples per second. The embedded sensor draws 0.35 from a 1 V supply at room temperature and occupies a chip area of 0.14 .
We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.
This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.
Mutual compensation of mobility and threshold voltage temperature
variations may result in a zero temperature coefficient bias point of a
MOS transistor. The conditions under which this effect occurs, and
stability of this bias point are investigated. Possible applications of
this effect include voltage reference circuits and temperature sensors
with linear dependence of voltage versus temperature. The theory is
verified experimentally investigating the temperature behavior of a
simple voltage reference circuit realized in 0.35 μm CMOS process
The low cost and direct digital output of CMOS smart temperature sensors are important advantages compared to conventional temperature sensors. This book addresses the main problem that nevertheless prevents widespread - plication of CMOS smart temperature sensors: their relatively poor absolute accuracy. Several new techniques are introduced to improve this accuracy. The effectiveness of these techniques is demonstrated using three prototypes. ? The ?nal prototype achieves an inaccuracy of±0.1 C over the military t- perature range, which is a signi?cant improvement in the state of the art. Since smart temperature sensors have been the subject of academic and industrial research for more than two decades, an overview of existing knowledge and techniques is also provided throughout the book. Inthisintroductorychapter,themotivationandobjectivesofthisworkare- scribed. ThisisfollowedbyareviewofthebasicoperatingprinciplesofCMOS smart temperature sensors, and a brief overview of previous work. The ch- lenges are then described that need to be met in order to improve the accuracy of CMOS smart temperature sensors while maintaining their cost advantage. Finally, the structure of the rest of the book is introduced.
In CMOS technology, BJT-based sensors are usually the temperature sensors of choice due to their decent accuracy after a single temperature trimming, e.g. ± 0. 2∘C (3σ) over the military temperature range: − 55∘C to 125∘C [1–3]. They also achieve low supply-sensitivity, typically in the order of 0. 1∘C/V. However, BJT-based sensors typically require supply voltages above 1V, since VBE will be about 0.8V at − 55∘C and some headroom is required for the current source (often cascoded) that biases the BJT. This restricts the use of such sensors in battery-powered systems, and also restricts the temperature range of implementations in nanometer CMOS [4]. However, from an energy-efficiency perspective, a lower VDD value is preferred.
This paper presents a precision BJT-based temperature sensor implemented in standard CMOS. Its interface electronics consists of a continuous-time duty-cycle modulator [1], whose output can be easily interfaced to a microcontroller, rather than the discrete-time ΔΣ modulators of most previous work [2-4]. This approach leads to high resolution (3mK in a 2.2ms measurement time) and high energy efficiency, as expressed by a resolution FoM of 3.6pJK2, which is a 3× improvement on the state of the art [4,5]. By employing chopping, dynamic element matching and a single room temperature trim, the sensor also achieves a spread of less than ±0.15°C (3σ) from -45 to 130°C.
This paper describes the design of a low power, energy-efficient CMOS smart temperature sensor intended for RFID temperature sensing. The BJT-based sensor employs an energy- efficient 2nd-order zoom ADC, which combines a coarse 5-bit SAR conversion with a fine 10-bit ΔΣ conversion. Moreover, a new integration scheme is proposed that halves the conversion time, while requiring no extra supply current. To meet the stringent cost constraints on RFID tags, a fast voltage calibration technique is used, which can be carried out in only 200 msec. After batch calibration and an individual room-temperature calibration, the sensor achieves an inaccuracy of ±0.15°C (3σ) from -55°C to 125°C . Over the same range, devices from a second lot achieved an inaccuracy of ±0.25°C (3σ) in both ceramic and plastic packages. The sensor occupies 0.08 mm
2
in a 0.16 μm CMOS process, draws 3.4 μA from a 1.5 V to 2 V supply, and achieves a resolution of 20 mK in a conversion time of 5.3 msec. This corresponds to a minimum energy dissipation of 27 nJ per conversion.
MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, a MEMS-based programmable oscillator is presented which achieves better than +/-0.5-ppm frequency stability from -40 degrees C to 85 degrees C and less than 1-ps (rms) integrated phase noise (12 kHz to 20 MHz). A key component of this system is a thermistor-based temperature-to-digital converter (TDC) which enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high-resolution tunable reference resistor based on a switched-capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. The TDC achieves 0.1-mK (rms) resolution within a 5-Hz bandwidth while consuming only 3.97mA for all analog and digital circuits at 3.3-V supply in 180-nm CMOS.
This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 degrees C/LSB and the maximum inaccuracy of 20 measured samples is less than +/- 1.5 degrees C over a temperature range of 0 degrees C similar to 110 degrees C. The entire block occupies 0.008 mm(2) in 65 nm CMOS and consumes 500 mu W at a conversion rate of 469 kS/s.
In this paper, a low-power CMOS smart temperature sensor is presented. The temperature information extracted using substrate PNP transistors is digitized with a resolution of 0.03 degrees C using a precision switched-capacitor (SC) incremental Delta Sigma A/D converter. After batch calibration, an inaccuracy of +/- 0.25 degrees C (+/- 3 sigma) from -70 degrees C to 130 degrees C is obtained. This represents a two-fold improvement compared to the state-of-the-art. After individual calibration at room temperature, an inaccuracy better than +/- 0.1 degrees C over the military temperature range is obtained, which is in-line with the state-of-the-art. This performance is achieved at a power consumption of 65 mu W during a measurement time of 100 ms, by optimizing the power/inaccuracy tradeoffs, and by employing a clock frequency proportional to absolute temperature. The latter ensures accurate settling of the SC input stage at low temperatures, and reduces the effects of leakage currents at high temperatures.
We report a 39 μm × 27 μm on-chip temperature sensor which uses the temperature-dependent reverse-bias leakage current of a lateral silicon on insulator (SOI) CMOS p-n diode to monitor the thermal profile of a 32-nm microprocessor core. In this sensor, the diode junction capacitance is first charged to a fixed voltage. Subsequently, the diode capacitance is allowed to self-discharge through its temperature-dependent reverse-bias current. Next, by using a time-to-digital-converter circuit, the discharge voltage is converted to a temperature-dependent time pulse, and finally, its width is measured by using a digital counter. This compact temperature sensor demonstrates a 3σ measurement inaccuracy of ±1.95°C across the 5°C-100°C temperature range while consuming only 100 μW from a single 1.65-V supply.
Because temperature variations significantly affect the performance and reliability of highly integrated chips, the thermal management of such chips is an important issue. In this paper, a time-domain process variation calibrated temperature sensor is proposed for on-chip thermal management. For a suitable on-chip implementation, the digitally converted temperature-dependent time signal is used to reduce the area and power consumption of the chip. The proposed temperature sensor is fabricated using a 0.13- μm CMOS technology and has an active area of 0.031 mm2. Measurement results show an energy consumption of 0.67 nJ/conversion at a 430 kHz conversion rate, with 1.2 V supply voltage. Using one-point calibration, the sensing error is found to range from -0.63°C to 1.04°C over a temperature range of 20°C to 120°C.
This paper presents an economical time-domain CMOS smart temperature sensor with only one delay line. With the use of a path selection circuit, the delay line was used to first sense the temperature, to generate a pulse with a width proportional to absolute temperature (PTAT). The original delay line was then reused to measure the PTAT pulse. Final digital code conversion was fulfilled using a simple counter. Compared with former work with two delay lines, the proposed work with the novel structure can reduce one delay line to lower the circuit area. The proposed circuit was fabricated in a TSMC CMOS 0.35- μm 2P4M digital process, and had an extremely small chip area of 0.025 mm2, which is currently the best size among smart temperature sensors that has ever been reported when considering the CMOS process. The achieved measurement errors for eight chips are within -0.8°C-1.0 °C after two-point calibration over a 0 °C-100 °C temperature range. The effective resolution is measured to be 0.2 °C, and the power consumption is 1.5 μW at a sampling rate of 10 samples per second.
Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. We propose an on-chip CMOS thermometer specifically designed for controlling the refresh period of a DRAM. This thermometer includes a novel temperature sensor which has been implemented and integrated into an LPDDR2 chip. The LPDDR2 chip is fabricated in a 44-nm DRAM process. The sensor has a temperature sensitivity of -3.2 mV/°C, over a range of 0°C to 110°C. Its resolution is 1.94°C and is only limited by the 6.2-mV step of the associated resistor ladder not by its own design. The linearity of the sensor permits one-point calibration, after which the errors in 61 sample circuits ranged between -1.42°C and +2.66°C. The sensor has an active area of 0.001725 mm2 and consumes less than 0.36 μW on average with a supply of 1.1 V. At its lowest operating temperature, this thermometer reduces the IDD6 current of the LPDDR2 chip by almost half.
A thermal sensor is proposed for microprocessors, which compares the BJT voltage to a reference by converting both voltages to frequency and dividing the frequencies to result in a digital number. The sensor has an rms resolution of ±0.2C and an area of 0.02 mm2 at the 32-nm process node and 0.006 mm2 at 22 nm, including all digital processing circuitry. The conversion rate is between 2-20 kS/s, which enables it to capture fast transients on the CPU. It consumes 3.8/1.4 mW at 32/22 nm from an unregulated 1.4-V supply. The combination of speed, low power, and area make this sensor appropriate to measure hot-spots in microprocessors.
Despite the increasing use of ICs at very high temperatures (>150°C) in automotive and industrial applications, sensing such temperatures is still mostly done with discrete thermocouples or thermistors. This is because conventional integrated temperature sensors are based on BJTs, which have a strongly process-, stress — and temperature-dependent saturation current (Is). Together with other leakage currents, this leads to rapidly increasing temperature errors at high temperatures: up to ±3.0°C at 200°C [1].
This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain SigmaDelta modulator whose phase-summing node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than plusmn0.7degC (3sigma) over the military range (-55degC to 125degC).
This paper describes a time-domain temperature sensor based on a successive approximation algorithm. Without using any bipolar transistor, a temperature sensor composed of a temperature-dependent delay line (TDDL) is utilized to generate a delay proportional to the measured temperature. A binary-weighted adjustable reference delay line (ARDL) is adopted with an effective delay varied by a SAR control logic to approximate the TDDL delay for output coding. For linearity enhancement, a curvature compensation between both delay lines is invented to achieve the best ever accuracy among inverter-delay-based smart temperature sensors. With two-point calibration, a -0.4°C ˜ +0.6°C inaccuracy (3σ) over a 0°C ˜ 90°C temperature operation range has been measured for 23 test chips. With 10 output bits, the proposed sensor achieves a resolution better than 0.1°C and a chip area of 0.6 mm2 in a TSMC 0.35-μm standard digital CMOS process. The sensor's average current consumption is 11.1 μA at a conversion rate of 2 samples/s.
Delay elements are used in integrated circuits (ICs) to meet design specific timing requirements. Delays are often generated by increasing the input transition times. For long delays, such a signal generally results in prolonged short-circuit current either within the delay element itself or at the subsequent stage, elevating the overall power consumption of the system. In this paper, a novel CMOS semi-static threshold- triggered delay element architecture is proposed, that can also be configured to work with other conventional delay elements, to minimize the short-circuit current over a wide delay range resulting in a predictable output delay and reduced power consumption. The semi-static threshold-triggered delay element is fabricated in a commercial 0.35 µm CMOS technology and comparative results show significant improvements in operating range and power consumption over other well-known delay elements. I. INTRODUCTION
To get rid of the heavy burden of aspect ratio tuning, bias adjustment and porting problem among processes in full-custom or mixed-mode design, a fully digital smart tem- perature sensor realizable with 140 field programmable gate array (FPGA) logic elements was proposed for painless VLSI on-chip integrations. By simply replacing the cyclic delay line with a retriggerable ring oscillator for accuracy enhancement, modifying the gain of time amplifier from fixed to variable for one-point calibration support and adopting a second-order master curve for curvature correction in this paper, the proposed smart temperature sensor can achieve two thirds reduction in circuit size, at least four-fold improvement in power consumption and more than two-fold enhancement in accuracy. To demonstrate the performance under practical process variation, the sensor realized with as few as 48 FPGA logic elements for rapid proto- typing was measured over 0 C to 100 C range for 20 test chips from batches spreading over 4 years. The measured inaccuracy is 0.7 C 0.6 C which is superior to 1.8 C 2.3 C of its full-custom predecessor with a third-order master curve and five test samples from one single batch. The accuracy is even better than those of full-custom sensors with two-point calibration. The conversion rate is around 4.4 kHz and the power consumption can be reduced to 175 nJ per conversion by increasing the number of delay stages in ring oscillator to 4608.
An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ ) and a trimmed inaccuracy of (3σ) over the temperature range from to 125 . This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 from a 1.2-V supply and occupies an area of 0.1 mm
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The electrical characteristics of devices and circuits realized in
CMOS technology on silicon-on-insulator (SOI) substrates and operated at
elevated temperatures are presented and compared with results obtained
using other materials (bulk Si, GaAs, SiC). It is demonstrated that
fully depleted CMOS on SOI is the most suitable process for the
realization of complex electronic circuits to be operated in
high-temperature environments, up to more than 300°C
Extensive measurements of electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces were performed using the field effect conductance technique. It was found that both electron and hole mobilities are practically constant and approximately equal to one half of their respective bulk values up to a surface field of about 1.5 × 105volts/cm, corresponding to about 1012electronic charges/cm2induced in the silicon. At higher fields the inversion layer mobilities begin to decrease slightly. The temperature dependence of inversion layer mobilities follows a T-1.5rule at the upper range of the interval -196 to 200°C, indicating a scattering mechanism similar to lattice scattering. This observation is further supported by the lack of a significant effect of an order-of-magnitude variation in the bulk impurity concentration (1015- 1016cm3) on the inversion layer mobilities. No significant effect of structural and geometrical parameters (such as channel length and shape, oxide type and thickness, and surface charge density) was found on the inversion layer mobilities.
An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C.
A BJT-based CMOS temperature sensor with a 3.6 pJ
- A Heidary
- G Wang
- K Makinwa
- G Meijer
366-kS/s 1.09-nJ 0.0013-mm
- K Kim
- H Lee
- C Kim
A 1.2 V 10 $\mu$ W NPN-based temperature sensor in 65 nm CMOS with an inaccuracy of ±0.2 °C (3 s) from ?70 °C to 125 °C
- sebastiano