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1T-1R pillar-type topological-switching random access memory (TRAM) and data retention of GeTe/Sb 2 Te 3 super-lattice films
... iPCM is a new type of PCM, developed for use as a high speed and low-power-consumption non volatile memory. [12][13][14][15][16] A conventional PCM consists of Ge 2 Sb 2 Te 5 (GST) alloy sandwiched between electrodes. The memory operation is attributed to crystalline-amorphous phase transitions in the GST alloy as shown in Fig. 1(a). ...
... In an actual iPCM, the Sb 2 Te 3 layer in the superlattice is 4 nm thick, which is four times greater than the thickness of a primitive cell in a GeTe= Sb 2 Te 3 superlattice. 12,[14][15][16] Moreover, the GeTe=Sb 2 Te 3 superlattice is grown on a thicker Sb 2 Te 3 layer (5 nm). [14][15][16] Thus, the GeTe layers are sandwiched between thicker Sb 2 Te 3 layer than the primitive cell. ...
... 12,[14][15][16] Moreover, the GeTe=Sb 2 Te 3 superlattice is grown on a thicker Sb 2 Te 3 layer (5 nm). [14][15][16] Thus, the GeTe layers are sandwiched between thicker Sb 2 Te 3 layer than the primitive cell. Table I and Fig. 3 show the lattice constants and optimized structures of doublestacked GeTe=Sb 2 Te 3 superlattices sandwiched between five quintuple layers of Sb 2 Te 3 (QL 5 ). ...
The interfacial phase change memory (iPCM) based on a GeTe/Sb2Te3 superlattice is one of the candidates for future storage class memories. However, the atomic structures of the high and low resistance states (HRS/LRS) remain unclear and the resistive switching mechanism is still under debate. Clarifying the switching mechanism is essential for developing further high-reliability and low-power-consumption iPCM. We propose, on the basis of the results of first-principles molecular dynamics simulations, a mechanism for resistive switching, and describe the atomic structures of the high and low resistance states of iPCM for unipolar switching. Our simulations indicated that switching from HRS to LRS occurs with Joule heating only, while that from LRS to HRS occurs with both hole injection and Joule heating.
... Because of the trade-off limitation between retention and write speed, modifications of GeSbTe and the use of totally different material systems as the PRAM material group have been attempted, as shown in figure 2(b). The modified GST through the use of materials such as N and C improves PRAM retention and speed over the original GST [89,90]. To achieve more speed using less energy, totally new structures such as a GeTe/Sb 2 Te 3 super-lattice (SL) have been proposed. ...
... To overcome these issues, the overall write performance of PRAM has to be improved. As we discussed in section 2, many studies about phase-change materials show great progress and potential, but it takes time for new materials to become prototype level quality [89][90][91][92][93][94]. ...
Neural network technologies have taken center stage owing to their powerful computing capability for supporting deep learning in artificial intelligence. However, conventional synaptic devices such as SRAM and DRAM are not satisfactory solutions for neural networks. Recently, several types of memristor devices have become popular alternatives because of their outstanding characteristics such as scalability, high performance, and non-volatility. To understand the characteristics of memristors, a comparison among memristors has been made, considering both maturity and performance. Magneto-resistance random access memory, phase-change random access memory, and resistive random access memory among the proposed memristors are good candidates as synaptic devices for weight storage and matrix-vector multiplication required in artificial neural networks (ANNs). Moreover, these devices play key roles as synaptic devices in research for bio-plausible spiking neural networks (SNNs) because their distinctive switching properties are well matched for emulating synaptic and neuron functions of biological neural networks. In this paper we review motivation, advantage, technology, and applications of memristor devices for neural networks from practical approaches of ANNs to futuristic research of SNNs, considering the current status of memristor technology.
... The superlattice consists of rhombohedral Sb 2 Te 3 and GeTe 2D crystals that are alternately stacked along the out-of-plane growth axis, <111>. [15,16] This "interfacial phase-change memory" (iPCM) superlattice structure, [16] which is also known as the "topological-switching random-access memory" (TRAM) structure, [17] is designed to promote the vertical displacement of Ge atoms at the heterostructure interface. Even though a lateral motion of the GeTe will transfer in-plane tensile stress to the adjacent GeTe block thus increasing its lattice parameter a; see Figure 1b. ...
... Note that both Bi 2 Te 3 and Bi 2 Se 3 are topological insulators and may allow new memory concepts such as TRAM. [17] ...
Van der Waals heterostructure superlattices of Sb2 Te1 and GeTe are strain engineered to promote switchable atomic disordering, which is confined to the GeTe layer. Careful control of the strain in the structures presents a new degree of freedom to design the properties of functional superlattice structures for data storage and photonics applications.
... Scientific RepoRts | 5:12612 | DOi: 10.1038/srep12612 ...
... The corresponding energy barriers are listed in Table 2. The overall energy barrier for the whole transition varies from 2.56 eV to 3.10 eV, which is close to the experiment value of 2.3 eV 10 . As the vertical flip motion has by far the larger energy barrier, this will dominate the switching process. ...
We study the switching process in chalcogenide superlattice (CSL) phase-change memory materials by describing the motion of an atomic layer between the low and high resistance states. Two models have been proposed by different groups based on high-resolution electron microscope images. Model 1 proposes a transition from Ferro to Inverted Petrov state. Model 2 proposes a switch between Petrov and Inverted Petrov states. For each case, we note that the main transition is actually a vertical displacement of a Ge layer through a Te layer, followed by a lateral motion of GeTe sublayer to the final, low energy structure. Through calculating energy barriers, the rate-determining step is the displacive transition.
... This improved understanding may eventually lead to improved memory, e.g., by changing materials or programming conditions to come up with a direct programming in a more stable amorphous phase. 2) Solid-to-Solid Phase Transition: A new kind of nonthermal , but charge-injection-driven phase change [43] in the so-called topological RAM (TRAM) [44] has been claimed recently (Fig. 10). The phase transition would occur through small atomic rearrangements in thin superlattices of PCM materials, resulting in solid-to-solid phase transition without melting. ...
... Fig. 10. Schematic of topological switching between crystalline LRS to crystalline LRS in GeTe/Sb 2 Te 5 superlattice PCM materials, by charge-injection-driven movement of the Ge atoms (reproduced with permission from [44]). Fig. 11. ...
This paper addresses the two main resistive switching (RS) memory technologies: phase-change memory (PCM) and redox-based resistive random access memory (ReRAM). It will review the basic concepts, the initial promises, and current state of the art, with focus on possible scaling pathways for low-power operation and dense, true 3-D memory. Recent physical insights and new potential concepts will be discussed.
... RESET current as small as 3 has been demonstrated with / superlattice PCM cell at a SET resistance of 30 [88]. Since its first introduction, device performance of superlattice PCM stacks has been continuously improved, by optimizing the superlattice stack design and by decreasing the cell size [86], [87], [89], [90]. Although the conduction mechanism, switching mechanism, and even the precise multilayer structure are still not fully understood, various physical properties of the superlattice stack such as magnetoelectric property are being explored as well [91], [92]. ...
We survey progress in the PCM field over the past five years, ranging from large-scale PCM demonstrations to materials improvements for high-Temperature retention and faster switching. Both materials and new cell designs that support lower-power switching are discussed, as well as higher reliability for long cycling endurance. Two paths towards higher density are discussed: Through 3D integration by the combination of PCM and 3D-capable access devices, and through multiple bits per cell, by understanding and managing resistance drift caused by structural relaxation of the amorphous phase. We also briefly survey work in the nascent field of brain-inspired neuromorphic systems that use PCM to implement non-Von Neumann computing.
Chalcogenide superlattice (CSL) is one of the emerging material technologies for ultralow-power phase change memories. However, the resistance switching mechanism of the CSL-based device is still hotly debated. Early electrical measurements and recent materials characterizations have suggested that the Kooi-phase CSL is very likely to be the as-fabricated low-resistance state. Due to the difficulty in in situ characterization at atomic resolution, the structure of the electrically switched CSL in its high-resistance state is still unknown and mainly investigated by theoretical modelings. So far, there has been no simple model that can unify experimental results obtained from device-level electrical measurements and atomic-level materials characterizations. In this work, we carry out atomistic transport modelings of the CSL-based device and propose a simple mechanism accounting for its high resistance. The modeled high-resistance state is based on the interfacial SbTe bilayer flipped CSL that has previously been mistaken for the low-resistance state. This work advances the understanding of CSL for emerging memory applications.
In this letter we explore the potential of stoichiometry determination for chalcogenide superlattices with X-ray diffraction. To this end, a set of epitaxial GeTe Sb2Te3 superlattice samples with varyinglayer thickness is sputter-deposited. Kinematic scattering theory is employed to link the average composition with the diffraction features. The observed lattice constants of the superlattice reference unit cell follow Vegard's law, enabling a straight-forward stoichiometry determination.
Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade.
The biological brain has the capability of learning, pattern recognition, processing imprecisely defined data, and executing complex computational tasks. Consisting of 1011 neurons and 1015 synapses as the major computational components, the biological brain is extremely power efficient, massively parallel, structurally plastic, and exceptionally robust against noise and variations (Kuzum et al. Nanotechnology 24:382001, 2013). The question of how to design and build a compact neuromorphic system is a grand challenge for academia and industry. An electronic synaptic device is an essential element in such neuromorphic systems. Among various electronic synapses candidates, nonvolatile memory-based synaptic devices have the highest potential to realize massive parallelism and 3D integration for achieving high function per unit volume. This chapter will focus on synaptic devices based on phase-change memory (PCM). We first review the basics of phase-change synaptic devices: device operation, phase-change materials, conduction mechanism, power consumption, and scaling. We then review the use of PCM synaptic device implementations spanning from single device operation to various array architecture designs in the following sections. The concept of spike-timing-dependent plasticity (STDP), various pulse scheme designs, and pulse programming techniques for plasticity will be explained and compared. Last, we will discuss recent advances in designing PCM synaptic device to achieve lower power consumption and more stable resistance states.
GeSbTe-based chalcogenide superlattice (CSLs) phase-change memories consist of GeSbTe layer blocks separated by van der Waals bonding gaps. Recent high resolution electron microscopy found two types of disorder in CSLs, a chemical disorder within individual layers, and SbTe bilayer stacking faults connecting one block to an adjacent block which allows individual block heights to vary. The disorder requires a generalization of the previous switching models developed for CSL systems. Density functional calculations are used to describe the stability of various types of intra-layer disorder, how the block heights can vary by means of SbTe-based stacking faults and using a vacancy-mediated kink motion, and also to understand the nature of the switching process in more chemically disordered CSLs.
The number of integrated transistors has increased so rapidly that it has become evident that a further increase of the performance is limited by the power dissipation. The future IT and electronics, therefore, require more efficient power-reduction solutions. In the human brain and nerve system, analog signals from sensing orgasms are processed by a network composed of neurons and synapses. This process is slow but very power-efficient because it is done by below-100 mV signal levels. Although near-threshold or sub-threshold operation of digital CMOS circuits would be possible candidates for the future low-power electronics, the operating voltage was not scaled due to the fact that the sub-threshold characteristics of MOSFETs are not scalable. Various parameter variations of the MOSFETs also deteriorate the noise margin. Most of the existing non-volatile memories and switches have problems in operating at low voltages. It is evident that off-chip interface circuits, power delivery- and control-means, such as back-bias, and the protection devices against electrostatic discharge, also need to be integrated. If the power of the chip is greatly reduced, stacked-chip 3D integration could be an efficient solution in the future IT and electronics. © Springer International Publishing Switzerland 2016. All rights are reserved.
The fabrication of topological-switching random-access memory (TRAM), a new type of phase change memory, was investigated. The deposition and etching process technologies of a GeTe/Sb2Te3 superlattice memory cell were developed and micro test structures of TRAM were fabricated. Analysis of the fabricated structures revealed that the electrical properties of TRAM were different from those of conventional phase change memory and the reset voltage of TRAM, 0.6 V, was less than that of PRAM, 1 V. The non-melting behaviors of resistance change in TRAM were clarified via thermal-conductivity measurements and device simulation.
A fabrication process for a pillar memory cell for topological-switching random access memory (TRAM) devices has been developed. The process consists of two processes: dry etching of a GeTe/Sb2Te3 superlattice layer for pillar formation and wet etching for the removal of sidewall deposits of the pillar. With this fabrication process, one-transistor and one-resistor (1T-1R) devices with TRAM were fabricated, and the reset operation was confirmed. The 1T-1R device with TRAM has a reset voltage of 40% that of phase-change random access memory (PRAM) with the same structure as TRAM.
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