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Design and implementation of high-precision variable-gain amplifier with on-chip temperature compensation scheme for MEMS sensors

Authors:
Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for
Sensor Sensitivity and Offset Compensation for MEMS based, Wheatstone Bridge
type, Resistive Smart Sensor
Anupam Dutta
Dept. of Electronics and Electrical Communication
Engineering, IIT Kharagpur, India
E-mail: chinnapatra@yhaoo.co.in
T. K. Bhattacharyya
Dept. of Electronics and Electrical Communication
Engineering, IIT Kharagpur, India
E-mail: tkb@ece.iitkgp.ernet.in
AbstractA fully-analog, on-chip, low input offset, low noise,
variable gain instrumentation amplifier with a new scheme for
nonlinear and dynamic temperature compensation of sensor
sensitivity and offset, is designed in 0.18µm commercial CMOS
process. The system has a scalable system bandwidth up to 5kHz,
a dynamic range of 84dB, and a maximum gain of 104dB. All the
sensor non idealities and CMOS process mismatch have been
incorporated in simulation. Using this interfacing circuit, a smart
MEMS piezoresistive accelerometer has been designed
subsequently.
Keywords - low offset, low noise, instrumentation amplifier,
chopping, auto-zero, accelerometer, smart MEMS, sensor
temperature compensation.
I. INTRODUCTION
With the advent of novel microelectronic fabrication
technologies, the era of highly sensitive, low cost Micro
Electro Mechanical System (MEMS) based sensors have been
stared [1]. Many of these sensors are of piezoresistive, Wheat
Stone Bridge type like accelerometer, pressure sensor, Hall
sensor, strain gauge, various biomedical sensors etc.
Traditionally Wheatstone bridge is being used to reduce sensor
offset. But non standard MEMS fabrication process and
temperature dependency of piezoresistors [2] invite a few
problems.
One of the problems is that, the sensor sensitivity is a direct
function of the bridge bias voltage. As the bias voltage of
commercial CMOS processes are decreasing gradually, this
sensor sensitivity-CMOS scaling trade off is one of the hurdles
preventing MEMS-CMOS integration. Another major problem
is that, the senor sensitivity and offset are nonlinear functions
of temperature and dynamic in nature. These functions are
very much sensor specific and vary with ageing and stress. It
is impossible to find an accurate generalized function for
sensor sensitivity and offset. These sensors can detect very
weak excitation but their output voltage is also very small,
often of the order of few micro volts. This very small output
voltage has to be amplified to a moderate level, so that further
digitization is possible and to make the signal insensitive to
the CMOS circuit offset. Again, majority of the biomedical
and other physical signals have a frequency less then 5kHz.
For that frequency range, 1/f noise is more important than
thermal noise. So, a very high gain, low offset, low noise
CMOS amplifier is needed to amplify the sensor output. The
gradual diminishing of CMOS bias voltage necessitates the
use of variable gain topology to accommodate the total
dynamic range of the sensor. This paper presents a fully on-
chip, completely analog and generic interface circuit that can
solve all the above mentioned problems and makes it easier to
integrate the MEMS sensor with commercially available
CMOS process as a low cost smart MEMS sensor.
Section II discusses the architecture of the sensor and
interfacing circuit. Building blocks of the smart MEMS sensor
are discussed in section III. In section IV, simulation results
are given, followed by conclusion in section V.
II. ARCHITECTURE
The smart MEMS implemented in this paper consists of a
MEMS sensor and an interfacing circuit. The sensor is a uni-
axial, quad beam, piezoresistive accelerometer, designed for
±13g acceleration range and low off-axis sensitivity.
The total interfacing circuit can be divided into two parts.
One part consists of a low offset, low noise, variable gain,
instrumentation amplifier along with a peak detector and a
gain controlling circuit. The other part consists of a novel
circuit for sensor sensitivity and offset temperature
compensation. Without any separate temperature sensing unit,
this circuit can dynamically compensate the nonlinear
temperature dependency of sensor sensitivity and offset.
Timing control block generates all clock signals and a fail-safe
Triple Modular Redundant (TMR) bias generator block
generates all bias voltages and currents. Overall block diagram
of the main amplifier and the sensitivity-offset compensation
circuit have been shown in Fig.1 and Fig.2 respectively.
There are broadly three types of circuit topologies for
dynamic reduction of offset and 1/f noise [3], [4]. It is possible
to combine two or more of these topologies to obtain a
optimized result. Table 1 shows a comparison between these
topologies. There are various hybrid topologies reported for
low offset and 1/f noise, (as low as 100nV input offset [5]) but
all of them have either very low system bandwidth or low
dynamic range [6], [7], [8] .
In this work the main amplifier is a combination of two
well known low offset, low noise topologies, namely chopper
and ping-pong auto-zero. Each of the two parallel branches of
the main amplifier is auto zeroed and the whole amplifier is
put inside a pair of choppers. Chopping frequency is 100kHz
(1/f noise corner frequency of the amplifier is around 1kHz).
The auto-zero technique prevents the amplifier from becoming
saturated due to its own offset, as the input offset of each
amplifier will be multiplied by the close loop gain of that
amplifier. This hybrid implementation lifts the severe
bandwidth limitation of nested chopper amplifier and ping-
Figure 1. Main amplifier block diagram.
Figure 2. Sensitivity- offset temperature
Compensation block diagram.
Table 1. Comparison between different topologies
Topology Band width
Residual
offset
High
frequency
ripple
Time
continuity
Auto Zero No
limitation Higher No Not
continuous
Chopper Limited Lowest High continuous
Chopper
Stabilization
No
limitation Medium Depends continuous
pong auto-zero provides continuous time output (no loss of
information).Each branch consists of four cascaded amplifiers.
First amplifier is a fixed gain OpAmp and the rest are of
variable gain. The input signal is modulated by the input
chopper (Cch is the chopper clock in Fig. 1) and then amplified
by cascaded OpAmps. The output chopper demodulates the
signal back to its original frequency but modulates the offset
and the 1/f noise around 100kHz. The auto-zero switches are
operating at 12.5kHz (Caz in Fig. 1).
Afterwards two types of Low Pass Filters (LPFs) are used
to filter out the modulated offset and 1/f noise. First LPF is a
second order, differential-in-differential-out, continuous time
(using on chip lumped resistances and capacitances) filter with
cutoff frequency 10kHz. which is followed by three stages of
second order, differential-in-differential-out, variable cut-off
frequency Switched Capacitor LPF (SCLPF). The filtered
output is fed to a peak detector circuit (PD). Subsequently, two
bit digital signal is generated by PD and a Finite State
Machine (FSM) is designed to change the gain of the
amplifier. The amplifier is designed for a bandwidth up to
5kHz, and a maximum gain of 104dB, with a dynamic range
of 84dB.
In the 1980’s, temperature dependency of sensor sensitivity
and offset were corrected either by special devices whose
temperature characteristics are complimentary to that of the
original sensor [9] or by modulating the bridge supply [10].
But the compensation was not dynamic and accuracy was very
poor. In the 1990’s, some papers reported the use of a second
passive bridge for compensation [11]. As the piezoresistivity is
a coupled function of stress and temperature, such techniques
had the similar draw backs as those of the 1980’s. Later digital
techniques were used to store sensitivity and offset data and
then compensate the sensor. MAXIM and Microbridge
Technologies Inc. came up with highly accurate interfacing
ICs for piezoresistive sensors, namely the MAX14XX series
[12] and MBSTC-02 [13] respectively. But the non-dynamic
compensation, high cost (of the calibration kit and the IC
itself) and tedious calibration process remained the major
disadvantages. There are also some very unique compensation
methods have been reported like using some calibration
algorithm implemented in 2µm CMOS process [14], by
thermal feedback [15], using indirect readout method [16] and
with some miscellaneous analog signal processing techniques
[17], [18]. But all of them ignore the sensitivity variation
(except [15], whose accuracy is poor) and the compatibility of
MEMS process with small feature size commercial CMOS
process was not addressed at all. Some algorithms are yet to be
implemented in commercial CMOS process (like the
compensation based on ANN algorithm [19]).
In this paper a new, low cost compensation circuit has been
proposed, which is implemented in 0.18µm commercial
CMOS process. This circuit can dynamically compensate the
nonlinear sensitivity and offset temperature dependency with
accuracy comparable with digital EEPROM based methods. In
this compensation scheme a variable current is used to bias the
bridge instead of voltage. This modification breaks the sensor
sensitivity-CMOS scaling trade-off. The sensor sensitivity is
controlled by varying the bridge bias current (Ib) and a
feedback loop keeps the bridge bias voltage (Vb) fixed to a
desired value, which is to be set externally. While Vb is kept
fixed, Ib varies with temperature. The offset correction circuit
determines the offset at the operational temperature. The
accuracy of this circuit is limited by a theoretical limitation.
This accuracy has been improved using a set of 25 external
trimming resistances. The calculated offset is subtracted from
the original input signal at the main amplifier after first stage.
In this system, no separate temperature sensor has been
implemented to measure the operational temperature; rather
various intermediate sensor voltages are judiciously used to
extract the temperature information.
III. 3. BUILDING BLOCKS
A. Sensor:
The accelerometer structure consists of eight boron-
diffused piezoresistors (PZRs), four flexures, a proof mass and
a supporting frame. The flexures support the proof mass. On
each flexure, two PZRs are located at maximum stress regions,
one near the proof mass and other near the frame [20]. The
isometric view with wiring connections of the accelerometer is
shown in Fig. 3. The accelerometer can sense acceleration
along z axis (Fig.3), which is defined as on-axis and the other
two axes are defined as off-axis (x and y axis). These PZRs are
connected to form a Wheatstone bridge for sensing the
acceleration. Change in different resistances for z, x and y axis
acceleration are shown in Fig.4 (a), (b), (c) respectively. Each
PZR is designed to have a nominal resistance of 1.5k and a
PZR sensitivity of 2/g. To obtain 1mv/g sensitivity at 27ºC,
Ib is set at 250µA.
Figure 3. 3-D view of the MEMS piezoresistive Accelerometer.
B. Auto-zero amplifier:
A single stage, folded cascode OpAmp with NMOS input
pair and auto-zero functionality (shown in Fig. 5 [21]) is used
for each of the four stages of each branch. In storing phase of
the auto-zero clock (when Caz is high), the input terminals of
the OpAmp are shorted to the input common mode voltage
and the output offset voltage is stored in the capacitors C1 and
C2. In correcting phase (when Caz is low), the input terminals
are connected to the signal and those two capacitors are
disconnected from respective outputs. Transistors M3 and M4
adjust the current through M7 and M8 depending on the
magnitude and polarity of output offset voltage.
(a) (b) (c)
Figure 4. Change in PZRs due to (a) z axis (b) x axis (c) y axis acceleration.
(Up and down arrow implies increase and decrease in PZRs respectively)
The residual offset after correction is given by:
12
2
11 2
11
offset offset
m
IRO
mm m
VV
G
VGR G GR
=+×
++
Where Voffset1, Gm1 and R are the input referred offset,
transconductance and load impedance of main amplifier
respectively. Voffset2 and Gm2 are the input referred offset and
transconductance of the auxiliary amplifier. The Common
Mode Feedback (cmfb) circuit is used to define the output
common mode voltage.
C. Switched capacitor low pass filter(SCLPF):
Three stages of the same SCLPF have been cascaded. Each
stage has been implemented as shown in Fig. 6. The OpAmp
of third SCLPF is designed to drive a load capacitor up to
40pF (either from a subsequent SAR ADC or from measuring
instrument). Two non-overlapping clocks are used for each of
the SCLPF (clk and clkNO in the Fig. 6). Values of the on-
chip capacitors C1, C2, C3 and C4 are 1pF, 2pF, 375fF and
500fF respectively. The system bandwidth can be varied using
Sel0 and Sel1 bits (Table 2). SCLPF provides a sampled
output, which can be directly interfaced with an ADC,
followed by the interfacing circuit.
D. Peak detector:
A diode and capacitor based PD has been implemented with
off chip RL & CL as shown in Fig. 7. The RLCL product has to
be chosen by user, according to the following relation -
11
10
10 LL
cm
RC
ω
ω
≤≤×
×
Where, ωc is the angular frequency of the acceleration and ωm
is the angular frequency of maximum change of the amplitude
of the acceleration.
Figure 5: Auto-zero amplifier.
PD generates a dc voltage proportional to output voltage
amplitude, which is subsequently compared with the upper
(Vhigh) and lower (Vlow) limits of the output voltage
amplitude. Two bit digital signal (AFH & AFL) is generated and
Table 3 shows the possible combinations.
Figure 6. Switched capacitor low pass filter.
Table 2. System bandwidth selection
Sel0 Sel1 System bandwidth
0 0 5kHz
0 1 1kHz
1 0 200Hz
1 1 10Hz
Figure 7. Peak detector.
E. Gain control circuit:
All gain bands and their corresponding state numbers are
shown in Table 4. Output voltage is limited within 200mV to
1V (peak to peak) for all the gain bands. Signal state diagram
of the gain controlling FSM is shown in Fig. 8. The FSM is
initialized with maximum gain setting (X5 in Fig 8). A 6 bit
digital signal is generated from the FSM, which are used to
change the gain of 2nd, 3rd, 4th stages of the main amplifier.
Table 3. AFH & AFL combinations
AFH A
FL Comment
0 0 Signal is in correct gain band. No action needed.
0 1 Signal in lower gain band. Gain has to be increased.
1 0 Signal is in higher gain band. Gain has to be decreased.
1 1 Physically cannot occur. Don’t care state.
Table 4. Gain bands and gain breakup over 4 stages
State
No
Input Range
(peak to peak)
Total
Gain
Gain breakup
X0 20mVVin>4mV 50 50 x 1 x 1x 1
X1 4mVVin>0.8mV 250 50 x 5 x 1x 1
X2 0.8mVVin>0.16mV 1250 50 x 25 x 1x 1
X3 0.16mVVin>32µV 6250 50 x 25 x 5x 1
X4 32µVVin>6.4µV 31,250 50 x25x 25x 1
X5 6.4µVVin>1.28µV 156,250 50 x 25 x 25x 5
F. Sensor sensitivity compensation circuit:
Sensor sensitivity is a nonlinear function of temperature.
Each of the Wheatstone bridge resistance can be expressed as
Figure 8. State transition diagram for FSM (MSB and LSB of the bits shown
correspond to AFH & AFL respectively).
(
)()()
,S
R
sT R s Tℑ×Γ
Where Rs is the zero stressed resistance at 0ºC,
(
)
s
is the
stress function, and
)
TΓis the temperature function.
From the basic principle of Wheatstone bridge operation, it
can be shown that Vb will be a function of temperature only
and output voltage (Vo) will be a function of both temperature
and stress. Also an additive offset term will be present with the
Vo. Vb and Vo can be expressed respectively as
(
)()()
2
bS b
VT R T ITΓ×
)
(
)
(
)
,2
o S offset actual
VsT R s T V
×Γ+
The sensor sensitivity is given by
()
(
)
() ()
(
)
,2
o
Sbb
ss
V
s
TR TIT V
gg g
∂ℑ ∂ℑ
=
××Γ×
∂∂ ∂
By keeping Vb(T) fixed at Vb(27ºC), it is possible to have a
constant sensitivity i.e.
(
)
0/,27
o
Vgs C∂∂ . A negative
feedback circuit is used to keep Vb fixed. Theoretically, the
error in compensation can be reduced to a very low value
using a high open loop dc gain of the compensation loop. But
in practical implementation, the error is limited by the CMOS
circuit offset. Various offset reduction can be used to reduce
this error.
G. Sensor offset compensation circuit:
Mismatch in the fabricated resistances and temperature
coefficient of the PZR generate a nonlinear temperature
dependent offset. For a Wheatstone bridge driven by Ib the
offset is given by
32 14 3 2 1 4
4
1
()2( )
()
8
offset actual b
n
n
RR RR R R R R R
VIT
RR
=
±Δ + − −
=
±Δ
Where R1=R1f+R2f, R2=R3m+R4m, R3=R1m+R2m, R4=R3f+R4f
and R is the change in resistance due to change in
temperature. At room temperature (27ºC), R is zero. Ib(T) is
the temperature dependent bridge bias current, given by
()()
4
1
42
13 2 3 14 42
1
8
() (27 )
416
n
no
b b
n
n
RR
I
TVC
RR R R RR R R R R R
=
=
⎛⎞
−Δ
⎜⎟
⎝⎠
=
+++ −Δ +Δ
The analog signal processor (ASP) block takes both bridge
output voltages and Vb to compute all four voltages across the
four bridge arm resistances. ASP then calculates Voffset-course =
(VR4+VR2) - (VR1+VR3) , Where VRi denotes voltage across
Ri-th arm resistance. Finally, ASP generates Voffset-course as a
differential output voltage. Voffset-course is given by:
2431 4213 2314 0
4
4213
1
24 31 2 3 1 4 32
4
4213
1
2( ) 4 ( ) () 2
8
() (
()
offset course b
n
n
b
n
n
R
RRR RRRRR RRRR A
VIT
RRRR
RR
RR RR R R R R RR
IT RRRR
R
=
=
⎡⎤
⎛⎞
⎢⎥
⎜⎟
⎛⎞
−±Δ+− +
⎢⎥
⎜⎟
×
⎜⎟
+−
⎢⎥
⎜⎟
⎝⎠
±Δ
⎜⎟
⎢⎥
⎝⎠
⎣⎦
⎡⎤
⎛⎞
⎢⎥
⎜⎟
⎛⎞
−+
⎢⎥
⎜⎟
−×+
⎜⎟
+−
⎢⎥
⎜⎟
⎝⎠
⎜⎟
⎢⎥
⎝⎠
⎣⎦
14
4
1
)()
b
n
n
RR IT
R
=
⎛⎞
⎜⎟
⎜⎟
⎜⎟
⎜⎟
⎝⎠
Where, A0 is the gain of the 1st stage of the main amplifier.
Error in offset estimation is defined as {(Voffset-course
/A0) ~ Voffset-actual)}. The denominator of the second and third
terms of the Voffset-course contains 4
1
n
n
R
=
instead of 4
1
8
n
n
RR
=
±
Δ
.
This approximation causes the error in offset estimation.
Voffset-course has been improved further by using piecewise
linear curve fitting technique. In this technique the total
temperature zone has been divided into 25 sections and a
MATLAB program is used to generate the required gain
values for 25 temperature sections. Externally trimming
resistances are used to set appropriate gain for each of the
temperature sections.
IV. SIMULATION RESULTS
On-axis and off-axis sensitivity (over ±13g) of the
standalone accelerometer (biased with a constant 250µA
current) is shown in Fig. 9. Results show an on-axis sensitivity
of 0.9 mV/g and off-axis sensitivity of 0.8µV/g and 0.7µV/g
(along x and y axis) respectively.
10% mismatch in the input pair (M1-M2), auto-zero pair
(M3-M4) and cmfb pair of each amplifier stage (shown in Fig.
5) has been incorporated to simulate the random offset effect.
The same 10% mismatch is incorporated in the input pairs of
all the LPFs. The sensor PZR mismatch is also taken to be
10% around its nominal value, throughout the simulation. An
acceleration of 1mg amplitude (peak to peak) and 5kHz
frequency is applied to the sensor. Output voltage of the
combined smart sensor with a gain setting of 104 dB is shown
in Fig.10. The Fig. 11 shows the FFT of the output voltage.
The spectrum shows an output offset of 25mV and low
harmonic components.
The sensitivity compensation loop has a UGB of 385kHz,
phase margin of 60º and open loop dc gain of 85.2dB. The
variation of Vb (due to a temperature cycle of ±75ºC around
27ºC and 100mHz frequency) with and without the
compensation loop is shown in Fig. 12. Lower part of Fig.12
shows the variation of Ib around 250µA due to the same
temperature variation. Vb variation with compensation is
within 30µV, which is equivalent to a temperature error of
0.05ºC.
Figure 13 shows the error in offset estimation over a
temperature from -75ºC to +125ºC after course and fine
calibration. Error due to the estimation of Voffset-course varies
from -500µVto 300µV. After piecewise linearization this error
reduces to within ±10µV.
-12 -6 0 6 12
-10
-5
0
5
10
Vout for acceleration along z-axis
Vout for acceleration along y-axis
Vout for acceleration along x-axis
Output voltage in V
Acceleration (g )
Figure 9. On-axis and Off-axis sensitivity of accelerometer.
Figure 10. Smart sensor output voltage corresponding to 1mg, 5kHz
acceleration input.
Figure 11. FFT of the output voltage.
Figure 12. Vb and Ib variation with temperature.
-100 -50 0 50 100
-600
-500
-400
-300
-200
-100
0
100
200
300
400
Error in offset e stimation (uV)
Temperature above and below room temperature (i n celsius)
Error in offset estimation after course calibration
Error in offset estimation after fine calibration
Figure 13. Error in offset estimation.
V. CONCLUSION
This paper presents the implementation of a smart MEMS
accelerometer with a fully analog, low offset, low noise,
variable gain instrumentation amplifier. An input referred
offset less than 200nV (assuming 10% piezoresistor and
CMOS process mismatch) and a low harmonic distortion at the
output voltage have been achieved. A novel scheme for
dynamic and nonlinear compensation of the temperature
dependency of sensor sensitivity and offset is also
accomplished. This scheme can be used for all resistive
Wheatstone bridge type sensors. The sensitivity compensation
error is around 0.05ºC. The error in offset estimation is less
than ±10µV.
ACKNOWLEDGEMENTS
The authors would like to thank National Programme on
Micro and Smart Systems (NPMASS), Govt. of India for
sponsorship.
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... Its variation with MEMS sensor resistance (Fig. 6a) yields an input referred offset (IRO) value (at zero resistance) of ∼2.9 V while exhibiting incremental behavior with increasing sensor resistance. Fig. 6b demonstrates the dependence of the input referred noise spectrum on the MA core sub-blocks where the AZ + CH assisted noise cancellation gives a very low noise floor of ∼45 nV/ √ Hz (at 10 Hz) [37]. The trends seen in percentage relative offset (PRO) and sensitivity (PRS) error over the operating range of temperatures (Fig. 6c) indicate a <1% error in the MEMS sensor output compensation failure by the front-end with the overall amplifier and temperature compensation schemes consuming ∼4 mW in operation. ...
Chapter
MEMS piezoresistive accelerometers are inertial sensors which measure acceleration of the reference frame to which they are attached. These devices provide extremely localized acceleration-induced stress sensing with low noise outputs and have been the subject of academic as well as commercial research for quite a few years. This chapter deals with the basics micromachined piezoresistive accelerometers, tracing their evolution and typical analyses to sensor fabrication and characterization.
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